Index: /trunk/modules/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd =================================================================== --- /trunk/modules/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd (revision 148) +++ /trunk/modules/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd (revision 148) @@ -0,0 +1,25 @@ + +# -*- python -*- + +Module('caba:vci_vdspin_initiator_wrapper', + classname = 'soclib::caba::VciVdspinInitiatorWrapper', + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + parameter.Int('dspin_cmd_width'), + parameter.Int('dspin_rsp_width'), ], + header_files = ['../source/include/vci_vdspin_initiator_wrapper.h', ], + implementation_files = ['../source/src/vci_vdspin_initiator_wrapper.cpp',], + ports = [ + Port('caba:vci_initiator', 'p_vci'), + Port('caba:dspin_output', 'p_dspin_out', dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_dspin_in', dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), ], + uses = [ + Uses('caba:base_module'), + Uses('caba:generic_fifo'), + ], + instance_parameters = [ + parameter.Int('cmd_fifo_depth'), + parameter.Int('rsp_fifo_depth'), ], +) Index: /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h =================================================================== --- /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h (revision 148) +++ /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h (revision 148) @@ -0,0 +1,120 @@ +/* -*- c++ -*- + * File : vci_vdspin_initiator_wrapper.h + * Copyright (c) UPMC, Lip6 + * Author : Alain Greiner + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + */ + +///////////////////////////////////////////////////////////////////////// +// This component performs the protocol translation between VCI & DSPIN, +// and can be used to connect a VCI initiator to a DSPIN network. +// It is implemented as two fully independant sub-components: +// - translation from a VCI CMD to a DSPIN CMD +// - translation from a DSPIN RSP to a VCI RSP +// Each subcomponent contains a FIFO containing DSPIN flits. +// For the DSPIN interfaces, the widths of the CMD & RSP flits +// are defined as template parameters for future evolutions, +// but the VCI to DSPIN translation makes the following assumptions: +// - DSPIN CMD flit width = 40 bits +// - DSPIN RSP flit width = 33 bits +// - VCI address width <= 40 bits +// - VCI data == 32 bits +// - VCI plen == 8 bits +// - VCI srcid <= 14 bits +// - VCI trdid <= 8 bits +// - VCI pktid field not transmitted +// - VCI rerror == 2 bits +//////////////////////////////////////////////////////////////////////// + +#ifndef VCI_VDSPIN_INITIATOR_WRAPPER_H_ +#define VCI_VDSPIN_INITIATOR_WRAPPER_H_ + +#include +#include +#include "caba_base_module.h" +#include "vci_target.h" +#include "generic_fifo.h" +#include "dspin_interface.h" + +namespace soclib { namespace caba { + +template +class VciVdspinInitiatorWrapper + : public soclib::caba::BaseModule +{ + // Command FSM + enum fsm_state_cmd{ + CMD_IDLE, + CMD_BROADCAST, + CMD_RW, + CMD_WDATA, + }; + + // Response FSM + enum fsm_state_rsp{ + RSP_IDLE, + RSP_READ, + }; + +protected: + SC_HAS_PROCESS(VciVdspinInitiatorWrapper); + +public: + // ports + sc_core::sc_in p_clk; + sc_core::sc_in p_resetn; + soclib::caba::DspinOutput p_dspin_out; + soclib::caba::DspinInput p_dspin_in; + soclib::caba::VciTarget p_vci; + + // constructor / destructor + VciVdspinInitiatorWrapper( sc_module_name name, + size_t cmd_fifo_depth, + size_t rsp_fifo_depth); +private: + // internal registers + sc_core::sc_signal r_cmd_fsm; + sc_core::sc_signal r_rsp_fsm; + sc_core::sc_signal > r_rsp_buf; + + // fifos cmd and rsp + soclib::caba::GenericFifo > r_fifo_cmd; + soclib::caba::GenericFifo > r_fifo_rsp; + + // methods systemc + void transition(); + void genMoore(); + +}; + +}} // end namespace + +#endif // VCI_VDSPIN_INITIATOR_WRAPPER_H_ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp =================================================================== --- /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp (revision 148) +++ /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp (revision 148) @@ -0,0 +1,317 @@ +/* -*- c++ -*- + * File : vci_vdspin_initiator_wrapper.cpp + * Copyright (c) UPMC, Lip6 + * Authors : Alain Greiner + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + */ + +#include "../include/vci_vdspin_initiator_wrapper.h" + +namespace soclib { namespace caba { + +#define tmpl(x) template x VciVdspinInitiatorWrapper + +//////////////////////////////////////////////////////////://////////////////////////////// +tmpl(/**/)::VciVdspinInitiatorWrapper(sc_module_name name, + size_t cmd_fifo_depth, + size_t rsp_fifo_depth) + : soclib::caba::BaseModule(name), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_dspin_out("p_dspin_out"), + p_dspin_in("p_dspin_in"), + p_vci("p_vci"), + r_cmd_fsm("r_cmd_fsm"), + r_rsp_fsm("r_rsp_fsm"), + r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), + r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) + { + SC_METHOD (transition); + dont_initialize(); + sensitive << p_clk.pos(); + SC_METHOD (genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); + assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); + assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); + assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); + assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); + assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); + assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); + assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); + + } // end constructor + +///////////////////////// +tmpl(void)::transition() +{ + sc_uint cmd_fifo_data; + bool cmd_fifo_write; + bool cmd_fifo_read; + + sc_uint rsp_fifo_data; + bool rsp_fifo_write; + bool rsp_fifo_read; + + if (p_resetn == false) + { + r_fifo_cmd.init(); + r_fifo_rsp.init(); + r_cmd_fsm = CMD_IDLE; + r_rsp_fsm = RSP_IDLE; + return; + } // end reset + + ///////////////////////////////////////////////////////////// + // VCI command packet to DSPIN command packet + // The VCI packet is analysed, translated, + // and the DSPIN packet is stored in the fifo_cmd + ///////////////////////////////////////////////////////////// + // - A N flits VCI write command packet is translated + // to a N+2 flits DSPIN command. + // - A single flit VCI read command packet is translated + // to a 2 flits DSPIN command. + // - A single flit VCI broadcast packet is translated to + // a 2 flits DSPIN command. + ////////////////////////////////////////////////////////////// + + // cmd_fifo_read + cmd_fifo_read = p_dspin_out.read.read(); + + // r_cmd_fsm, cmd_fifo_write and cmd_fifo_data + switch(r_cmd_fsm) { + case CMD_IDLE: // write first DSPIN flit into fifo_cmd + { + if( p_vci.cmdval && r_fifo_cmd.wok() ) + { + cmd_fifo_write = true; + sc_uint address = (sc_uint)p_vci.address.read(); + sc_uint srcid = (sc_uint)p_vci.srcid.read(); + sc_uint trdid = (sc_uint)p_vci.trdid.read(); + if ( address & 0x3 ) // VCI broacast command + { + r_cmd_fsm = CMD_BROADCAST; + cmd_fifo_data = ((address & 0xFFFFF00000) >> 1) | + (srcid << 5) | (trdid << 1) | 0x0000000001; + } + else // VCI READ or WRITE command + { + r_cmd_fsm = CMD_RW; + cmd_fifo_data = (address >> 1) & 0x788888888E; + } + } + else + { + cmd_fifo_write = false; + } + break; + } + case CMD_BROADCAST: // write second DSPIN flit in case of broadcast + { + if( p_vci.cmdval && r_fifo_cmd.wok() ) + { + cmd_fifo_write = true; + sc_uint data = (sc_uint)p_vci.wdata.read(); + sc_uint be = (sc_uint)p_vci.be.read(); + cmd_fifo_data = (data & 0x00FFFFFFFF) | ((be & 0x3) << 32) | 0x8000000000; + r_cmd_fsm = CMD_IDLE; + } + else + { + cmd_fifo_write = false; + } + break; + } + case CMD_RW: // write second DSPIN flit in case of read/write + { + if( p_vci.cmdval && r_fifo_cmd.wok() ) + { + cmd_fifo_write = true; + sc_uint srcid = (sc_uint)p_vci.srcid.read(); + sc_uint trdid = (sc_uint)p_vci.trdid.read(); + sc_uint cmd = (sc_uint)p_vci.cmd.read(); + sc_uint plen = (sc_uint)p_vci.plen.read(); + sc_uint be = (sc_uint)p_vci.be.read(); + cmd_fifo_data = ((be & 0xF) << 1) | + ((trdid & 0xFF) << 5) | + ((plen & 0xFF) << 13) | + ((cmd & 0x3) << 23) | + ((srcid & 0x3FFF) << 25) | + 0x1000000000; + if( (cmd == vci_param::CMD_READ) || + (cmd == vci_param::CMD_LOCKED_READ) ) r_cmd_fsm = CMD_IDLE; + else r_cmd_fsm = CMD_WDATA; + } + else + { + cmd_fifo_write = false; + } + break; + } + case CMD_WDATA: + { + if( p_vci.cmdval && r_fifo_cmd.wok() ) + { + cmd_fifo_write = true; + sc_uint data = (sc_uint)p_vci.wdata.read(); + sc_uint be = (sc_uint)p_vci.be.read(); + cmd_fifo_data = (data & 0xFFFFFFFF) | ((be & 0xF) << 32); + if ( p_vci.eop.read() ) + { + cmd_fifo_data = cmd_fifo_data | 0x8000000000; + r_cmd_fsm = CMD_IDLE; + } + } + else + { + cmd_fifo_write = false; + } + break; + } + } // end switch r_cmd_fsm + + // fifo_cmd + if((cmd_fifo_write == true) && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } + if((cmd_fifo_write == true) && (cmd_fifo_read == true)) { r_fifo_cmd.put_and_get(cmd_fifo_data); } + if((cmd_fifo_write == false) && (cmd_fifo_read == true)) { r_fifo_cmd.simple_get(); } + + ////////////////////////////////////////////////////////////// + // DSPIN response packet to VCI response packet + // The DSPIN packet is stored in the fifo_rsp + // The FIFO output is analysed and translated to a VCI packet + ////////////////////////////////////////////////////////////// + // - A N+2 flits DSPIN read response packet is translated + // to a N flits VCI response. + // - A single flit DSPIN write response packet is translated + // to a single flit VCI response. + ////////////////////////////////////////////////////////////// + + // rsp_fifo_write, rsp_fifo_data + rsp_fifo_write = p_dspin_in.write.read(); + rsp_fifo_data = p_dspin_in.data.read(); + + // r_rsp_fsm, rsp_fifo_read + switch(r_rsp_fsm) { + case RSP_IDLE: + { + if( r_fifo_rsp.rok() && p_vci.rspack ) + { + rsp_fifo_read = true; + if ( (r_fifo_rsp.read() & 0x000020000) == 0 ) // read response + { + r_rsp_buf = r_fifo_rsp.read(); + r_rsp_fsm = RSP_READ; + } + } + else + { + rsp_fifo_read = false; + } + + break; + } + case RSP_READ: + { + if( r_fifo_rsp.rok() && p_vci.rspack ) + { + rsp_fifo_read = true; + if ( (r_fifo_rsp.read() & 0x100000000) ) r_rsp_fsm = RSP_IDLE; + } + else + { + rsp_fifo_read = false; + } + break; + } + } // end switch r_rsp_fsm + + // fifo_rsp + if((rsp_fifo_write == true) && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } + if((rsp_fifo_write == true) && (rsp_fifo_read == true)) { r_fifo_rsp.put_and_get(rsp_fifo_data); } + if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } + +}; // end transition + +////////////////////// +tmpl(void)::genMoore() +{ + // VCI CMD interface + if ( r_cmd_fsm.read() == CMD_IDLE ) p_vci.cmdack = false; + else p_vci.cmdack = r_fifo_cmd.wok(); + + // VCI RSP interface + if ( r_rsp_fsm.read() == RSP_IDLE ) + { + if ( r_fifo_rsp.rok() && (r_fifo_rsp.read() & 0x000020000) ) // valid RSP WRITE + { + p_vci.rspval = true; + p_vci.rdata = 0; + p_vci.rsrcid = (sc_uint)((r_fifo_rsp.read() & 0x0FFFC0000) >> 18); + p_vci.rtrdid = (sc_uint)((r_fifo_rsp.read() & 0x00000FF00) >> 8); + p_vci.rpktid = 0; + p_vci.rerror = (sc_uint)((r_fifo_rsp.read() & 0x000030000) >> 16); + p_vci.reop = true; + } + else + { + p_vci.rspval = false; + } + } + else // Next flit of a RSP READ + { + if ( r_fifo_rsp.rok() ) // valid RSP READ + { + p_vci.rspval = true; + p_vci.rdata = (sc_uint<4*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFF); + p_vci.rsrcid = (sc_uint)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); + p_vci.rtrdid = (sc_uint)((r_rsp_buf.read() & 0x00000FF00) >> 8); + p_vci.rpktid = 0; + p_vci.rerror = (sc_uint)((r_rsp_buf.read() & 0x000030000) >> 16); + p_vci.reop = ((r_fifo_rsp.read() & 0x100000000) == 0x100000000); + } + else + { + p_vci.rspval = false; + } + } + + // DSPIN_OUT interface + p_dspin_out.write = r_fifo_cmd.rok(); + p_dspin_out.data = r_fifo_cmd.read(); + + // DSPIN_IN interface + p_dspin_in.read = r_fifo_rsp.wok(); + +}; // end genMoore + +}} // end namespace + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /trunk/modules/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd =================================================================== --- /trunk/modules/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd (revision 148) +++ /trunk/modules/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd (revision 148) @@ -0,0 +1,25 @@ + +# -*- python -*- + +Module('caba:vci_vdspin_target_wrapper', + classname = 'soclib::caba::VciVdspinTargetWrapper', + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + parameter.Int('dspin_cmd_width'), + parameter.Int('dspin_rsp_width'), ], + header_files = ['../source/include/vci_vdspin_target_wrapper.h', ], + implementation_files = ['../source/src/vci_vdspin_target_wrapper.cpp',], + ports = [ + Port('caba:vci_initiator', 'p_vci'), + Port('caba:dspin_output', 'p_dspin_out', dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_dspin_in', dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), ], + uses = [ + Uses('caba:base_module'), + Uses('caba:generic_fifo'), + ], + instance_parameters = [ + parameter.Int('cmd_fifo_depth'), + parameter.Int('rsp_fifo_depth'), ], +) Index: /trunk/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h =================================================================== --- /trunk/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h (revision 148) +++ /trunk/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h (revision 148) @@ -0,0 +1,124 @@ +/* -*- c++ -*- + * File : vci_vdspin_target_wrapper.h + * Copyright (c) UPMC, Lip6 + * Author : Alain Greiner + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + */ + +///////////////////////////////////////////////////////////////////////// +// This component performs the protocol translation between VCI & DSPIN, +// and can be used to connect a VCI target to a DSPIN netnork. +// It is implemented as two fully independant sub-components: +// - translation from a DSPIN CMD to a VCI CMD +// - translation from a VCI RSP to a DSPIN RSP +// Each subcomponent contains a FIFO containing DSPIN flits. +// For the DSPIN interfaces, the widths of the CMD & RSP flits +// are defined as template parameters for future evolutions, +// but the VCI to DSPIN translation makes the following assumptions: +// - DSPIN CMD flit width == 40 bits +// - DSPIN RSP flit width == 33 bits +// - VCI address width <= 40 bits +// - VCI data == 32 bits +// - VCI plen == 8 bits +// - VCI srcid <= 14 bits +// - VCI trdid <= 8 bits +// - VCI pktid field not transmitted +// - VCI rerror == 2 bits +//////////////////////////////////////////////////////////////////////// + +#ifndef VCI_VDSPIN_TARGET_WRAPPER_H_ +#define VCI_VDSPIN_TARGET_WRAPPER_H_ + +#include +#include +#include "caba_base_module.h" +#include "vci_initiator.h" +#include "generic_fifo.h" +#include "dspin_interface.h" + +namespace soclib { namespace caba { + + +template +class VciVdspinTargetWrapper + : public soclib::caba::BaseModule +{ + + // Command FSM + enum fsm_state_cmd{ + CMD_IDLE, + CMD_BROADCAST, + CMD_RW, + CMD_WDATA, + }; + + // Response FSM + enum fsm_state_rsp{ + RSP_IDLE, + RSP_READ, + RSP_WRITE, + }; + +protected: + SC_HAS_PROCESS(VciVdspinTargetWrapper); + +public: + // ports + sc_core::sc_in p_clk; + sc_core::sc_in p_resetn; + soclib::caba::DspinOutput p_dspin_out; + soclib::caba::DspinInput p_dspin_in; + soclib::caba::VciInitiator p_vci; + + // constructor / destructor + VciVdspinTargetWrapper( sc_module_name name, + size_t cmd_fifo_depth, + size_t rsp_fifo_depth); +private: + // internal registers + sc_core::sc_signal r_cmd_fsm; + sc_core::sc_signal > r_cmd_buf0; + sc_core::sc_signal > r_cmd_buf1; + sc_core::sc_signal r_rsp_fsm; + + // fifos cmd and rsp + soclib::caba::GenericFifo > r_fifo_cmd; + soclib::caba::GenericFifo > r_fifo_rsp; + + // methods systemc + void transition(); + void genMoore(); + +}; + +}} // end namespace + +#endif // VCI_VDSPIN_TARGET_WRAPPER_H_ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /trunk/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp =================================================================== --- /trunk/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp (revision 148) +++ /trunk/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp (revision 148) @@ -0,0 +1,349 @@ +/* -*- c++ -*- + * File : vci_vdspin_target_wrapper.cpp + * Copyright (c) UPMC, Lip6 + * Author : Alain Greiner + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + */ + +#include "../include/vci_vdspin_target_wrapper.h" + +namespace soclib { namespace caba { + +#define tmpl(x) template x VciVdspinTargetWrapper + +//////////////////////////////////////////////////////////://////////////////////////////// +tmpl(/**/)::VciVdspinTargetWrapper(sc_module_name name, + size_t cmd_fifo_depth, + size_t rsp_fifo_depth) + : soclib::caba::BaseModule(name), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_dspin_out("p_dspin_out"), + p_dspin_in("p_dspin_in"), + p_vci("p_vci"), + r_cmd_fsm("r_cmd_fsm"), + r_rsp_fsm("r_rsp_fsm"), + r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), + r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) + { + SC_METHOD (transition); + dont_initialize(); + sensitive << p_clk.pos(); + SC_METHOD (genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); + assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); + assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); + assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); + assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); + assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); + assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); + assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); + + } // end constructor + +///////////////////////// +tmpl(void)::transition() +{ + sc_uint cmd_fifo_data; + bool cmd_fifo_write; + bool cmd_fifo_read; + + sc_uint rsp_fifo_data; + bool rsp_fifo_write; + bool rsp_fifo_read; + + if (p_resetn == false) + { + r_fifo_cmd.init(); + r_fifo_rsp.init(); + r_cmd_fsm = CMD_IDLE; + r_rsp_fsm = RSP_IDLE; + return; + } // end reset + + ///////////////////////////////////////////////////////////// + // VCI response packet to DSPIN response packet. + // The VCI packet is analysed, translated, + // and the DSPIN packet is stored in the fifo_rsp + ///////////////////////////////////////////////////////////// + // - A single flit VCI write response packet is translated + // to a single flit DSPIN response. + // - A N flits VCI read response packet is translated + // to a N+1 flits DSPIN response + // In the RSP_IDLE state, the first DSPIN flit is written + // in fifo_rsp , but no VCI flit is consumed. The VCI flits + // are consumed in the RSP_READ or RSP_WRITE states. + ////////////////////////////////////////////////////////////// + + // rsp_fifo_read + rsp_fifo_read = p_dspin_out.read.read(); + + // r_rsp_fsm, rsp_fifo_write and rsp_fifo_data + switch(r_rsp_fsm) { + case RSP_IDLE: // write first DSPIN flit into rsp_fifo + { + if( p_vci.rspval && r_fifo_rsp.wok() ) + { + bool is_read = ( (p_vci.rerror.read() & 0x2) == 0); + + rsp_fifo_write = true; + rsp_fifo_data = (((sc_uint)p_vci.rsrcid.read()) << 18) | + (((sc_uint)p_vci.rerror.read()) << 16) | + (((sc_uint)p_vci.rtrdid.read()) << 8); + if ( is_read ) + { + r_rsp_fsm = RSP_READ; + } + else + { + rsp_fifo_data = rsp_fifo_data | 0x100000000; + r_rsp_fsm = RSP_WRITE; + } + } + else + { + rsp_fifo_write = false; + } + break; + } + case RSP_READ: // write DSPIN data flit in case of read + { + if( p_vci.rspval && r_fifo_rsp.wok() ) + { + rsp_fifo_write = true; + rsp_fifo_data = ((sc_uint)p_vci.rdata.read()); + if ( p_vci.reop ) + { + rsp_fifo_data = rsp_fifo_data | 0x100000000; + r_rsp_fsm = RSP_IDLE; + } + } + else + { + rsp_fifo_write = false; + } + break; + } + case RSP_WRITE: + { + rsp_fifo_write = false; + if ( r_fifo_rsp.wok() ) r_rsp_fsm = RSP_IDLE; + break; + } + } // end switch r_cmd_fsm + + // fifo_rsp + if((rsp_fifo_write == true) && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } + if((rsp_fifo_write == true) && (rsp_fifo_read == true)) { r_fifo_rsp.put_and_get(rsp_fifo_data); } + if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } + + ////////////////////////////////////////////////////////////// + // DSPIN command packet to VCI command packet + // The DSPIN packet is stored in the fifo_rsp + // The FIFO output is analysed and translated to a VCI packet + ////////////////////////////////////////////////////////////// + // - A 2 flits DSPIN broadcast command is translated + // to a 1 flit VCI broadcast command. + // - A 2 flits DSPIN read command is translated + // to a 1 flit VCI read command. + // - A N+2 flits DSPIN write command is translated + // to a N flits VCI write command. + // The VCI flits are sent in the CMD_RW, CMD_WDATA + // & CMD_BROADCAST states. + // The r_cmd_buf0 et r_cmd_buf1 buffers are used to store + // the two first DSPIN flits (in case of write). + ////////////////////////////////////////////////////////////// + + // cmd_fifo_write, cmd_fifo_data + cmd_fifo_write = p_dspin_in.write.read(); + cmd_fifo_data = p_dspin_in.data.read(); + + // r_cmd_fsm, cmd_fifo_read + switch(r_cmd_fsm) { + case CMD_IDLE: + { + if( r_fifo_cmd.rok() && p_vci.cmdack ) + { + bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1); + + cmd_fifo_read = true; + r_cmd_buf0 = r_fifo_cmd.read(); + if ( is_broadcast ) r_cmd_fsm = CMD_BROADCAST; + else r_cmd_fsm = CMD_RW; + } + else + { + cmd_fifo_read = false; + } + break; + } + case CMD_BROADCAST: + { + if( r_fifo_cmd.rok() && p_vci.cmdack ) + { + cmd_fifo_read = true; + r_cmd_fsm = CMD_IDLE; + } + else + { + cmd_fifo_read = false; + } + break; + } + case CMD_RW: + { + if( r_fifo_cmd.rok() && p_vci.cmdack ) + { + cmd_fifo_read = true; + if ( (r_fifo_cmd.read() & 0x8000000000) ) // read command + { + r_cmd_fsm = CMD_IDLE; + } + else // write command + { + r_cmd_fsm = CMD_WDATA; + r_cmd_buf1 = r_fifo_cmd.read(); + } + } + else + { + cmd_fifo_read = false; + } + break; + } + case CMD_WDATA: + { + if( r_fifo_cmd.rok() && p_vci.cmdack ) + { + cmd_fifo_read = true; + if ( (r_fifo_cmd.read() & 0x8000000000) ) r_cmd_fsm = CMD_IDLE; + } + else + { + cmd_fifo_read = false; + } + break; + } + } // end switch r_cmd_fsm + + // fifo_cmd + if((cmd_fifo_write == true) && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } + if((cmd_fifo_write == true) && (cmd_fifo_read == true)) { r_fifo_cmd.put_and_get(cmd_fifo_data); } + if((cmd_fifo_write == false) && (cmd_fifo_read == true)) { r_fifo_cmd.simple_get(); } + +}; // end transition + +////////////////////// +tmpl(void)::genMoore() +{ + // VCI RSP interface + if ( r_rsp_fsm.read() == RSP_IDLE ) p_vci.rspack = false; + else p_vci.rspack = r_fifo_rsp.wok(); + + // VCI CMD interface + if ( r_cmd_fsm.read() == CMD_IDLE ) + { + p_vci.cmdval = false; + } + else if ( r_cmd_fsm.read() == CMD_BROADCAST ) // VCI CMD broadcast + { + if ( r_fifo_cmd.rok() ) + { + p_vci.cmdval = true; + p_vci.address = (sc_uint)((r_cmd_buf0.read() & 0x7FFFF80000) << 1) | 0x3; + p_vci.cmd = vci_param::CMD_WRITE; + p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFF); + p_vci.be = (sc_uint)((r_fifo_cmd.read() & 0x0F00000000) >> 32); + p_vci.srcid = (sc_uint)((r_cmd_buf0.read() & 0x000007FFE0) >> 5); + p_vci.trdid = (sc_uint)((r_cmd_buf0.read() & 0x000000001E) >> 1); + p_vci.pktid = 0; + p_vci.plen = vci_param::B; + p_vci.eop = true; + } + else + { + p_vci.cmdval = false; + } + } + else if ( r_cmd_fsm.read() == CMD_RW ) // VCI read if eop + { + if ( r_fifo_cmd.rok() & ((r_fifo_cmd.read() & 0x8000000000) == 0x8000000000) ) + { + p_vci.cmdval = true; + p_vci.address = (sc_uint)((r_cmd_buf0.read() & 0x7FFFFFFFFE) << 1); + p_vci.cmd = (sc_uint<2>)((r_fifo_cmd.read() & 0x0001800000) >> 23); + p_vci.wdata = 0; + p_vci.be = (sc_uint)((r_fifo_cmd.read() & 0x000000001E) >> 1); + p_vci.srcid = (sc_uint)((r_fifo_cmd.read() & 0x7FFE000000) >> 25); + p_vci.trdid = (sc_uint)((r_fifo_cmd.read() & 0x0000001FE0) >> 5); + p_vci.pktid = 0; + p_vci.plen = (sc_uint)((r_fifo_cmd.read() & 0x00001FE000) >> 13); + p_vci.eop = true; + } + else + { + p_vci.cmdval = false; + } + } + else if ( r_cmd_fsm.read() == CMD_WDATA ) // VCI write + { + if ( r_fifo_cmd.rok() ) + { + p_vci.cmdval = true; + p_vci.address = (sc_uint)((r_cmd_buf0.read() & 0x7FFFFFFFFE) << 1); + p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000) >> 23); + p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFF); + p_vci.be = (sc_uint)((r_fifo_cmd.read() & 0x0F00000000) >> 32); + p_vci.srcid = (sc_uint)((r_cmd_buf1.read() & 0x7FFE000000) >> 25); + p_vci.trdid = (sc_uint)((r_cmd_buf1.read() & 0x0000001FE0) >> 5); + p_vci.pktid = 0; + p_vci.plen = (sc_uint)((r_cmd_buf1.read() & 0x00001FE000) >> 13); + p_vci.eop = ((r_fifo_cmd.read() & 0x8000000000) == 0x8000000000); + } + else + { + p_vci.cmdval = false; + } + } + + // DSPIN_OUT interface + p_dspin_out.write = r_fifo_rsp.rok(); + p_dspin_out.data = r_fifo_rsp.read(); + + // DSPIN_IN interface + p_dspin_in.read = r_fifo_cmd.wok(); + +}; // end genMoore + +}} // end namespace + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4