Index: /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h =================================================================== --- /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h (revision 149) +++ /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h (revision 150) @@ -66,5 +66,6 @@ CMD_IDLE, CMD_BROADCAST, - CMD_RW, + CMD_READ, + CMD_WRITE, CMD_WDATA, }; @@ -74,4 +75,5 @@ RSP_IDLE, RSP_READ, + RSP_WRITE, }; @@ -105,4 +107,7 @@ void genMoore(); +public: + void print_trace(); + }; Index: /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp =================================================================== --- /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp (revision 149) +++ /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp (revision 150) @@ -95,4 +95,7 @@ // - A single flit VCI broadcast packet is translated to // a 2 flits DSPIN command. + // A DSPIN flit is written in the fifo_cmd in all states + // but a VCI flit is consumed only in the CMD_READ, + // CMD_BROACAST, and CMD_WDATA states. ////////////////////////////////////////////////////////////// @@ -101,4 +104,6 @@ // r_cmd_fsm, cmd_fifo_write and cmd_fifo_data + cmd_fifo_write = false; // default value + switch(r_cmd_fsm) { case CMD_IDLE: // write first DSPIN flit into fifo_cmd @@ -110,20 +115,31 @@ sc_uint srcid = (sc_uint)p_vci.srcid.read(); sc_uint trdid = (sc_uint)p_vci.trdid.read(); - if ( address & 0x3 ) // VCI broacast command + sc_uint cmd = (sc_uint)p_vci.cmd.read(); + + bool is_broadcast = ( (address & 0x3) != 0); + bool is_read = ((cmd == vci_param::CMD_READ) || (cmd == vci_param::CMD_LOCKED_READ)); + + if ( vci_param::N == 40 ) address = address >> 1; + else address = address << (39 - vci_param::N); + + if ( is_broadcast ) // VCI broacast command { r_cmd_fsm = CMD_BROADCAST; - cmd_fifo_data = ((address & 0xFFFFF00000) >> 1) | - (srcid << 5) | (trdid << 1) | 0x0000000001; + cmd_fifo_data = (address & 0x7FFFF80000) | + ((srcid << 5) & 0x000007FFE0) | + ((trdid << 1) & 0x000000001E) | + 0x0000000001; } - else // VCI READ or WRITE command - { - r_cmd_fsm = CMD_RW; - cmd_fifo_data = (address >> 1) & 0x788888888E; + else if (is_read ) // VCI READ command + { + r_cmd_fsm = CMD_READ; + cmd_fifo_data = address & 0x7FFFFFFFFE; + } + else // VCI WRITE command + { + r_cmd_fsm = CMD_WRITE; + cmd_fifo_data = address & 0x7FFFFFFFFE; } } - else - { - cmd_fifo_write = false; - } break; } @@ -135,14 +151,13 @@ sc_uint data = (sc_uint)p_vci.wdata.read(); sc_uint be = (sc_uint)p_vci.be.read(); - cmd_fifo_data = (data & 0x00FFFFFFFF) | ((be & 0x3) << 32) | 0x8000000000; + cmd_fifo_data = (data & 0x00FFFFFFFF) | + ((be << 32) & 0x0300000000) | + 0x8000000000; r_cmd_fsm = CMD_IDLE; } - else - { - cmd_fifo_write = false; - } break; } - case CMD_RW: // write second DSPIN flit in case of read/write + case CMD_READ: // write second DSPIN flit in case of read/write + case CMD_WRITE: { if( p_vci.cmdval && r_fifo_cmd.wok() ) @@ -154,18 +169,22 @@ sc_uint plen = (sc_uint)p_vci.plen.read(); sc_uint be = (sc_uint)p_vci.be.read(); - cmd_fifo_data = ((be & 0xF) << 1) | - ((trdid & 0xFF) << 5) | - ((plen & 0xFF) << 13) | - ((cmd & 0x3) << 23) | - ((srcid & 0x3FFF) << 25) | - 0x1000000000; - if( (cmd == vci_param::CMD_READ) || - (cmd == vci_param::CMD_LOCKED_READ) ) r_cmd_fsm = CMD_IDLE; - else r_cmd_fsm = CMD_WDATA; + cmd_fifo_data = ((be << 1 ) & 0x000000001E) | + ((trdid << 5 ) & 0x0000001FE0) | + ((plen << 13) & 0x00001FE000) | + ((cmd << 23) & 0x0001800000) | + ((srcid << 25) & 0x7FFE000000) ; + if ( p_vci.contig.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000400000 ; + if ( p_vci.cons.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000200000 ; + + if( r_cmd_fsm == CMD_READ ) // read command + { + r_cmd_fsm = CMD_IDLE; + cmd_fifo_data = cmd_fifo_data | 0x8000000000 ; + } + else // write command + { + r_cmd_fsm = CMD_WDATA; + } } - else - { - cmd_fifo_write = false; - } break; } @@ -177,5 +196,7 @@ sc_uint data = (sc_uint)p_vci.wdata.read(); sc_uint be = (sc_uint)p_vci.be.read(); - cmd_fifo_data = (data & 0xFFFFFFFF) | ((be & 0xF) << 32); + cmd_fifo_data = (data & 0x00FFFFFFFF) | + ((be << 32) & 0x0F00000000) ; + if ( p_vci.eop.read() ) { @@ -184,8 +205,4 @@ } } - else - { - cmd_fifo_write = false; - } break; } @@ -202,8 +219,11 @@ // The FIFO output is analysed and translated to a VCI packet ////////////////////////////////////////////////////////////// - // - A N+2 flits DSPIN read response packet is translated + // - A N+1 flits DSPIN read response packet is translated // to a N flits VCI response. // - A single flit DSPIN write response packet is translated // to a single flit VCI response. + // A valid DSPIN flit in the fifo_rsp is always consumed + // in the CMD_IDLE state, but no VCI flit is transmitted. + // The VCI flits are sent in the RSP_READ & RSP_WRITE states. ////////////////////////////////////////////////////////////// @@ -213,35 +233,30 @@ // r_rsp_fsm, rsp_fifo_read + rsp_fifo_read = false; // default value + switch(r_rsp_fsm) { case RSP_IDLE: { - if( r_fifo_rsp.rok() && p_vci.rspack ) + if( r_fifo_rsp.rok() ) { rsp_fifo_read = true; - if ( (r_fifo_rsp.read() & 0x000020000) == 0 ) // read response - { - r_rsp_buf = r_fifo_rsp.read(); - r_rsp_fsm = RSP_READ; - } + r_rsp_buf = r_fifo_rsp.read(); + if ( (r_fifo_rsp.read() & 0x000020000) == 0 ) r_rsp_fsm = RSP_READ; + else r_rsp_fsm = RSP_WRITE; } - else - { - rsp_fifo_read = false; - } - break; } case RSP_READ: { - if( r_fifo_rsp.rok() && p_vci.rspack ) + if( r_fifo_rsp.rok() && p_vci.rspack.read() ) { rsp_fifo_read = true; if ( (r_fifo_rsp.read() & 0x100000000) ) r_rsp_fsm = RSP_IDLE; } - else - { - rsp_fifo_read = false; - } break; + } + case RSP_WRITE: + { + if ( p_vci.rspack.read() ) r_rsp_fsm = RSP_IDLE; } } // end switch r_rsp_fsm @@ -258,42 +273,38 @@ { // VCI CMD interface - if ( r_cmd_fsm.read() == CMD_IDLE ) p_vci.cmdack = false; - else p_vci.cmdack = r_fifo_cmd.wok(); + if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) ) + { + p_vci.cmdack = false; + } + else + { + p_vci.cmdack = r_fifo_cmd.wok(); + } // VCI RSP interface if ( r_rsp_fsm.read() == RSP_IDLE ) { - if ( r_fifo_rsp.rok() && (r_fifo_rsp.read() & 0x000020000) ) // valid RSP WRITE - { - p_vci.rspval = true; - p_vci.rdata = 0; - p_vci.rsrcid = (sc_uint)((r_fifo_rsp.read() & 0x0FFFC0000) >> 18); - p_vci.rtrdid = (sc_uint)((r_fifo_rsp.read() & 0x00000FF00) >> 8); - p_vci.rpktid = 0; - p_vci.rerror = (sc_uint)((r_fifo_rsp.read() & 0x000030000) >> 16); - p_vci.reop = true; - } - else - { - p_vci.rspval = false; - } - } - else // Next flit of a RSP READ - { - if ( r_fifo_rsp.rok() ) // valid RSP READ - { - p_vci.rspval = true; - p_vci.rdata = (sc_uint<4*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFF); - p_vci.rsrcid = (sc_uint)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); - p_vci.rtrdid = (sc_uint)((r_rsp_buf.read() & 0x00000FF00) >> 8); - p_vci.rpktid = 0; - p_vci.rerror = (sc_uint)((r_rsp_buf.read() & 0x000030000) >> 16); - p_vci.reop = ((r_fifo_rsp.read() & 0x100000000) == 0x100000000); - } - else - { - p_vci.rspval = false; - } - } + p_vci.rspval = false; + } + else if ( r_rsp_fsm.read() == RSP_WRITE ) + { + p_vci.rspval = true; + p_vci.rdata = 0; + p_vci.rsrcid = (sc_uint)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); + p_vci.rtrdid = (sc_uint)((r_rsp_buf.read() & 0x00000FF00) >> 8); + p_vci.rpktid = 0; + p_vci.rerror = (sc_uint)((r_rsp_buf.read() & 0x000030000) >> 16); + p_vci.reop = true; + } + else if ( r_rsp_fsm.read() == RSP_READ ) + { + p_vci.rspval = true; + p_vci.rdata = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFF); + p_vci.rsrcid = (sc_uint)((r_rsp_buf.read() & 0x0FFFC0000) >> 18); + p_vci.rtrdid = (sc_uint)((r_rsp_buf.read() & 0x00000FF00) >> 8); + p_vci.rpktid = 0; + p_vci.rerror = (sc_uint)((r_rsp_buf.read() & 0x000030000) >> 16); + p_vci.reop = ((r_fifo_rsp.read() & 0x100000000) == 0x100000000); + } // DSPIN_OUT interface @@ -305,4 +316,27 @@ }; // end genMoore + +///////////////////////// +tmpl(void)::print_trace() +{ + const char* cmd_str[] = { + "CMD_IDLE ", + "CMD_BROADCAST", + "CMD_READ ", + "CMD_WRITE ", + "CMD_WDATA ", + }; + const char* rsp_str[] = { + "RSP_IDLE ", + "RSP_READ ", + "RSP_WRITE ", + }; + + std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()] + << " | " << rsp_str[r_rsp_fsm.read()] + << " | fifo_cmd = " << r_fifo_cmd.filled_status() + << " | fifo_rsp = " << r_fifo_rsp.filled_status() + << std::endl; +} }} // end namespace