Changeset 166

Timestamp:

May 11, 2011, 4:59:18 PM (14 years ago)

Author:

kane

Message:

(1) add modif from previous version (before merging), (2) add two registers to manage priority (FSM CMD)

Location:

trunk

Files:

• modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (modified) (11 diffs)
• platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg (modified) (1 diff)

trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp

@@ -3287 +3287 @@
               ASSERT(p_vci_ini_c.reop and (p_vci_ini_c.rtrdid.read() == TYPE_DATA_CLEANUP),
                      "illegal response packet received for a cleanup transaction");
-              ASSERT(p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL,
+              ASSERT(p_vci_ini_c.rerror.read()&1 == vci_param::ERR_NORMAL,
                      "error signaled in a cleanup response" );
               ASSERT(p_vci_ini_c.rpktid.read() == (sc_dt::sc_uint<vci_param::P>)r_cleanup_num_cache,
@@ -3306 +3306 @@
               ASSERT(p_vci_ini_c.reop and (p_vci_ini_c.rtrdid.read() == TYPE_INS_CLEANUP),
                      "illegal response packet received for a cleanup transaction");
-              ASSERT(p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL, 
+              ASSERT(p_vci_ini_c.rerror.read()&1 == vci_param::ERR_NORMAL, 
                      "error signaled in a cleanup response" );
                     
@@ -3363 +3363 @@
       for (uint32_t i=0; i<m_nb_dcache; ++i)
         {
-          bool find = false;
+          uint32_t num_cache=(r_vci_cmd_num_dcache_prior+i)%m_nb_dcache;
+          bool     find = false;
           
           size_t  _wbuf_min   = 0;
@@ -3374 +3375 @@
           if (
 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
-              (r_wbuf[i]->rok_info(&_wbuf_min, &_wbuf_max, &_wbuf_addr, &_wbuf_index)) and
+              (r_wbuf[num_cache]->rok_info(&_wbuf_min, &_wbuf_max, &_wbuf_addr, &_wbuf_index)) and
 #else
-              (r_wbuf[i]->rok     (&_wbuf_min, &_wbuf_max)) and
+              (r_wbuf[num_cache]->rok     (&_wbuf_min, &_wbuf_max)) and
 #endif                      
               (dcache_write_num_cache == m_nb_dcache))
             {
               find = true;
-              dcache_write_num_cache = i;
+              dcache_write_num_cache = num_cache;
               
               PRINTF("      * <CMD> wbuf min, max            : %d, %d\n",(int)_wbuf_min,(int)_wbuf_max);
@@ -3421 +3422 @@
           bool     dcache_miss_req      = false;
           bool     icache_miss_req      = false;
-          uint32_t dcache_miss_num_cache = 0;
-          uint32_t icache_miss_num_cache = 0;
+          uint32_t dcache_miss_num_cache = m_nb_dcache;
+          uint32_t icache_miss_num_cache = m_nb_icache;
           addr_40  addr = 0;
 
@@ -3429 +3430 @@
       
           {
-            for (; dcache_miss_num_cache<m_nb_dcache; ++dcache_miss_num_cache)
+            for (uint32_t i=0; i<m_nb_dcache; ++i)
               {
-                dcache_miss_req = r_dcache_miss_req[dcache_miss_num_cache];
+                uint32_t num_cache=(r_vci_cmd_num_dcache_prior+i)%m_nb_dcache;
+
+                dcache_miss_req = r_dcache_miss_req[num_cache];
                 if (dcache_miss_req)
-                  break;
+                {
+                    dcache_miss_num_cache = num_cache;
+                    break;
+                }
               }
-            for (; icache_miss_num_cache<m_nb_icache; ++icache_miss_num_cache)
+            for (uint32_t i=0; i<m_nb_icache; ++i)
               {
-                icache_miss_req = r_icache_miss_req[icache_miss_num_cache];
+                uint32_t num_cache=(r_vci_cmd_num_icache_prior+i)%m_nb_icache;
+
+                icache_miss_req = r_icache_miss_req[num_cache];
                 if (icache_miss_req)
-                  break;
+                {
+                    icache_miss_num_cache = num_cache;
+                    break;
+                }
               }
 
@@ -3489 +3500 @@
           }
 
-          uint32_t dcache_unc_num_cache = 0;
-          for (; dcache_unc_num_cache<m_nb_dcache; ++dcache_unc_num_cache)
-            if (r_dcache_unc_req[dcache_unc_num_cache])
-              break;
-          uint32_t icache_unc_num_cache = 0;
-          for (; icache_unc_num_cache<m_nb_icache; ++icache_unc_num_cache)
-            if (r_icache_unc_req[icache_unc_num_cache])
-              break;
-          uint32_t dcache_sc_num_cache = 0;
-          for (; dcache_sc_num_cache<m_nb_dcache; ++dcache_sc_num_cache)
-            if (r_dcache_sc_req[dcache_sc_num_cache])
-              break;
+          uint32_t dcache_unc_num_cache = m_nb_dcache;
+          for (uint32_t i=0; i<m_nb_dcache; ++i)
+          {
+              uint32_t num_cache=(r_vci_cmd_num_dcache_prior+i)%m_nb_dcache;
+              if (r_dcache_unc_req[num_cache])
+              {
+                  dcache_unc_num_cache = num_cache;
+                  break;
+              }
+          }
+          uint32_t icache_unc_num_cache = m_nb_icache;
+          for (uint32_t i=0; i<m_nb_icache; ++i)
+          {
+              uint32_t num_cache=(r_vci_cmd_num_icache_prior+i)%m_nb_icache;
+              if (r_icache_unc_req[num_cache])
+              {
+                  icache_unc_num_cache = num_cache;
+                  break;
+              }
+          }
+          uint32_t dcache_sc_num_cache = m_nb_dcache;
+          for (uint32_t i=0; i<m_nb_dcache; ++i)
+          {
+              uint32_t num_cache=(r_vci_cmd_num_dcache_prior+i)%m_nb_dcache;
+              if (r_dcache_sc_req[num_cache])
+              {
+                  dcache_sc_num_cache = num_cache;
+                  break;
+              }
+          }
 
           // 1 - Data Read
@@ -3881 +3910 @@
             PRINTF("      * <RSP> ins : %x\n",(int)p_vci_ini_rw.rdata.read());
 
-            ASSERT( (r_vci_rsp_cpt < m_icache_words),
+            ASSERT( (r_vci_rsp_cpt.read() < m_icache_words),
                     "The VCI response packet for instruction miss is too long" );
-            r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+            r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
             vci_rsp_fifo_icache_put       = true,
             vci_rsp_fifo_icache_num_cache = r_vci_rsp_num_cache;
@@ -3892 +3921 @@
                 PRINTF("      * <RSP> have reop\n");
 
-                ASSERT( ((r_vci_rsp_cpt == m_icache_words - 1) or
-                         p_vci_ini_rw.rerror.read() or
+                ASSERT( ((r_vci_rsp_cpt.read() == m_icache_words - 1) or
+                         (p_vci_ini_rw.rerror.read()&1) or
                          (r_vci_rsp_ins_error[r_vci_rsp_num_cache].read()&0x1)),
                         "The VCI response packet for instruction miss is too short");
@@ -3929 +3958 @@
             PRINTF("      * <RSP> have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read());
 
-            ASSERT(r_vci_rsp_cpt < m_dcache_words,
+            ASSERT(r_vci_rsp_cpt.read() < m_dcache_words,
                    "illegal VCI response packet for data read miss");
-            r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+            r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
 
             vci_rsp_fifo_dcache_put       = true,
@@ -3938 +3967 @@
 
             if ( p_vci_ini_rw.reop.read() ) {
-              ASSERT( ((r_vci_rsp_cpt == m_dcache_words - 1) 
+              ASSERT( ((r_vci_rsp_cpt.read() == m_dcache_words - 1) 
                        or (p_vci_ini_rw.rerror.read()&0x1)
                        or r_vci_rsp_data_error[r_vci_rsp_num_cache].read()),

trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg

@@ -1 @@
-2
-2 2
+1
+4 4
 4 64 16
 4 64 16