Index: /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h =================================================================== --- /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (revision 174) +++ /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (revision 175) @@ -92,5 +92,5 @@ #endif #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN -#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 4725000 +#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1013300 #endif #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION @@ -133,5 +133,4 @@ DCACHE_CC_CHECK, DCACHE_CC_INVAL, - DCACHE_CC_UPDT, DCACHE_CC_CLEANUP, }; @@ -147,5 +146,4 @@ ICACHE_CC_CHECK, ICACHE_CC_INVAL, - ICACHE_CC_UPDT, }; Index: /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp =================================================================== --- /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (revision 174) +++ /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (revision 175) @@ -88,8 +88,4 @@ # define set_num_icache( addr,num_cache) set_num_cache (addr,num_cache) # define set_num_icache_only(addr,num_cache) set_num_cache_only(addr,num_cache) -# define get_num_dcache( addr) get_num_cache (addr) -# define get_num_dcache_only(addr) get_num_cache_only(addr) -# define set_num_dcache( addr,num_cache) set_num_cache (addr,num_cache) -# define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache) #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) # define get_num_icache( addr,num_cpu) num_cpu @@ -97,11 +93,11 @@ # define set_num_icache( addr,num_cache) do {} while (0) # define set_num_icache_only(addr,num_cache) addr +#else +#error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE" +#endif # define get_num_dcache( addr) get_num_cache (addr) # define get_num_dcache_only(addr) get_num_cache_only(addr) # define set_num_dcache( addr,num_cache) set_num_cache (addr,num_cache) # define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache) -#else -#error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE" -#endif const char *dcache_fsm_state_str[] = { @@ -118,5 +114,4 @@ "DCACHE_CC_CHECK", "DCACHE_CC_INVAL", - "DCACHE_CC_UPDT", "DCACHE_CC_CLEANUP", }; @@ -131,5 +126,4 @@ "ICACHE_CC_CHECK", "ICACHE_CC_INVAL", - "ICACHE_CC_UPDT", }; const char *cmd_fsm_state_str[] = { @@ -300,5 +294,5 @@ "wbuf_nlines must be a multiple of nb cache."); - // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE + // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE, car le type est fournit dans le champs l'adresse ASSERT((m_nb_dcache == 1) or (dcache_words >= 16), "When multi cache is activated, need 4 bits (16 word) to the cache set ."); @@ -576,5 +570,4 @@ << _dcache_words << std::endl; // cache_nb_words } - #endif } // end constructor @@ -1209,6 +1202,16 @@ // r_wbuf[num_cache]->printTrace(1); // #endif - - } + } +#if CC_XCACHE_WRAPPER_DEBUG + if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) + { + PRINTF(" * rsp_fifo_icache %s\n",name().c_str()); + r_vci_rsp_fifo_icache_data .print(); + r_vci_rsp_fifo_icache_num_cache.print(); + PRINTF(" * rsp_fifo_dcache %s\n",name().c_str()); + r_vci_rsp_fifo_dcache_data .print(); + r_vci_rsp_fifo_dcache_num_cache.print(); + } +#endif ///////////////////////////////////////////////////////////////////// @@ -2138,5 +2141,4 @@ m_cpt_icache_data_read += m_icache_ways; addr_40 ad = r_tgt_iaddr; - data_t icache_rdata = 0; PRINTF(" * CC_CHECK\n",num_cache); @@ -2157,5 +2159,8 @@ r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache]; } else { - bool icache_hit = r_icache[num_cache]->read(ad, &icache_rdata); + uint32_t word = r_cache_word; + data_t mask = vci_param::be2mask(r_tgt_be[word]); + data_t rdata = 0; + bool icache_hit = r_icache[num_cache]->read(ad+word*4,&rdata); PRINTF(" * have no request, hit cache : %d\n",num_cache,icache_hit); @@ -2163,10 +2168,9 @@ if ( icache_hit and r_tgt_update) { - uint32_t word = r_cache_word; - data_t mask = vci_param::be2mask(r_tgt_be[word]); - data_t rdata = 0; - - r_icache[num_cache]->read(ad+word*4,&rdata); - r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); + // Assumption : We have RAM for icache with write enable on byte. + // Consequence : icache_read is only consultation of directory + + //if(r_tgt_be[word]) + r_icache[num_cache]->write(ad+word*4, (mask & r_tgt_buf[word]) | (~mask & rdata)); word ++; @@ -2179,10 +2183,8 @@ if (word==m_icache_words) { - r_icache_fsm[num_cache] = ICACHE_CC_UPDT; - - // find next valid word - for (word=0; wordwrite(ad+word*4, r_tgt_buf[word]); - - word ++; - - // find next valid word - for (; word CC_CHECK\n",num_cache); @@ -2942,20 +2915,21 @@ r_dcache_fsm[num_cache] = r_dcache_fsm_save[num_cache]; } else { - bool dcache_hit = r_dcache[num_cache]->read(ad, &dcache_rdata); + uint32_t word = r_cache_word; + data_t mask = vci_param::be2mask(r_tgt_be[word]); + data_t rdata = 0; + bool dcache_hit = r_dcache[num_cache]->read(ad+word*4,&rdata); PRINTF(" * have no request, hit cache : %d, update : %d\n",num_cache,dcache_hit,(uint32_t)r_tgt_update); - m_cpt_dcache_data_read += m_dcache_ways; + m_cpt_dcache_data_write+= m_dcache_ways; m_cpt_dcache_dir_read += m_dcache_ways; if ( dcache_hit and r_tgt_update ) { - uint32_t word = r_cache_word; - data_t mask = vci_param::be2mask(r_tgt_be[word]); - data_t rdata = 0; - - r_dcache[num_cache]->read(ad+word*4,&rdata); - - r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); + // Assumption : We have RAM for dcache with write enable on byte. + // Consequence : dcache_read is only consultation of directory + + //if(r_tgt_be[word]) + r_dcache[num_cache]->write(ad+word*4, (mask & r_tgt_buf[word]) | (~mask & rdata)); word ++; @@ -2968,9 +2942,8 @@ if (word==m_dcache_words) { - r_dcache_fsm[num_cache] = DCACHE_CC_UPDT; - - for (word=0; wordwrite(ad+word*4, r_tgt_buf[word]); - - word ++; - - for (; word rspval : %d\n",(uint32_t)p_vci_ini_rw.rspval.read()); + PRINTF(" * rspval : %d / r_vci_rsp_fifo_icache_data.wok %d\n",(uint32_t)p_vci_ini_rw.rspval.read(),(uint32_t)r_vci_rsp_fifo_icache_data.wok()); if (p_vci_ini_rw.rspval.read() and r_vci_rsp_fifo_icache_data.wok()) @@ -3949,7 +3892,10 @@ m_cost_dmiss_transaction++; + + PRINTF(" * rspval : %d / r_vci_rsp_fifo_icache_data.wok %d\n",(uint32_t)p_vci_ini_rw.rspval.read(),(uint32_t)r_vci_rsp_fifo_dcache_data.wok()); + if (p_vci_ini_rw.rspval.read() and r_vci_rsp_fifo_dcache_data.wok()) { - PRINTF(" * have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read()); + PRINTF(" * have rsp - r_vci_rsp_cpt : %d/%d\n",(uint32_t)r_vci_rsp_cpt.read(),(uint32_t)m_icache_words); ASSERT(r_vci_rsp_cpt.read() < m_dcache_words, Index: /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp =================================================================== --- /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 174) +++ /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 175) @@ -30,5 +30,5 @@ #define DEBUG_VCI_MEM_CACHE 0 -#define DEBUG_START_CYCLE 1500 +#define DEBUG_START_CYCLE 1013300 #define RANDOMIZE_SC @@ -1583,5 +1583,5 @@ if ( !r_write_to_tgt_rsp_req.read() ) { - PRINTF(" * YURI Request from %d.%d (%d)\n",(uint32_t)r_write_srcid.read(), (uint32_t)r_write_trdid.read(), (uint32_t)r_write_pktid.read()); + PRINTF(" * Request from %d.%d (%d)\n",(uint32_t)r_write_srcid.read(), (uint32_t)r_write_trdid.read(), (uint32_t)r_write_pktid.read()); r_write_to_tgt_rsp_req = true; @@ -3820,4 +3820,6 @@ case TGT_RSP_READ: // send the response { + PRINTF("* YURI RSP_READ : rspack %d - cpt %d on %d\n", (int)p_vci_tgt.rspack,(int)r_tgt_rsp_cpt.read(),(int)(r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1)); + if ( p_vci_tgt.rspack ) { if ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ) { Index: /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg =================================================================== --- /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg (revision 174) +++ /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg (revision 175) @@ -1,3 +1,3 @@ -1 +2 4 4 4 64 16 Index: /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h =================================================================== --- /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h (revision 174) +++ /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h (revision 175) @@ -28,5 +28,5 @@ #define SORT_SHELL_SIZE 5000 #define MATRIX_MULTIPLICATION_ST_SIZE 50 -#define MATRIX_MULTIPLICATION_MT_SIZE 96 +#define MATRIX_MULTIPLICATION_MT_SIZE 75 #define MATRIX_MULTIPLICATION_MT_LOCK_BY_LINE 1 #define SELF_CODE_MODIFYING_NB_RUNS 10 Index: /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp =================================================================== --- /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp (revision 174) +++ /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp (revision 175) @@ -32,5 +32,4 @@ # define USE_OLD_XCACHE 0 -# define USE_VGMN 1 # define NB_PROC_MIN 1 # define NB_PROC_MAX 15 @@ -460,4 +459,17 @@ sc_start(sc_core::sc_time(ncycles, SC_NS)); + // sc_start(sc_core::sc_time(1013000, SC_NS)); + // uint32_t num_cycle=1013000 ; + + // for (uint32_t i=0; i<600; ++i) + // { + // std::cout << std::endl + // << std::dec << "===== [ cycle " << num_cycle << " ]======" << std::endl + // << std::endl; + // sc_start(sc_core::sc_time(1, SC_NS)); + // interconnect_p.print_trace(); + // num_cycle ++; + // } + // std::cout << "Hit ENTER to end simulation" << std::endl; // char buf[1];