Changeset 177 for trunk/modules/vci_mem_cache_v4/caba

Timestamp:

Jun 17, 2011, 11:41:19 AM (14 years ago)

Author:

alain

Message:

ng two warnings regarding the order of member variables initialisation.

File:

• trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (modified) (1 diff)

trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

@@ -339 +339 @@
 
       // Component attributes
-      const size_t                      m_initiators;           // Number of initiators
-      const size_t                      m_heap_size;            // Size of the heap
-      const size_t                      m_ways;                 // Number of ways in a set
-      const size_t                      m_sets;                 // Number of cache sets
-      const size_t                      m_words;                // Number of words in a line
-      const size_t                      m_srcid_ixr;            // Srcid for requests to XRAM 
-      const size_t                      m_srcid_ini;            // Srcid for requests to processors
-      std::list<soclib::common::Segment>  m_seglist;            // memory cached into the cache
-      std::list<soclib::common::Segment>  m_cseglist;           // coherence segment for the cache
-      vci_addr_t                             *m_coherence_table;        // address(srcid)
-      TransactionTab                        m_transaction_tab;  // xram transaction table
-      uint32_t                    m_transaction_tab_lines;
-      UpdateTab                         m_update_tab;           // pending update & invalidate 
-      uint32_t                    m_update_tab_lines;
+      const size_t                              m_initiators;           // Number of initiators
+      const size_t                              m_heap_size;            // Size of the heap
+      const size_t                              m_ways;                 // Number of ways in a set
+      const size_t                              m_sets;                 // Number of cache sets
+      const size_t                              m_words;                // Number of words in a line
+      const size_t                              m_srcid_ixr;            // Srcid for requests to XRAM 
+      const size_t                              m_srcid_ini;            // Srcid for requests to processors
+      std::list<soclib::common::Segment>        m_seglist;              // memory cached into the cache
+      std::list<soclib::common::Segment>        m_cseglist;             // coherence segment for the cache
+      vci_addr_t                                *m_coherence_table;     // address(srcid)
+      uint32_t                                  m_transaction_tab_lines;
+      TransactionTab                            m_transaction_tab;      // xram transaction table
+      uint32_t                                  m_update_tab_lines;
+      UpdateTab                                 m_update_tab;           // pending update & invalidate 
       CacheDirectory                            m_cache_directory;      // data cache directory
-      HeapDirectory                     m_heap_directory;       // heap directory
-
-      data_t                           ***m_cache_data;         // data array[set][way][word]
+      HeapDirectory                             m_heap_directory;       // heap directory
+
+      data_t                                    ***m_cache_data;        // data array[set][way][word]
 
       // adress masks