Index: trunk/modules/vci_cc_vcache_wrapper2_multi/caba/source/src/vci_cc_vcache_wrapper2_multi.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_multi/caba/source/src/vci_cc_vcache_wrapper2_multi.cpp	(revision 17)
+++ trunk/modules/vci_cc_vcache_wrapper2_multi/caba/source/src/vci_cc_vcache_wrapper2_multi.cpp	(revision 18)
@@ -1073,4 +1073,5 @@
                 r_itlb_read_dcache_req = true;
 		r_icache_vaddr_req = ireq.addr;
+		r_itlb_k_read_dcache = true;
                 r_icache_fsm = ICACHE_TLB2_READ;
                 m_cpt_ins_tlb_miss++;
@@ -1675,5 +1676,8 @@
         if ( r_tgt_icache_req )
         {
-            r_tgt_icache_req = false;
+	    r_icache_fsm = ICACHE_CC_INVAL;
+    	    r_icache_fsm_save = r_icache_fsm;
+	    m_cost_ins_waste_wait_frz++;
+            break;	    
         }
 
@@ -1735,4 +1739,12 @@
     {	
         if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+	    r_icache_fsm = ICACHE_CC_INVAL;
+    	    r_icache_fsm_save = r_icache_fsm;
+	    m_cost_ins_waste_wait_frz++;
+            break;	    
+        }
 
         paddr_t ipaddr = 0;                     
@@ -1764,4 +1776,13 @@
     case ICACHE_CACHE_INVAL_PA:
     {	
+	// external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+	    r_icache_fsm = ICACHE_CC_INVAL;
+    	    r_icache_fsm_save = r_icache_fsm;
+	    m_cost_ins_waste_wait_frz++;
+            break;	    
+        }    
+
         paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
 
@@ -2172,6 +2193,7 @@
 
     	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
-	    if ( (r_icache_fsm == ICACHE_TLB2_READ) && itlb_hit_dcache )
+	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
 	    {	
+		r_itlb_k_read_dcache = false;
 	        bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
 		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
@@ -3995,5 +4017,8 @@
         if ( r_tgt_dcache_req )
         {
-            r_tgt_dcache_req = false;
+	    r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;	   
+	    m_cost_data_waste_wait_frz++;
+	    break; 
         }   
 
@@ -4063,4 +4088,13 @@
     case DCACHE_DCACHE_INVAL:
     {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )
+        {
+	    r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;	   
+	    m_cost_data_waste_wait_frz++;
+	    break; 
+        }   
+
         m_cpt_dcache_dir_read += m_dcache_ways;
         vaddr_t invadr = dreq.wdata;
@@ -4111,4 +4145,12 @@
     case DCACHE_DCACHE_INVAL_PA:
     {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )
+        {
+	    r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;	   
+	    m_cost_data_waste_wait_frz++;
+	    break; 
+        }   	    
         m_cpt_dcache_dir_read += m_dcache_ways;
         paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
@@ -4305,7 +4347,5 @@
             if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
             {
-                r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_tlb_rsp = false;
-		break;
             }
 
@@ -4812,6 +4852,4 @@
         }
 
-            r_dtlb_translation_valid = false;
-            r_dcache_ptba_ok = false;
 	if ( !r_dcache_cc_check )
 	{
@@ -4823,4 +4861,6 @@
 	    r_dcache_cc_check = false;
 	}
+	r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;
         break;
     }