- Timestamp:
- Jan 8, 2012, 2:36:49 PM (13 years ago)
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trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r175 r188 1 1 /* -*- c++ -*- 2 * File : vci_cc_xcache_wrapper_v4.h 3 * Copyright (c) UPMC, Lip6, SoC 4 * Authors : Alain GREINER 5 * Date : 27/11/2011 2 6 * 3 7 * SOCLIB_LGPL_HEADER_BEGIN … … 20 24 * 21 25 * SOCLIB_LGPL_HEADER_END 22 *23 * Copyright (c) UPMC, Lip6, SoC24 * Alain Greiner <alain.greiner@lip6.fr>, 200825 *26 * Maintainers: alain27 26 */ 28 27 … … 38 37 #include "generic_cache.h" 39 38 #include "generic_fifo.h" 39 #include "generic_cam.h" 40 40 #include "vci_initiator.h" 41 41 #include "vci_target.h" 42 42 #include "mapping_table.h" 43 43 #include "static_assert.h" 44 45 /* 46 * ---------------------------------------------------------- 47 * Implementation 48 * ---------------------------------------------------------- 49 * 50 * CC_XCACHE_WRAPPER_MULTI_CACHE 51 * 1 - icache static partitionnement 52 * 2 - icache dedicated 53 * 54 * ---------------------------------------------------------- 55 * Debug 56 * ---------------------------------------------------------- 57 * 58 * CC_XCACHE_WRAPPER_STOP_SIMULATION 59 * stop simulation if processor is stall after a long time 60 * (configurable with "stop_simulation" function) 61 * 62 * CC_XCACHE_WRAPPER_DEBUG 63 * Add log to help the debugging 64 * 65 * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 66 * Number of cycle before to prinf debug message 67 * 68 * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 69 * Print transaction between : 70 * - the cpu and the cache (icache and dcache) 71 * - vci 72 * - cleanup 73 * - coherency 74 * 75 * MWBUF_VHDL_TESTBENCH 76 * generate a vhdl testbench for multi write buffer 77 */ 78 79 // implementation 80 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE 81 #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 82 // if multi_cache : 83 // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 84 #endif 85 86 // debug 87 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION 88 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 89 #endif 90 #ifndef CC_XCACHE_WRAPPER_DEBUG 91 #define CC_XCACHE_WRAPPER_DEBUG 0 92 #endif 93 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 94 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1013300 95 #endif 96 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 97 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 98 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" 99 #endif 100 #ifndef MWBUF_VHDL_TESTBENCH 101 #define MWBUF_VHDL_TESTBENCH 0 102 #endif 44 #include "iss2.h" 103 45 104 46 namespace soclib { … … 113 55 : public soclib::caba::BaseModule 114 56 { 115 typedef uint64_t vhdl_tb_t; 116 typedef sc_dt::sc_uint<40> addr_40; 117 typedef uint32_t data_t; 118 typedef uint32_t tag_t; 119 typedef uint32_t be_t; 120 typedef typename vci_param::fast_addr_t vci_addr_t; 57 typedef uint32_t data_t; 58 typedef uint32_t tag_t; 59 typedef uint32_t be_t; 60 typedef typename vci_param::fast_addr_t vci_addr_t; 121 61 122 enum dcache_fsm_state_e { 62 enum dcache_fsm_state_e 63 { 123 64 DCACHE_IDLE, 124 65 DCACHE_WRITE_UPDT, … … 127 68 DCACHE_MISS_UPDT, 128 69 DCACHE_UNC_WAIT, 129 DCACHE_SC_WAIT,130 70 DCACHE_INVAL, 71 DCACHE_INVAL_GO, 131 72 DCACHE_SYNC, 132 73 DCACHE_ERROR, 133 74 DCACHE_CC_CHECK, 134 75 DCACHE_CC_INVAL, 135 DCACHE_CC_CLEANUP, 136 }; 137 138 enum icache_fsm_state_e { 76 DCACHE_CC_UPDT, 77 }; 78 79 enum icache_fsm_state_e 80 { 139 81 ICACHE_IDLE, 140 82 ICACHE_MISS_VICTIM, … … 143 85 ICACHE_UNC_WAIT, 144 86 ICACHE_ERROR, 145 ICACHE_CC_CLEANUP,146 87 ICACHE_CC_CHECK, 147 88 ICACHE_CC_INVAL, 148 }; 149 150 enum cmd_fsm_state_e { 89 ICACHE_CC_UPDT, 90 }; 91 92 enum cmd_fsm_state_e 93 { 151 94 CMD_IDLE, 152 95 CMD_INS_MISS, … … 158 101 }; 159 102 160 enum rsp_fsm_state_e { 103 enum rsp_fsm_state_e 104 { 161 105 RSP_IDLE, 162 106 RSP_INS_MISS, … … 168 112 }; 169 113 170 enum tgt_fsm_state_e { 114 enum tgt_fsm_state_e 115 { 171 116 TGT_IDLE, 172 117 TGT_UPDT_WORD, … … 180 125 }; 181 126 182 enum cleanup_fsm_state_e { 183 CLEANUP_IDLE, 184 CLEANUP_REQ, 185 CLEANUP_RSP_DCACHE, 186 CLEANUP_RSP_ICACHE, 187 }; 188 189 enum transaction_type_c_e { 190 // convention with memcache 191 TYPE_DATA_CLEANUP = 0x0, 192 TYPE_INS_CLEANUP = 0x1 193 }; 194 195 enum transaction_type_rw_e { 127 enum cleanup_cmd_fsm_state_e 128 { 129 CLEANUP_DATA_IDLE, 130 CLEANUP_INS_IDLE, 131 CLEANUP_DATA_GO, 132 CLEANUP_INS_GO, 133 }; 134 135 enum transaction_type_d_e 136 { 196 137 // convention with memcache 197 138 // b0 : 1 if cached … … 202 143 TYPE_INS_UNC = 0x2, 203 144 TYPE_INS_MISS = 0x3, 204 TYPE_DATA_SC = 0x4, // sc is data and no cached205 145 }; 206 146 … … 210 150 sc_in<bool> p_clk; 211 151 sc_in<bool> p_resetn; 212 sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq];213 soclib::caba::VciInitiator<vci_param> p_vci_ini_ rw;152 sc_in<bool> * p_irq; // [iss_t::n_irq]; 153 soclib::caba::VciInitiator<vci_param> p_vci_ini_d; 214 154 soclib::caba::VciInitiator<vci_param> p_vci_ini_c; 215 soclib::caba::VciTarget<vci_param> p_vci_tgt ;155 soclib::caba::VciTarget<vci_param> p_vci_tgt_c; 216 156 217 157 private: 218 158 219 159 // STRUCTURAL PARAMETERS 220 const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table;221 const soclib::common::Segment m_segment;222 iss_t ** m_iss; //[m_nb_cpu] 223 const uint32_t m_srcid_rw;224 const uint32_t m_srcid_c;160 const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; 161 const soclib::common::Segment m_segment; 162 163 const uint32_t m_srcid_d; 164 const uint32_t m_srcid_c; 225 165 226 const size_t m_nb_cpu; 227 const size_t m_nb_icache; 228 const size_t m_nb_dcache; 229 const size_t m_nb_cache; 230 const size_t m_dcache_ways; 231 const size_t m_dcache_words; 232 const uint32_t m_dcache_words_shift; 233 const size_t m_dcache_yzmask; 234 const size_t m_icache_ways; 235 const size_t m_icache_words; 236 const uint32_t m_icache_words_shift; 237 const size_t m_icache_yzmask; 238 const size_t m_cache_words; // max between m_dcache_words and m_icache_words 239 240 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 241 bool m_stop_simulation; 242 uint32_t m_stop_simulation_nb_frz_cycles_max; 243 uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu] 244 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 245 246 // REGISTERS 247 sc_signal<uint32_t> r_cpu_prior; 248 sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache] 249 sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache] 250 sc_signal<bool> * r_dcache_sync;//[m_nb_dcache] 251 252 sc_signal<int> * r_dcache_fsm; //[m_nb_dcache] 253 sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache] 254 sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache] 255 sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache] 256 sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache] 257 sc_signal<int> * r_dcache_type_save; //[m_nb_dcache] 258 sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache] 259 sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache] 260 sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache] 261 sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache] 262 sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache] 263 sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache] 264 sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache] 265 sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache] 266 sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache] 267 sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache] 268 sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache] 269 sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache] 270 sc_signal<data_t> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] 271 sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] 272 sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] 273 sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache] 166 const size_t m_dcache_ways; 167 const size_t m_icache_ways; 168 169 const size_t m_cache_words; 170 const size_t m_cache_words_shift; 171 const vci_addr_t m_cache_yzmask; 172 173 const uint32_t m_max_frozen_cycles; 174 175 iss_t * r_iss; 176 MultiWriteBuffer<vci_addr_t> * r_wbuf; 177 GenericCache<vci_addr_t> * r_icache; 178 GenericCache<vci_addr_t> * r_dcache; 179 180 sc_signal<int> r_icache_fsm; 181 sc_signal<int> r_icache_fsm_save; // return state for coherence request 182 sc_signal<vci_addr_t> r_icache_addr_save; // address requested by proc 183 sc_signal<bool> r_icache_miss_req; // set by icache_fsm / reset by cmd_fsm 184 sc_signal<bool> r_icache_unc_req; // set by icache_fsm / reset by cmd_fsm 185 sc_signal<bool> r_icache_cleanup_req; // a victim line must be evicted 186 sc_signal<vci_addr_t> r_icache_cleanup_line; // address of the selected victim line 187 sc_signal<size_t> r_icache_cleanup_way; // way of the selected victim line 188 sc_signal<size_t> r_icache_cleanup_set; // set of the selected victim line 189 sc_signal<bool> r_icache_miss_inval; // cancellation request for pending miss 190 sc_signal<size_t> r_icache_update_word; // word index for update (intern/extern) 191 sc_signal<data_t> r_icache_unc_buf; // Non cacheable read buffer (one word) 192 sc_signal<bool> r_icache_unc_valid; // Non cacheable read buffer valid 193 sc_signal<size_t> r_icache_cc_way; // way index for coherence request 194 sc_signal<size_t> r_icache_cc_set; // set index for coherence request 195 196 sc_signal<int> r_dcache_fsm; 197 sc_signal<int> r_dcache_fsm_save; // return state when coherence request 198 sc_signal<vci_addr_t> r_dcache_addr_save; // address requested by proc 199 sc_signal<data_t> r_dcache_wdata_save; // data written (for dcache update) 200 sc_signal<be_t> r_dcache_be_save; // byte enable (for dcache update) 201 sc_signal<be_t> r_dcache_way_save; // selected way (in case of hit) 202 sc_signal<be_t> r_dcache_set_save; // selected set (in case of hit) 203 sc_signal<be_t> r_dcache_word_save; // selected word (in case of hit) 204 sc_signal<bool> r_dcache_cleanup_req; // a victim line must be evicted 205 sc_signal<vci_addr_t> r_dcache_cleanup_line; // address of the selected victim line 206 sc_signal<size_t> r_dcache_cleanup_way; // way of the selected victim line 207 sc_signal<size_t> r_dcache_cleanup_set; // set of the selected victim line 208 sc_signal<bool> r_dcache_miss_req; // set by dcache_fsm / reset by cmd_fsm 209 sc_signal<bool> r_dcache_unc_req; // set by dcache_fsm / reset by cmd_fsm 210 sc_signal<bool> r_dcache_sc_req; // set by dcache_fsm / reset by cmd_fsm 211 sc_signal<bool> r_dcache_miss_inval; // cancellation of a pending miss 212 sc_signal<size_t> r_dcache_update_word; // word index for update (intern/extern) 213 sc_signal<data_t> r_dcache_ll_data; // LL reservation data 214 sc_signal<vci_addr_t> r_dcache_ll_addr; // ll reservation address 215 sc_signal<bool> r_dcache_ll_valid; // ll reservation valid 216 sc_signal<bool> r_dcache_pending_unc_write; // Non cacheable write pending 217 sc_signal<data_t> r_dcache_unc_buf; // Non cacheable read buffer (one word) 218 sc_signal<bool> r_dcache_unc_valid; // Non cacheable read buffer valid 219 sc_signal<size_t> r_dcache_cc_way; // way index for coherence request 220 sc_signal<size_t> r_dcache_cc_set; // set index for coherence request 274 221 275 sc_signal<int> * r_icache_fsm; //[m_nb_icache]276 sc_signal<int> * r_icache_fsm_save; //[m_nb_icache]277 sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache]278 sc_signal<bool> * r_icache_miss_req; //[m_nb_icache]279 sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache]280 sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache]281 sc_signal<bool> * r_icache_unc_req; //[m_nb_icache]282 sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache]283 sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache]284 sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache]285 sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache]286 sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache]287 288 222 sc_signal<int> r_vci_cmd_fsm; 289 sc_signal<size_t> r_vci_cmd_min; 290 sc_signal<size_t> r_vci_cmd_max; 223 sc_signal<size_t> r_vci_cmd_min; // min word index for a write burst 224 sc_signal<size_t> r_vci_cmd_max; // max word index for a write burst 291 225 sc_signal<size_t> r_vci_cmd_cpt; 292 sc_signal<bool> r_vci_cmd_dcache_prior; 293 sc_signal<uint32_t> r_vci_cmd_num_icache_prior; 294 sc_signal<uint32_t> r_vci_cmd_num_dcache_prior; 295 sc_signal<uint32_t> r_vci_cmd_num_cache; 226 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin flip-flop to access wbuf 296 227 297 228 sc_signal<int> r_vci_rsp_fsm; 298 229 sc_signal<size_t> r_vci_rsp_cpt; 299 sc_signal<uint32_t> r_vci_rsp_num_cache; 300 sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache] 301 sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] 302 303 GenericFifo<data_t> r_vci_rsp_fifo_icache_data; 304 GenericFifo<uint32_t> r_vci_rsp_fifo_icache_num_cache; 305 GenericFifo<data_t> r_vci_rsp_fifo_dcache_data; 306 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache_num_cache; 307 308 data_t * r_tgt_buf; //[m_cache_words] 309 be_t * r_tgt_be; //[m_cache_words] 310 sc_signal<uint32_t> r_cache_word; 311 312 sc_signal<int> r_vci_tgt_fsm; 313 sc_signal<addr_40> r_tgt_iaddr; 314 sc_signal<addr_40> r_tgt_daddr; 315 sc_signal<size_t> r_tgt_word; 316 sc_signal<bool> r_tgt_update; 317 sc_signal<bool> r_tgt_update_data; 318 //sc_signal<bool> r_tgt_brdcast; 230 sc_signal<bool> r_vci_rsp_ins_error; // set by rsp_fsm / reset by icache_fsm 231 sc_signal<bool> r_vci_rsp_data_error; // set by rsp_fsm / reset by dcache_fsm 232 GenericFifo<data_t> r_vci_rsp_fifo_icache; // response fifo to ICACHE FSM 233 GenericFifo<data_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 234 235 sc_signal<int> r_tgt_fsm; // target port on coherence network 236 sc_signal<bool> r_tgt_icache_rsp; // VCI response required when true 237 sc_signal<bool> r_tgt_dcache_rsp; // VCI response required when true 238 sc_signal<vci_addr_t> r_tgt_addr; // address of the target line 239 sc_signal<size_t> r_tgt_word_min; // index of the first word to be updated 240 sc_signal<size_t> r_tgt_word_max; // index of the last word to be updated 241 sc_signal<size_t> r_tgt_word_count; // word counter to fill the tgt_buf 242 sc_signal<bool> r_tgt_update; // update request when true 243 sc_signal<bool> r_tgt_update_data; // update_data request when true 319 244 sc_signal<size_t> r_tgt_srcid; 320 245 sc_signal<size_t> r_tgt_pktid; 321 246 sc_signal<size_t> r_tgt_trdid; 322 //sc_signal<size_t> r_tgt_plen; 323 sc_signal<uint32_t> r_tgt_num_cache; 324 sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache] 325 sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache] 326 sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache] 327 sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache] 328 329 sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network 330 sc_signal<uint32_t> r_cleanup_num_cache; 331 sc_signal<bool> r_cleanup_icache; 332 333 MultiWriteBuffer<addr_40>** r_wbuf; 334 GenericCache<vci_addr_t> ** r_icache; 335 GenericCache<vci_addr_t> ** r_dcache; 336 337 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 338 bool generate_log_transaction_file_icache; 339 bool generate_log_transaction_file_dcache; 340 bool generate_log_transaction_file_cmd; 341 bool generate_log_transaction_file_tgt; 342 bool generate_log_transaction_file_cleanup; 343 344 std::ofstream * log_transaction_file_icache; //[m_nb_cpu] 345 std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] 346 std::ofstream log_transaction_file_cmd; 347 std::ofstream log_transaction_file_tgt; 348 std::ofstream log_transaction_file_cleanup; 349 #endif 350 351 #if MWBUF_VHDL_TESTBENCH 352 bool simulation_started; 353 bool generate_vhdl_testbench_mwbuf; 354 std::ofstream * vhdl_testbench_mwbuf; //[m_nb_dcache] 355 #endif 356 357 // Activity counters 358 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 359 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 360 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 361 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 362 363 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 364 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 365 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 366 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 367 368 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 369 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 370 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 371 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 372 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 373 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 374 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 375 376 uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 377 uint32_t m_cpt_total_cycles; // total number of cycles 378 379 uint32_t m_cpt_data_read; // number of data read 380 uint32_t m_cpt_data_read_miss; // number of data read miss 381 uint32_t m_cpt_data_read_uncached; // number of data read uncached 382 uint32_t m_cpt_data_write; // number of data write 383 uint32_t m_cpt_data_write_miss; // number of data write miss 384 uint32_t m_cpt_data_write_uncached; // number of data write uncached 385 uint32_t m_cpt_ins_miss; // * number of instruction miss 386 387 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 388 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 389 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 390 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 391 392 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 393 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 394 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 395 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 396 397 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 398 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 399 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 400 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 401 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 402 403 uint32_t * m_cpt_icache_access; //[m_nb_icache] 404 uint32_t * m_cpt_dcache_access; //[m_nb_dcache] 405 uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache] 406 uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache] 407 uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache] 408 uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache] 409 uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache] 410 411 uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] 412 uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] 413 uint32_t * m_cpt_fsm_cmd; 414 uint32_t * m_cpt_fsm_rsp; 415 uint32_t * m_cpt_fsm_tgt; 416 uint32_t * m_cpt_fsm_cleanup; 417 418 // Non blocking multi-cache 419 typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] 420 typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] 421 bool * ireq_cached ; //[m_nb_icache] 422 uint32_t * ireq_num_cpu; //[m_nb_dcache] 423 typename iss_t::DataRequest * dreq ; //[m_nb_dcache] 424 typename iss_t::DataResponse * drsp ; //[m_nb_dcache] 425 bool * dreq_cached ; //[m_nb_dcache] 426 uint32_t * dreq_num_cpu; //[m_nb_dcache] 427 428 const uint32_t m_num_cache_LSB; 429 const uint32_t m_num_cache_MSB; 430 addr_40 m_num_cache_LSB_mask; 431 addr_40 m_num_cache_mask; 247 sc_signal<bool> r_tgt_icache_req; // coherence request to ICACHE 248 sc_signal<bool> r_tgt_dcache_req; // coherence request to DCACHE 249 sc_signal<data_t> * r_tgt_buf; // [m_cache_words] 250 sc_signal<be_t> * r_tgt_be; // [m_cache_words] 251 252 sc_signal<int> r_cleanup_fsm; // send cleanup commands 253 sc_signal<size_t> r_cleanup_trdid; // index for trdid 254 GenericCam<vci_addr_t> r_cleanup_buffer; // registration buffer for cleanups 255 256 // ISS interface variables (used for communication 257 // between transition() and print_trace() functions 258 bool m_ireq_valid; 259 uint32_t m_ireq_addr; 260 soclib::common::Iss2::ExecMode m_ireq_mode; 261 262 bool m_irsp_valid; 263 uint32_t m_irsp_instruction; 264 bool m_irsp_error; 265 266 bool m_dreq_valid; 267 uint32_t m_dreq_addr; 268 soclib::common::Iss2::ExecMode m_dreq_mode; 269 soclib::common::Iss2::DataOperationType m_dreq_type; 270 uint32_t m_dreq_wdata; 271 uint8_t m_dreq_be; 272 273 bool m_drsp_valid; 274 uint32_t m_drsp_rdata; 275 bool m_drsp_error; 276 277 // Activity counters (for power consumption evaluation) 278 uint32_t m_conso_dcache_data_read; // DCACHE DATA READ activity 279 uint32_t m_conso_dcache_data_write; // DCACHE DATA WRITE activity 280 uint32_t m_conso_dcache_dir_read; // DCACHE DIR READ activity 281 uint32_t m_conso_dcache_dir_write; // DCACHE DIR WRITE activity 282 283 uint32_t m_conso_icache_data_read; // ICACHE DATA READ activity 284 uint32_t m_conso_icache_data_write; // ICACHE DATA WRITE activity 285 uint32_t m_conso_icache_dir_read; // ICACHE DIR READ activity 286 uint32_t m_conso_icache_dir_write; // ICACHE DIR WRITE activity 287 288 uint32_t m_conso_wbuf_read; // WBUF READ activity 289 uint32_t m_conso_wbuf_write; // WBUF WRITE activity 290 291 uint32_t m_cpt_cc_update_icache; // number of coherence update packets for icache 292 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets for dcache 293 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets for icache 294 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets for dcache 295 uint32_t m_cpt_cc_inval_broadcast; // number of coherence broadcast packets 296 297 uint32_t m_cpt_frz_cycles; // total number of cpu frozen cycles 298 uint32_t m_cpt_total_cycles; // total number of cycles from reset 299 uint32_t m_cpt_stop_simulation; // consecutive frozen cycles counter 300 301 uint32_t m_cpt_ins_cacheable; // number of cacheable instructions 302 uint32_t m_cpt_ins_uncacheable; // number of non cacheable instructions 303 uint32_t m_cpt_ins_miss; // number of cacheable instruction miss 304 305 uint32_t m_cpt_data_read_cacheable; // number of cacheable data read 306 uint32_t m_cpt_data_read_miss; // number of cacheable data read miss 307 uint32_t m_cpt_data_read_uncacheable; // number of non cacheable data read 308 uint32_t m_cpt_data_write_cacheable; // number of cacheable write 309 uint32_t m_cpt_data_write_uncacheable; // number of non cacheable write 310 uint32_t m_cpt_data_write_hit; // number of cacheable write making hit 311 uint32_t m_cpt_data_ll; // number of LL requests 312 uint32_t m_cpt_data_sc; // number of SC requests 313 314 uint32_t m_cpt_xtn_dcache_inval; // dcache line invalidation request 315 uint32_t m_cpt_xtn_sync; // write buffer flush request 316 317 uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer 318 uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss 319 uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss 320 321 uint32_t m_cpt_imiss_transaction; // number of VCI inst read miss transactions 322 uint32_t m_cpt_dmiss_transaction; // number of VCI data read miss transactions 323 uint32_t m_cpt_iunc_transaction; // number of VCI uncacheable inst read transactions 324 uint32_t m_cpt_dunc_transaction; // number of VCI uncacheable data read transactions 325 uint32_t m_cpt_write_transaction; // number of VCI write transactions 326 uint32_t m_cpt_sc_transaction; // number of VCI sc transactions 327 328 uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions 329 uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions 330 uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions 331 uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions 332 uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions 333 334 335 uint32_t * m_cpt_fsm_dcache; // array of number of cycles per state 336 uint32_t * m_cpt_fsm_icache; // array of number of cycles per state 337 uint32_t * m_cpt_fsm_cmd; // array of number of cycles per state 338 uint32_t * m_cpt_fsm_rsp; // array of number of cycles per state 339 uint32_t * m_cpt_fsm_tgt; // array of number of cycles per state 340 uint32_t * m_cpt_fsm_cleanup; // array of number of cycles per state 432 341 433 342 protected: … … 437 346 438 347 VciCcXCacheWrapperV4( 439 sc_module_name insname, 440 int proc_id, 441 const soclib::common::MappingTable &mtp, 442 const soclib::common::MappingTable &mtc, 443 const soclib::common::IntTab &initiator_index_rw, 444 const soclib::common::IntTab &initiator_index_c, 445 const soclib::common::IntTab &target_index, 446 size_t nb_cpu, 447 size_t nb_dcache, 448 size_t icache_ways, 449 size_t icache_sets, 450 size_t icache_words, 451 size_t dcache_ways, 452 size_t dcache_sets, 453 size_t dcache_words, 454 size_t wbuf_nwords, 455 size_t wbuf_nlines 456 ); 348 sc_module_name insname, 349 int proc_id, 350 const soclib::common::MappingTable &mtd, 351 const soclib::common::MappingTable &mtc, 352 const soclib::common::IntTab &initiator_index_d, 353 const soclib::common::IntTab &initiator_index_c, 354 const soclib::common::IntTab &target_index_c, 355 size_t icache_ways, 356 size_t icache_sets, 357 size_t icache_words, 358 size_t dcache_ways, 359 size_t dcache_sets, 360 size_t dcache_words, 361 size_t wbuf_nwords, 362 size_t wbuf_nlines, 363 uint32_t max_frozen_cycles = 1000); 457 364 458 365 ~VciCcXCacheWrapperV4(); 459 366 460 void print_trace(size_t mode = 0); 461 void print_cpi(); 462 void print_stats(bool print_wbuf=true, bool print_fsm=true); 463 464 void stop_simulation (uint32_t); 465 void log_transaction ( bool generate_file_icache 466 ,bool generate_file_dcache 467 ,bool generate_file_cmd 468 ,bool generate_file_tgt 469 ,bool generate_file_cleanup); 470 471 void vhdl_testbench (bool generate_file_mwbuf); 367 void print_trace(size_t mode = 0); 368 void print_cpi(); 369 void print_stats(bool print_wbuf=true, bool print_fsm=true); 472 370 473 371 private: … … 475 373 void transition(); 476 374 void genMoore(); 477 478 uint32_t get_num_cache (addr_40 & addr);479 uint32_t get_num_cache_only(addr_40 addr);480 void set_num_cache (addr_40 & addr, uint32_t num_cache);481 addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache);482 375 483 376 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); … … 487 380 }} 488 381 489 #endif /* SOCLIB_CABA_VCI_CC_ XCACHE_WRAPPER_V4_H */382 #endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */ 490 383 491 384 // Local Variables:
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