Index: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
===================================================================
--- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h	(revision 175)
+++ trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h	(revision 188)
@@ -1,3 +1,7 @@
 /* -*- c++ -*-
+ * File : vci_cc_xcache_wrapper_v4.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER
+ * Date : 27/11/2011
  *
  * SOCLIB_LGPL_HEADER_BEGIN
@@ -20,9 +24,4 @@
  * 
  * SOCLIB_LGPL_HEADER_END
- *
- * Copyright (c) UPMC, Lip6, SoC
- *         Alain Greiner <alain.greiner@lip6.fr>, 2008
- *
- * Maintainers: alain
  */
  
@@ -38,67 +37,10 @@
 #include "generic_cache.h"
 #include "generic_fifo.h"
+#include "generic_cam.h"
 #include "vci_initiator.h"
 #include "vci_target.h"
 #include "mapping_table.h"
 #include "static_assert.h"
-
-/*
- * ----------------------------------------------------------
- * Implementation
- * ----------------------------------------------------------
- *
- * CC_XCACHE_WRAPPER_MULTI_CACHE
- *     1    - icache static partitionnement
- *     2    - icache dedicated
- *
- * ----------------------------------------------------------
- * Debug
- * ----------------------------------------------------------
- *
- * CC_XCACHE_WRAPPER_STOP_SIMULATION
- *   stop simulation if processor is stall after a long time
- *   (configurable with "stop_simulation" function)
- *
- * CC_XCACHE_WRAPPER_DEBUG
- *   Add log to help the debugging
- *
- * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
- *   Number of cycle before to prinf debug message
- *
- * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
- *   Print transaction between :
- *     - the cpu and the cache (icache and dcache)
- *     - vci
- *     - cleanup
- *     - coherency
- *
- * MWBUF_VHDL_TESTBENCH
- *   generate a vhdl testbench for multi write buffer
- */
-
-// implementation
-#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
-#define CC_XCACHE_WRAPPER_MULTI_CACHE                 2
-// if multi_cache : 
-// <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1
-#endif
-  
-// debug
-#ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
-#define CC_XCACHE_WRAPPER_STOP_SIMULATION             1
-#endif
-#ifndef CC_XCACHE_WRAPPER_DEBUG
-#define CC_XCACHE_WRAPPER_DEBUG                       0
-#endif
-#ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
-#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN             1013300
-#endif
-#ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
-#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION      0
-#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log"
-#endif
-#ifndef MWBUF_VHDL_TESTBENCH
-#define MWBUF_VHDL_TESTBENCH                          0
-#endif
+#include "iss2.h"
 
 namespace soclib {
@@ -113,12 +55,11 @@
     : public soclib::caba::BaseModule
 {
-    typedef uint64_t            vhdl_tb_t;
-    typedef sc_dt::sc_uint<40> 	addr_40;
-    typedef uint32_t    	data_t;
-    typedef uint32_t    	tag_t;
-    typedef uint32_t    	be_t;
-    typedef typename vci_param::fast_addr_t vci_addr_t;
+    typedef uint32_t    			            data_t;
+    typedef uint32_t    			            tag_t;
+    typedef uint32_t    			            be_t;
+    typedef typename vci_param::fast_addr_t 	vci_addr_t;
     
-    enum dcache_fsm_state_e {
+    enum dcache_fsm_state_e 
+    {
         DCACHE_IDLE,
         DCACHE_WRITE_UPDT,
@@ -127,14 +68,15 @@
         DCACHE_MISS_UPDT,
         DCACHE_UNC_WAIT,
-        DCACHE_SC_WAIT,
         DCACHE_INVAL,
+        DCACHE_INVAL_GO,
         DCACHE_SYNC,
         DCACHE_ERROR,
         DCACHE_CC_CHECK,
         DCACHE_CC_INVAL,
-        DCACHE_CC_CLEANUP,
-    };
-
-    enum icache_fsm_state_e {
+        DCACHE_CC_UPDT,
+    };
+
+    enum icache_fsm_state_e 
+    {
         ICACHE_IDLE,
         ICACHE_MISS_VICTIM,
@@ -143,10 +85,11 @@
         ICACHE_UNC_WAIT,
         ICACHE_ERROR,
-        ICACHE_CC_CLEANUP, 
         ICACHE_CC_CHECK,
         ICACHE_CC_INVAL,
-    };
-
-    enum cmd_fsm_state_e {
+        ICACHE_CC_UPDT,
+    };
+
+    enum cmd_fsm_state_e 
+    {
         CMD_IDLE,
         CMD_INS_MISS,
@@ -158,5 +101,6 @@
     };
 
-    enum rsp_fsm_state_e {
+    enum rsp_fsm_state_e 
+    {
         RSP_IDLE,
         RSP_INS_MISS,
@@ -168,5 +112,6 @@
     };
 
-    enum tgt_fsm_state_e {
+    enum tgt_fsm_state_e 
+    {
         TGT_IDLE,
         TGT_UPDT_WORD,
@@ -180,18 +125,14 @@
     };
 
-    enum cleanup_fsm_state_e {
-        CLEANUP_IDLE,
-        CLEANUP_REQ,
-        CLEANUP_RSP_DCACHE,
-        CLEANUP_RSP_ICACHE,
-    };
-
-    enum transaction_type_c_e {
-        // convention with memcache
-        TYPE_DATA_CLEANUP = 0x0,
-        TYPE_INS_CLEANUP  = 0x1
-    };
-
-    enum transaction_type_rw_e {
+    enum cleanup_cmd_fsm_state_e 
+    {
+        CLEANUP_DATA_IDLE,
+        CLEANUP_INS_IDLE,
+        CLEANUP_DATA_GO,
+        CLEANUP_INS_GO,
+    };
+
+    enum transaction_type_d_e 
+    {
         // convention with memcache
         // b0 : 1 if cached
@@ -202,5 +143,4 @@
         TYPE_INS_UNC      = 0x2,
         TYPE_INS_MISS     = 0x3,
-        TYPE_DATA_SC      = 0x4, // sc is data and no cached
     };
 
@@ -210,224 +150,193 @@
     sc_in<bool>                             p_clk;
     sc_in<bool>                             p_resetn;
-    sc_in<bool>                          ** p_irq;//[m_nb_cpu][iss_t::n_irq];
-    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
+    sc_in<bool>                           * p_irq;		// [iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_d;
     soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
-    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt_c;
 
 private:
 
     // STRUCTURAL PARAMETERS
-    const soclib::common::AddressDecodingTable<vci_addr_t, bool>    m_cacheability_table;
-    const soclib::common::Segment                                   m_segment;
-    iss_t            ** m_iss; //[m_nb_cpu]
-    const uint32_t      m_srcid_rw;   
-    const uint32_t      m_srcid_c;   
+    const soclib::common::AddressDecodingTable<vci_addr_t, bool>    	m_cacheability_table;
+    const soclib::common::Segment                                   	m_segment;
+
+    const uint32_t       						m_srcid_d;   
+    const uint32_t       						m_srcid_c;   
     
-    const size_t         m_nb_cpu;
-    const size_t         m_nb_icache;
-    const size_t         m_nb_dcache;
-    const size_t         m_nb_cache;
-    const size_t         m_dcache_ways;
-    const size_t         m_dcache_words;
-    const uint32_t       m_dcache_words_shift;
-    const size_t         m_dcache_yzmask;
-    const size_t         m_icache_ways;
-    const size_t         m_icache_words;
-    const uint32_t       m_icache_words_shift;
-    const size_t         m_icache_yzmask;
-    const size_t         m_cache_words; // max between m_dcache_words and m_icache_words
-
-#if CC_XCACHE_WRAPPER_STOP_SIMULATION
-    bool                m_stop_simulation;
-    uint32_t            m_stop_simulation_nb_frz_cycles_max;
-    uint32_t          * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]
-#endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
-
-    // REGISTERS
-    sc_signal<uint32_t>     r_cpu_prior;
-    sc_signal<uint32_t>   * r_icache_lock;//[m_nb_icache]
-    sc_signal<uint32_t>   * r_dcache_lock;//[m_nb_dcache]
-    sc_signal<bool>       * r_dcache_sync;//[m_nb_dcache]
-
-    sc_signal<int>        * r_dcache_fsm;          //[m_nb_dcache]
-    sc_signal<int>        * r_dcache_fsm_save;     //[m_nb_dcache]
-    sc_signal<addr_40>    * r_dcache_addr_save;    //[m_nb_dcache]
-    sc_signal<data_t>     * r_dcache_wdata_save;   //[m_nb_dcache]
-    sc_signal<data_t>     * r_dcache_rdata_save;   //[m_nb_dcache]
-    sc_signal<int>        * r_dcache_type_save;    //[m_nb_dcache]
-    sc_signal<be_t>       * r_dcache_be_save;      //[m_nb_dcache]
-    sc_signal<bool>       * r_dcache_cached_save;  //[m_nb_dcache]
-    sc_signal<uint32_t>   * r_dcache_num_cpu_save; //[m_nb_dcache]
-    sc_signal<bool>       * r_dcache_cleanup_req;  //[m_nb_dcache]
-    sc_signal<addr_40>    * r_dcache_cleanup_line; //[m_nb_dcache]
-    sc_signal<bool>       * r_dcache_miss_req;     //[m_nb_dcache]
-    sc_signal<size_t>     * r_dcache_miss_way;     //[m_nb_dcache]
-    sc_signal<size_t>     * r_dcache_miss_set;     //[m_nb_dcache]
-    sc_signal<bool>       * r_dcache_unc_req;      //[m_nb_dcache]
-    sc_signal<bool>       * r_dcache_sc_req;       //[m_nb_dcache]
-    sc_signal<bool>       * r_dcache_inval_rsp;    //[m_nb_dcache]
-    sc_signal<size_t>     * r_dcache_update_addr;  //[m_nb_dcache]
-    sc_signal<data_t>    ** r_dcache_ll_data;      //[m_nb_dcache][m_nb_cpu]
-    sc_signal<addr_40>   ** r_dcache_ll_addr;      //[m_nb_dcache][m_nb_cpu]
-    sc_signal<bool>      ** r_dcache_ll_valid;     //[m_nb_dcache][m_nb_cpu]
-    sc_signal<bool>       * r_dcache_previous_unc; //[m_nb_dcache]
+    const size_t         						m_dcache_ways;
+    const size_t         						m_icache_ways;
+
+    const size_t         						m_cache_words;
+    const size_t         						m_cache_words_shift;
+    const vci_addr_t     						m_cache_yzmask;
+
+    const uint32_t							    m_max_frozen_cycles;
+
+    iss_t              			    * r_iss; 
+    MultiWriteBuffer<vci_addr_t>	* r_wbuf;
+    GenericCache<vci_addr_t> 		* r_icache;
+    GenericCache<vci_addr_t> 		* r_dcache;
+
+    sc_signal<int>          r_icache_fsm; 
+    sc_signal<int>          r_icache_fsm_save;		// return state for coherence request
+    sc_signal<vci_addr_t>   r_icache_addr_save;		// address requested by proc
+    sc_signal<bool>         r_icache_miss_req;		// set by icache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_icache_unc_req;		// set by icache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_icache_cleanup_req;	// a victim line must be evicted   
+    sc_signal<vci_addr_t>   r_icache_cleanup_line;	// address of the selected victim line
+    sc_signal<size_t>       r_icache_cleanup_way;	// way of the selected victim line
+    sc_signal<size_t>       r_icache_cleanup_set;	// set of the selected victim line
+    sc_signal<bool>         r_icache_miss_inval;	// cancellation request for pending miss 
+    sc_signal<size_t>       r_icache_update_word;	// word index for update (intern/extern)
+    sc_signal<data_t>       r_icache_unc_buf;       // Non cacheable read buffer (one word) 
+    sc_signal<bool>	        r_icache_unc_valid;     // Non cacheable read buffer valid
+    sc_signal<size_t>       r_icache_cc_way;        // way index for coherence request
+    sc_signal<size_t>       r_icache_cc_set;        // set index for coherence request
+
+    sc_signal<int>          r_dcache_fsm;
+    sc_signal<int>          r_dcache_fsm_save;		// return state when coherence request
+    sc_signal<vci_addr_t>   r_dcache_addr_save;		// address requested by proc
+    sc_signal<data_t>       r_dcache_wdata_save;	// data written (for dcache update)
+    sc_signal<be_t>         r_dcache_be_save;		// byte enable (for dcache update)
+    sc_signal<be_t>         r_dcache_way_save;		// selected way (in case of hit)
+    sc_signal<be_t>         r_dcache_set_save;		// selected set (in case of hit)
+    sc_signal<be_t>         r_dcache_word_save;		// selected word (in case of hit)
+    sc_signal<bool>         r_dcache_cleanup_req;	// a victim line must be evicted
+    sc_signal<vci_addr_t>   r_dcache_cleanup_line;	// address of the selected victim line
+    sc_signal<size_t>       r_dcache_cleanup_way;	// way of the selected victim line
+    sc_signal<size_t>       r_dcache_cleanup_set;	// set of the selected victim line
+    sc_signal<bool>         r_dcache_miss_req;		// set by dcache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_dcache_unc_req;		// set by dcache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_dcache_sc_req;		// set by dcache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_dcache_miss_inval;	// cancellation of a pending miss     
+    sc_signal<size_t>       r_dcache_update_word;	// word index for update (intern/extern)
+    sc_signal<data_t>       r_dcache_ll_data;		// LL reservation data
+    sc_signal<vci_addr_t>   r_dcache_ll_addr;		// ll reservation address
+    sc_signal<bool>         r_dcache_ll_valid;		// ll reservation valid
+    sc_signal<bool>	        r_dcache_pending_unc_write; // Non cacheable write pending
+    sc_signal<data_t>       r_dcache_unc_buf;       // Non cacheable read buffer (one word)
+    sc_signal<bool>	        r_dcache_unc_valid;     // Non cacheable read buffer valid 
+    sc_signal<size_t>       r_dcache_cc_way;        // way index for coherence request
+    sc_signal<size_t>       r_dcache_cc_set;        // set index for coherence request
                                                    
-    sc_signal<int>        * r_icache_fsm;          //[m_nb_icache]
-    sc_signal<int>        * r_icache_fsm_save;     //[m_nb_icache]
-    sc_signal<addr_40>    * r_icache_addr_save;    //[m_nb_icache]
-    sc_signal<bool>       * r_icache_miss_req;     //[m_nb_icache]
-    sc_signal<size_t>     * r_icache_miss_way;     //[m_nb_icache]
-    sc_signal<size_t>     * r_icache_miss_set;     //[m_nb_icache]
-    sc_signal<bool>       * r_icache_unc_req;      //[m_nb_icache]
-    sc_signal<bool>       * r_icache_cleanup_req;  //[m_nb_icache]
-    sc_signal<addr_40>    * r_icache_cleanup_line; //[m_nb_icache]
-    sc_signal<bool>       * r_icache_inval_rsp;    //[m_nb_icache]
-    sc_signal<size_t>     * r_icache_update_addr;  //[m_nb_icache]
-    sc_signal<bool>       * r_icache_buf_unc_valid;//[m_nb_icache]
-
     sc_signal<int>          r_vci_cmd_fsm;
-    sc_signal<size_t>       r_vci_cmd_min;       
-    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_min;       	// min word index for a write burst
+    sc_signal<size_t>       r_vci_cmd_max;       	// max word index for a write burst
     sc_signal<size_t>       r_vci_cmd_cpt;       
-    sc_signal<bool>         r_vci_cmd_dcache_prior;
-    sc_signal<uint32_t>     r_vci_cmd_num_icache_prior;
-    sc_signal<uint32_t>     r_vci_cmd_num_dcache_prior;
-    sc_signal<uint32_t>     r_vci_cmd_num_cache;
+    sc_signal<bool>         r_vci_cmd_imiss_prio;	// round-robin flip-flop to access wbuf
 
     sc_signal<int>          r_vci_rsp_fsm;
     sc_signal<size_t>       r_vci_rsp_cpt;  
-    sc_signal<uint32_t>     r_vci_rsp_num_cache;
-    sc_signal<bool>       * r_vci_rsp_ins_error;  //[m_nb_icache]
-    sc_signal<bool>       * r_vci_rsp_data_error; //[m_nb_dcache]
-
-    GenericFifo<data_t>     r_vci_rsp_fifo_icache_data;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache_num_cache;
-    GenericFifo<data_t>     r_vci_rsp_fifo_dcache_data;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache_num_cache;
-
-    data_t                * r_tgt_buf;            //[m_cache_words]
-    be_t                  * r_tgt_be;             //[m_cache_words]
-    sc_signal<uint32_t>     r_cache_word;
-
-    sc_signal<int>          r_vci_tgt_fsm;
-    sc_signal<addr_40>      r_tgt_iaddr;
-    sc_signal<addr_40>      r_tgt_daddr;
-    sc_signal<size_t>       r_tgt_word;
-    sc_signal<bool>         r_tgt_update;
-    sc_signal<bool>         r_tgt_update_data;
-  //sc_signal<bool>         r_tgt_brdcast;
+    sc_signal<bool>         r_vci_rsp_ins_error;	// set by rsp_fsm / reset by icache_fsm
+    sc_signal<bool>         r_vci_rsp_data_error;	// set by rsp_fsm / reset by dcache_fsm
+    GenericFifo<data_t>     r_vci_rsp_fifo_icache;	// response fifo to ICACHE FSM
+    GenericFifo<data_t>     r_vci_rsp_fifo_dcache;	// response FIFO to DCACHE FSM
+
+    sc_signal<int>          r_tgt_fsm;			    // target port on coherence network
+    sc_signal<bool>         r_tgt_icache_rsp;		// VCI response required when true
+    sc_signal<bool>         r_tgt_dcache_rsp;		// VCI response required when true
+    sc_signal<vci_addr_t>   r_tgt_addr;			    // address of the target line
+    sc_signal<size_t>       r_tgt_word_min;		    // index of the first word to be updated
+    sc_signal<size_t>       r_tgt_word_max;		    // index of the last word to be updated
+    sc_signal<size_t>       r_tgt_word_count;		// word counter to fill the tgt_buf
+    sc_signal<bool>         r_tgt_update;		    // update request when true
+    sc_signal<bool>         r_tgt_update_data;  	// update_data request when true
     sc_signal<size_t>       r_tgt_srcid;
     sc_signal<size_t>       r_tgt_pktid;
     sc_signal<size_t>       r_tgt_trdid;
-  //sc_signal<size_t>       r_tgt_plen;
-    sc_signal<uint32_t>     r_tgt_num_cache;
-    sc_signal<bool>       * r_tgt_icache_req; //[m_nb_icache]
-    sc_signal<bool>       * r_tgt_icache_rsp; //[m_nb_icache]
-    sc_signal<bool>       * r_tgt_dcache_req; //[m_nb_dcache]
-    sc_signal<bool>       * r_tgt_dcache_rsp; //[m_nb_dcache]
-
-    sc_signal<int>          r_cleanup_fsm;		// controls initiator port of the coherence network
-    sc_signal<uint32_t>     r_cleanup_num_cache;
-    sc_signal<bool>         r_cleanup_icache;
-
-    MultiWriteBuffer<addr_40>** r_wbuf;
-    GenericCache<vci_addr_t> ** r_icache;
-    GenericCache<vci_addr_t> ** r_dcache;
-
-#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
-    bool                        generate_log_transaction_file_icache;
-    bool                        generate_log_transaction_file_dcache;
-    bool                        generate_log_transaction_file_cmd;
-    bool                        generate_log_transaction_file_tgt;
-    bool                        generate_log_transaction_file_cleanup;
-
-    std::ofstream             * log_transaction_file_icache; //[m_nb_cpu]
-    std::ofstream             * log_transaction_file_dcache; //[m_nb_cpu]
-    std::ofstream               log_transaction_file_cmd;
-    std::ofstream               log_transaction_file_tgt;
-    std::ofstream               log_transaction_file_cleanup;
-#endif
-
-#if MWBUF_VHDL_TESTBENCH
-    bool                        simulation_started;
-    bool                        generate_vhdl_testbench_mwbuf;
-    std::ofstream             * vhdl_testbench_mwbuf; //[m_nb_dcache]
-#endif
-
-    // Activity counters
-    uint32_t   m_cpt_dcache_data_read;             // * DCACHE DATA READ
-    uint32_t   m_cpt_dcache_data_write;            // * DCACHE DATA WRITE
-    uint32_t   m_cpt_dcache_dir_read;              // * DCACHE DIR READ
-    uint32_t   m_cpt_dcache_dir_write;             // * DCACHE DIR WRITE
-                                                   
-    uint32_t   m_cpt_icache_data_read;             // * ICACHE DATA READ
-    uint32_t   m_cpt_icache_data_write;            // * ICACHE DATA WRITE
-    uint32_t   m_cpt_icache_dir_read;              // * ICACHE DIR READ
-    uint32_t   m_cpt_icache_dir_write;             // * ICACHE DIR WRITE
-               
-    uint32_t   m_cpt_cc_update_icache;             // number of coherence update packets (for icache)
-    uint32_t   m_cpt_cc_update_dcache;             // number of coherence update packets (for dcache)
-    uint32_t   m_cpt_cc_inval_broadcast;           // number of coherence inval packets
-    uint32_t   m_cpt_cc_inval_icache;              // number of coherence inval packets
-    uint32_t   m_cpt_cc_inval_dcache;              // number of coherence inval packets
-    uint32_t   m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
-    uint32_t   m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
-               
-    uint32_t * m_cpt_frz_cycles;	               // * number of cycles where the cpu is frozen
-    uint32_t   m_cpt_total_cycles;	               // total number of cycles 
-               
-    uint32_t   m_cpt_data_read;                    //   number of data read
-    uint32_t   m_cpt_data_read_miss;               //   number of data read miss
-    uint32_t   m_cpt_data_read_uncached;           //   number of data read uncached
-    uint32_t   m_cpt_data_write;                   //   number of data write
-    uint32_t   m_cpt_data_write_miss;              //   number of data write miss
-    uint32_t   m_cpt_data_write_uncached;          //   number of data write uncached
-    uint32_t   m_cpt_ins_miss;                     // * number of instruction miss
-               
-    uint32_t   m_cost_write_frz;                   // * number of frozen cycles related to write buffer         
-    uint32_t   m_cost_data_miss_frz;               // * number of frozen cycles related to data miss
-    uint32_t   m_cost_unc_read_frz;                // * number of frozen cycles related to uncached read
-    uint32_t   m_cost_ins_miss_frz;                // * number of frozen cycles related to ins miss
-               
-    uint32_t   m_cpt_imiss_transaction;            // * number of VCI instruction miss transactions
-    uint32_t   m_cpt_dmiss_transaction;            // * number of VCI data miss transactions
-    uint32_t   m_cpt_unc_transaction;              // * number of VCI uncached read transactions
-    uint32_t   m_cpt_data_write_transaction;       // * number of VCI write transactions
-               
-    uint32_t   m_cost_imiss_transaction;           // * cumulated duration for VCI IMISS transactions
-    uint32_t   m_cost_dmiss_transaction;           // * cumulated duration for VCI DMISS transactions
-    uint32_t   m_cost_unc_transaction;             // * cumulated duration for VCI UNC transactions
-    uint32_t   m_cost_write_transaction;           // * cumulated duration for VCI WRITE transactions
-    uint32_t   m_length_write_transaction;         // * cumulated length for VCI WRITE transactions
-
-    uint32_t * m_cpt_icache_access; //[m_nb_icache]
-    uint32_t * m_cpt_dcache_access; //[m_nb_dcache]
-    uint32_t * m_cpt_dcache_hit_after_miss_read;  //[m_nb_dcache]
-    uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache]
-    uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache]
-    uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache]
-    uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache]
-
-    uint32_t ** m_cpt_fsm_dcache;  //[m_nb_dcache]
-    uint32_t ** m_cpt_fsm_icache;  //[m_nb_icache]
-    uint32_t  * m_cpt_fsm_cmd;
-    uint32_t  * m_cpt_fsm_rsp;
-    uint32_t  * m_cpt_fsm_tgt;
-    uint32_t  * m_cpt_fsm_cleanup;
-
-    // Non blocking multi-cache
-    typename iss_t::InstructionRequest  * ireq        ; //[m_nb_icache]
-    typename iss_t::InstructionResponse * irsp        ; //[m_nb_icache]
-    bool                                * ireq_cached ; //[m_nb_icache]
-    uint32_t                            * ireq_num_cpu; //[m_nb_dcache]
-    typename iss_t::DataRequest         * dreq        ; //[m_nb_dcache]
-    typename iss_t::DataResponse        * drsp        ; //[m_nb_dcache]
-    bool                                * dreq_cached ; //[m_nb_dcache]
-    uint32_t                            * dreq_num_cpu; //[m_nb_dcache]
-
-    const uint32_t m_num_cache_LSB;
-    const uint32_t m_num_cache_MSB;
-          addr_40  m_num_cache_LSB_mask;
-          addr_40  m_num_cache_mask;
+    sc_signal<bool>         r_tgt_icache_req; 		// coherence request to ICACHE
+    sc_signal<bool>         r_tgt_dcache_req;		// coherence request to DCACHE
+    sc_signal<data_t>     * r_tgt_buf;          	// [m_cache_words]
+    sc_signal<be_t>       * r_tgt_be;           	// [m_cache_words]
+
+    sc_signal<int>          r_cleanup_fsm;	        // send cleanup commands
+    sc_signal<size_t>       r_cleanup_trdid;        // index for trdid
+    GenericCam<vci_addr_t>  r_cleanup_buffer;       // registration buffer for cleanups
+
+    // ISS interface variables (used for communication 
+    // between transition() and print_trace() functions
+    bool					                m_ireq_valid;
+    uint32_t				                m_ireq_addr;
+    soclib::common::Iss2::ExecMode		    m_ireq_mode;
+	
+    bool					                m_irsp_valid;
+    uint32_t				                m_irsp_instruction;
+    bool					                m_irsp_error;
+	
+    bool					                m_dreq_valid;
+    uint32_t				                m_dreq_addr;
+    soclib::common::Iss2::ExecMode		    m_dreq_mode;
+    soclib::common::Iss2::DataOperationType	m_dreq_type;
+    uint32_t					            m_dreq_wdata;
+    uint8_t					                m_dreq_be;
+
+    bool					                m_drsp_valid;
+    uint32_t					            m_drsp_rdata;
+    bool					                m_drsp_error;
+
+    // Activity counters (for power consumption evaluation)
+    uint32_t   m_conso_dcache_data_read;           // DCACHE DATA READ activity
+    uint32_t   m_conso_dcache_data_write;          // DCACHE DATA WRITE activity
+    uint32_t   m_conso_dcache_dir_read;            // DCACHE DIR READ activity
+    uint32_t   m_conso_dcache_dir_write;           // DCACHE DIR WRITE activity
+                                                  
+    uint32_t   m_conso_icache_data_read;           // ICACHE DATA READ activity
+    uint32_t   m_conso_icache_data_write;          // ICACHE DATA WRITE activity
+    uint32_t   m_conso_icache_dir_read;            // ICACHE DIR READ activity
+    uint32_t   m_conso_icache_dir_write;           // ICACHE DIR WRITE activity
+               
+    uint32_t   m_conso_wbuf_read;		           // WBUF READ activity
+    uint32_t   m_conso_wbuf_write;		           // WBUF WRITE activity
+
+    uint32_t   m_cpt_cc_update_icache;             // number of coherence update packets for icache
+    uint32_t   m_cpt_cc_update_dcache;             // number of coherence update packets for dcache
+    uint32_t   m_cpt_cc_inval_icache;              // number of coherence inval packets	for icache
+    uint32_t   m_cpt_cc_inval_dcache;              // number of coherence inval packets for dcache
+    uint32_t   m_cpt_cc_inval_broadcast;           // number of coherence broadcast packets
+               
+    uint32_t   m_cpt_frz_cycles;	               // total number of cpu frozen cycles
+    uint32_t   m_cpt_total_cycles;	               // total number of cycles from reset
+    uint32_t   m_cpt_stop_simulation;	   	       // consecutive frozen cycles counter 
+               
+    uint32_t   m_cpt_ins_cacheable;                // number of cacheable instructions 
+    uint32_t   m_cpt_ins_uncacheable;              // number of non cacheable instructions
+    uint32_t   m_cpt_ins_miss;                     // number of cacheable instruction miss
+               
+    uint32_t   m_cpt_data_read_cacheable;          // number of cacheable data read
+    uint32_t   m_cpt_data_read_miss;               // number of cacheable data read miss
+    uint32_t   m_cpt_data_read_uncacheable;        // number of non cacheable data read 
+    uint32_t   m_cpt_data_write_cacheable;         // number of cacheable write
+    uint32_t   m_cpt_data_write_uncacheable;       // number of non cacheable write
+    uint32_t   m_cpt_data_write_hit;               // number of cacheable write making hit
+    uint32_t   m_cpt_data_ll;			           // number of LL requests
+    uint32_t   m_cpt_data_sc;			           // number of SC requests
+
+    uint32_t   m_cpt_xtn_dcache_inval;		       // dcache line invalidation request
+    uint32_t   m_cpt_xtn_sync;		               // write buffer flush request
+
+    uint32_t   m_cost_write_frz;                   // number of frozen cycles related to write buffer 
+    uint32_t   m_cost_data_miss_frz;               // number of frozen cycles related to data miss
+    uint32_t   m_cost_ins_miss_frz;                // number of frozen cycles related to ins miss
+               
+    uint32_t   m_cpt_imiss_transaction;            // number of VCI inst read miss transactions
+    uint32_t   m_cpt_dmiss_transaction;            // number of VCI data read miss transactions
+    uint32_t   m_cpt_iunc_transaction;             // number of VCI uncacheable inst read transactions
+    uint32_t   m_cpt_dunc_transaction;             // number of VCI uncacheable data read transactions
+    uint32_t   m_cpt_write_transaction;            // number of VCI write transactions
+    uint32_t   m_cpt_sc_transaction;               // number of VCI sc transactions
+               
+    uint32_t   m_cost_imiss_transaction;           // cumulated duration for VCI IMISS transactions
+    uint32_t   m_cost_dmiss_transaction;           // cumulated duration for VCI DMISS transactions
+    uint32_t   m_cost_unc_transaction;             // cumulated duration for VCI UNC transactions
+    uint32_t   m_cost_write_transaction;           // cumulated duration for VCI WRITE transactions
+    uint32_t   m_length_write_transaction;         // cumulated length for VCI WRITE transactions
+
+
+    uint32_t * m_cpt_fsm_dcache;  		   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_icache; 		   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_cmd;			   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_rsp;			   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_tgt;			   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_cleanup;		   // array of number of cycles per state
 
 protected:
@@ -437,37 +346,26 @@
 
     VciCcXCacheWrapperV4(
-                       sc_module_name insname,
-                       int proc_id,
-                       const soclib::common::MappingTable &mtp,
-                       const soclib::common::MappingTable &mtc,
-                       const soclib::common::IntTab &initiator_index_rw,
-                       const soclib::common::IntTab &initiator_index_c,
-                       const soclib::common::IntTab &target_index,
-                       size_t nb_cpu,
-                       size_t nb_dcache,
-                       size_t icache_ways,
-                       size_t icache_sets,
-                       size_t icache_words,
-                       size_t dcache_ways,
-                       size_t dcache_sets,
-                       size_t dcache_words,
-                       size_t wbuf_nwords,
-                       size_t wbuf_nlines
-                         );
+                       sc_module_name 				insname,
+                       int 					proc_id,
+                       const soclib::common::MappingTable 	&mtd,
+                       const soclib::common::MappingTable 	&mtc,
+                       const soclib::common::IntTab 		&initiator_index_d,
+                       const soclib::common::IntTab 		&initiator_index_c,
+                       const soclib::common::IntTab 		&target_index_c,
+                       size_t 					icache_ways,
+                       size_t 					icache_sets,
+                       size_t 					icache_words,
+                       size_t 					dcache_ways,
+                       size_t 					dcache_sets,
+                       size_t 					dcache_words,
+                       size_t 					wbuf_nwords,
+                       size_t 					wbuf_nlines,
+                       uint32_t					max_frozen_cycles = 1000);
 
     ~VciCcXCacheWrapperV4();
 
-  void print_trace(size_t mode = 0);
-  void print_cpi();
-  void print_stats(bool print_wbuf=true, bool print_fsm=true);
-
-  void stop_simulation (uint32_t);
-  void log_transaction ( bool generate_file_icache
-                        ,bool generate_file_dcache
-                        ,bool generate_file_cmd
-                        ,bool generate_file_tgt
-                        ,bool generate_file_cleanup);
-
-  void vhdl_testbench (bool generate_file_mwbuf);
+    void print_trace(size_t mode = 0);
+    void print_cpi();
+    void print_stats(bool print_wbuf=true, bool print_fsm=true);
 
 private:
@@ -475,9 +373,4 @@
     void transition();
     void genMoore();
-
-    uint32_t get_num_cache     (addr_40 & addr);
-    uint32_t get_num_cache_only(addr_40   addr);
-    void     set_num_cache     (addr_40 & addr, uint32_t num_cache);
-    addr_40  set_num_cache_only(addr_40   addr, uint32_t num_cache);
 
     soclib_static_assert((int)iss_t::SC_ATOMIC     == (int)vci_param::STORE_COND_ATOMIC);
@@ -487,5 +380,5 @@
 }}
 
-#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */
 
 // Local Variables:
