Index: /trunk/platforms/tsarv4_generic_mmu/Makefile =================================================================== --- /trunk/platforms/tsarv4_generic_mmu/Makefile (revision 189) +++ /trunk/platforms/tsarv4_generic_mmu/Makefile (revision 189) @@ -0,0 +1,8 @@ + +simulator.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x tty* + Index: /trunk/platforms/tsarv4_generic_mmu/soclib.conf =================================================================== --- /trunk/platforms/tsarv4_generic_mmu/soclib.conf (revision 189) +++ /trunk/platforms/tsarv4_generic_mmu/soclib.conf (revision 189) @@ -0,0 +1,2 @@ +config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI']) + Index: /trunk/platforms/tsarv4_generic_mmu/top.cpp =================================================================== --- /trunk/platforms/tsarv4_generic_mmu/top.cpp (revision 189) +++ /trunk/platforms/tsarv4_generic_mmu/top.cpp (revision 189) @@ -0,0 +1,803 @@ +///////////////////////////////////////////////////////////////////////// +// File: top.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : june 2011 +// This program is released under the GNU public license +///////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture with virtual memory. +// - It uses vci_local_crossbar as local interconnect +// - It uses virtual_dspin as global interconnect +// - It uses the vci_cc_vcache_wrapper_v4 +// - It uses the vci_mem_cache_v4 +// - It uses one vci_xicu, one vci_multi_tty, +// and one vci_multi_dma controler per cluster. +// +// It is build with one single component implementing a cluster: +// The Tsarv4ClusterMmu component is defined in files +// tsarv4_cluster_mmu.* (with * = cpp, h, sd) +// +// The physical address space is 32 bits. +// The number of clusters cannot be larger than 256. +// The number of processors per cluster cannot be larger than 4. +// The parameters must be power of 2. +// - xmax : number of clusters in a row +// - ymax : number of clusters in a column +// - nprocs : number of processors per cluster +// +// The peripherals BDEV, FBUF, and the boot BROM +// are in the cluster containing address 0xBFC00000. +// - The nprocs TTY IRQs are connected to IRQ_IN[0] to IRQ_IN[3] +// - The nprocs DMA IRQs are connected to IRQ_IN[4] to IRQ_IN[7] +// - The IOC IRQ is connected to IRQ_IN[8] +// +// General policy for 32 bits physical address decoding: +// All segments base addresses are multiple of 64 Kbytes +// Therefore the 16 address MSB bits completely define the target: +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the 8 LSB bits define the local index: +// | X_ID | Y_ID |---| LADR | OFFSET | +// |x_width|y_width|---| 8 | 16 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "tsarv4_cluster_mmu.h" +#include "alloc_elems.h" + +/////////////////////////////////////////////////// +// OS +/////////////////////////////////////////////////// + +#define USE_ALMOS 1 +#define almos_bootloader_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/bootloader/bin/bootloader-soclib-mipsel.bin" +#define almos_kernel_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/kernel/bin/kernel-soclib-mipsel.bin@0xbfc10000:D" +#define almos_archinfo_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/arch_bins/arch-info_4_4.bin@0xBFC08000:D" + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// + +#define USE_OPENMP 0 +#define OPENMP_THREADS_NR 8 + +#if USE_OPENMP +#include +#endif + +// cluster index (computed from x,y coordinates) +#define cluster(x,y) (y + ymax*x) + +// flit widths for the DSPIN network +#define cmd_width 40 +#define rsp_width 33 + +// VCI format +#define cell_width 4 +#define address_width 32 +#define plen_width 8 +#define error_width 2 +#define clen_width 1 +#define rflag_width 1 +#define srcid_width 14 +#define pktid_width 4 +#define trdid_width 4 +#define wrplen_width 1 + +/////////////////////////////////////////////////// +// Parameters default values +/////////////////////////////////////////////////// + +#define MESH_XMAX 2 +#define MESH_YMAX 2 + +#define NPROCS 1 +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 + +#define BDEV_SECTOR_SIZE 128 +#define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw" + +#define BOOT_SOFT_NAME "../../softs/soft_transpose_giet/bin.soft" + +#define MAX_FROZEN_CYCLES 1000 + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// +// There is 3 segments replicated in all clusters: +// - seg_memc -> MEMC / BASE = 0x**000000 (12 M bytes) +// - seg_icu -> ICU / BASE = 0x**F00000 +// - seg_dma -> CDMA / BASE = 0x**F30000 +// +// There is 4 specific segments in the "IO" cluster +// (containing address 0xBF000000) +// - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) +// - seg_fbuf -> FBUF / BASE = 0xBFD00000 (2 M bytes) +// - seg_bdev -> BDEV / BASE = 0xBFF10000 +// - seg_tty -> MTTY / BASE = 0x**F20000 +// +// There is one special segment corresponding to +// the processors in the coherence address space +// - seg_proc -> PROC / BASE = 0x**B0 to 0xBF +/////////////////////////////////////////////////// + +// specific segments in "IO" cluster + +#define BROM_BASE 0xBFC00000 +#define BROM_SIZE 0x00100000 + +#define FBUF_BASE 0xBFD00000 +#define FBUF_SIZE 0x00200000 + +#define BDEV_BASE 0xBFF10000 +#define BDEV_SIZE 0x00000020 + +#define MTTY_BASE 0xBFF20000 +#define MTTY_SIZE 0x00000040 + +// replicated segments + +#define MEMC_BASE 0x00000000 +#define MEMC_SIZE 0x00C00000 + +#define XICU_BASE 0x00F00000 +#define XICU_SIZE 0x00001000 + +#define CDMA_BASE 0x00F30000 +#define CDMA_SIZE 0x00004000 + +#define PROC_BASE 0x00D00000 +#define PROC_SIZE 0x00000010 + +//////////////////////////////////////////////////////////////////// +// TGTID definition in direct space +// For all components: global TGTID = global SRCID = cluster_index +//////////////////////////////////////////////////////////////////// + +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define CDMA_TGTID 2 +#define MTTY_TGTID 3 +#define FBUF_TGTID 4 +#define BROM_TGTID 5 +#define BDEV_TGTID 6 + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + + char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code + size_t ncycles = 1000000000; // simulated cycles + size_t xmax = MESH_XMAX; // number of clusters in a row + size_t ymax = MESH_YMAX; // number of clusters in a column + size_t nprocs = NPROCS; // number of processors per cluster + size_t xfb = FBUF_X_SIZE; // frameBuffer column number + size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number + size_t memc_ways = MEMC_WAYS; + size_t memc_sets = MEMC_SETS; + size_t l1_d_ways = L1_DWAYS; + size_t l1_d_sets = L1_DSETS; + size_t l1_i_ways = L1_IWAYS; + size_t l1_i_sets = L1_ISETS; + char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image + size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) + size_t xram_latency = XRAM_LATENCY; // external RAM latency + bool trace_ok = false; // trace activated + size_t trace_period = 1; // trace period + uint32_t from_cycle = 0; // debug start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for( int n=1 ; n vci_param; + + size_t cluster_io_index; + size_t x_width; + size_t y_width; + + if (xmax == 1) x_width = 0; + else if (xmax == 2) x_width = 1; + else if (xmax <= 4) x_width = 2; + else if (xmax <= 8) x_width = 3; + else x_width = 4; + + if (ymax == 1) y_width = 0; + else if (ymax == 2) y_width = 1; + else if (ymax <= 4) y_width = 2; + else if (ymax <= 8) y_width = 3; + else y_width = 4; + + cluster_io_index = 0xBF >> (8 - x_width - y_width); + + ///////////////////// + // Mapping Tables + ///////////////////// + + // direct network + MappingTable maptabd(address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, srcid_width - x_width - y_width), + 0x00FF0000); + + for ( size_t x = 0 ; x < xmax ; x++) + { + for ( size_t y = 0 ; y < ymax ; y++) + { + sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); + + std::ostringstream sh; + sh << "d_seg_memc_" << x << "_" << y; + maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); + + std::ostringstream si; + si << "d_seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); + + std::ostringstream sd; + sd << "d_seg_mdma_" << x << "_" << y; + maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); + + if ( cluster(x,y) == cluster_io_index ) + { + maptabd.add(Segment("d_seg_mtty ", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); + maptabd.add(Segment("d_seg_fbuf ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); + maptabd.add(Segment("d_seg_bdev ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); + maptabd.add(Segment("d_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); + } + } + } + std::cout << maptabd << std::endl; + + // coherence network + // - tgtid_c_proc = srcid_c_proc = local procid + // - tgtid_c_memc = srcid_c_memc = nprocs + MappingTable maptabc(address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, srcid_width - x_width - y_width), + 0x00FF0000); + + for ( size_t x = 0 ; x < xmax ; x++) + { + for ( size_t y = 0 ; y < ymax ; y++) + { + sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); + + // cleanup requests regarding the memc segment must be routed to the memory cache + std::ostringstream sh; + sh << "c_seg_memc_" << x << "_" << y; + maptabc.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y), nprocs), false)); + + // cleanup requests regarding the BROM segment are also be routed to the memory cache + if ( cluster(x,y) == cluster_io_index ) + { + maptabc.add(Segment("c_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false)); + } + + // update & invalidate requests must be routed to the proper processor + for ( size_t p = 0 ; p < nprocs ; p++) + { + std::ostringstream sp; + sp << "c_seg_proc_" << x << "_" << y << "_" << p; + maptabc.add(Segment(sp.str(), PROC_BASE+offset+(p*0x10000), PROC_SIZE, + IntTab(cluster(x,y), p), false, true, IntTab(cluster(x,y), p))); + } + } + } + std::cout << maptabc << std::endl; + + // external network + MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); + + for ( size_t x = 0 ; x < xmax ; x++) + { + for ( size_t y = 0 ; y < ymax ; y++) + { + sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); + std::ostringstream sh; + sh << "x_seg_memc_" << x << "_" << y; + maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false)); + } + } + std::cout << maptabx << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + // Horizontal inter-clusters DSPIN signals + DspinSignals*** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2); + DspinSignals*** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2); + DspinSignals*** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2); + DspinSignals*** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2); + + // Vertical inter-clusters DSPIN signals + DspinSignals*** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2); + DspinSignals*** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2); + DspinSignals*** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2); + DspinSignals*** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2); + + // Mesh boundaries DSPIN signals + DspinSignals**** signal_dspin_false_cmd_in = + alloc_elems >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4); + DspinSignals**** signal_dspin_false_cmd_out = + alloc_elems >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4); + DspinSignals**** signal_dspin_false_rsp_in = + alloc_elems >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4); + DspinSignals**** signal_dspin_false_rsp_out = + alloc_elems >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4); + + + //////////////////////////// + // Components + //////////////////////////// + +#if USE_ALMOS + soclib::common::Loader loader(almos_bootloader_pathname, + almos_archinfo_pathname, + almos_kernel_pathname); +#else + soclib::common::Loader loader(soft_name); +#endif + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + TsarV4ClusterMmu* clusters[xmax][ymax]; + +#if USE_OPENMP + +#pragma omp parallel +{ +#pragma omp for + for( size_t i = 0 ; i < (xmax * ymax); i++) + { + size_t x = i / ymax; + size_t y = i % ymax; + +#pragma omp critical + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarV4ClusterMmu + (sc.str().c_str(), + nprocs, + x, + y, + cluster(x,y), + maptabd, + maptabc, + maptabx, + x_width, + y_width, + MEMC_TGTID, + XICU_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + BDEV_TGTID, + CDMA_TGTID, + memc_ways, + memc_sets, + l1_i_ways, + l1_i_sets, + l1_d_ways, + l1_d_sets, + xram_latency, + (cluster(x,y) == cluster_io_index), + xfb, + yfb, + disk_name, + blk_size, + loader, + frozen_cycles, + from_cycle, + trace_ok and (cluster_io_index == cluster(x,y)) ); + } + +#else // NO OPENMP + + for( size_t x = 0 ; x < xmax ; x++) + { + for( size_t y = 0 ; y < ymax ; y++ ) + { + +std::cout << "building cluster_" << x << "_" << y << std::endl; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarV4ClusterMmu + (sc.str().c_str(), + nprocs, + x, + y, + cluster(x,y), + maptabd, + maptabc, + maptabx, + x_width, + y_width, + MEMC_TGTID, + XICU_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + BDEV_TGTID, + CDMA_TGTID, + memc_ways, + memc_sets, + l1_i_ways, + l1_i_sets, + l1_d_ways, + l1_d_sets, + xram_latency, + (cluster(x,y) == cluster_io_index), + xfb, + yfb, + disk_name, + blk_size, + loader, + frozen_cycles, + from_cycle, + trace_ok and (cluster_io_index == cluster(x,y)) ); + +std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; + + } + } + +#endif // USE_OPENMP + + /////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////// + + // Clock & RESET + for ( size_t x = 0 ; x < (xmax) ; x++ ) + { + for ( size_t y = 0 ; y < ymax ; y++ ) + { + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if ( xmax > 1 ) + { + for ( size_t x = 0 ; x < (xmax-1) ; x++ ) + { + for ( size_t y = 0 ; y < ymax ; y++ ) + { + for ( size_t k = 0 ; k < 2 ; k++ ) + { + clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); + clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); + } + } + } + } + std::cout << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if ( ymax > 1 ) + { + for ( size_t y = 0 ; y < (ymax-1) ; y++ ) + { + for ( size_t x = 0 ; x < xmax ; x++ ) + { + for ( size_t k = 0 ; k < 2 ; k++ ) + { + clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); + clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); + } + } + } + } + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for ( size_t y = 0 ; y < ymax ; y++ ) + { + for ( size_t k = 0 ; k < 2 ; k++ ) + { + clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); + clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); + clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); + clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); + + clusters[xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]); + clusters[xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]); + clusters[xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]); + clusters[xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]); + } + } + + // North & South boundary clusters connections + for ( size_t x = 0 ; x < xmax ; x++ ) + { + for ( size_t k = 0 ; k < 2 ; k++ ) + { + clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); + clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); + clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); + clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); + + clusters[x][ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]); + clusters[x][ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]); + clusters[x][ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]); + clusters[x][ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]); + } + } + + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // network boundaries signals + for(size_t x=0; x from_cycle) and (n%trace_period == 0) ) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ************************************************" << std::endl; + + // components cluster 00 ///////////////////// +// clusters[0][0]->proc[0]->print_trace(); +// clusters[0][0]->memc->print_trace(); + + // signals cluster 00 //////////////////////// +// clusters[0][0]->signal_vci_ini_d_proc[0].print_trace("proc_0_0_0_ini_d"); +// clusters[0][0]->signal_vci_ini_c_proc[0].print_trace("proc_0_0_0_ini_c"); +// clusters[0][0]->signal_vci_tgt_c_proc[0].print_trace("proc_0_0_0_tgt_c"); +// clusters[0][0]->signal_vci_xram.print_trace("memc_0_0_xram"); + + // components cluster 01 ///////////////////// +// clusters[0][1]->proc[0]->print_trace(); +// clusters[0][1]->memc->print_trace(); + + // signals cluster 01 /////////////////////// +// clusters[0][1]->signal_vci_ini_d_proc[0].print_trace("proc_0_1_0_ini_d"); +// clusters[0][1]->signal_vci_ini_c_proc[0].print_trace("proc_0_1_0_ini_c"); +// clusters[0][1]->signal_vci_tgt_c_proc[0].print_trace("proc_0_1_0_tgt_c"); +// clusters[0][1]->signal_vci_xram.print_trace("memc_0_1_xram"); + + // components cluster 10 //////////////////// + clusters[1][0]->proc[0]->print_trace(1); + clusters[1][0]->memc->print_trace(); +// clusters[1][0]->bdev->print_trace(); +// clusters[1][0]->mdma->print_trace(); + + // signals cluster 10 /////////////////////// + clusters[1][0]->signal_vci_ini_d_proc[0].print_trace("proc_1_0_0_ini_d"); +// clusters[1][0]->signal_vci_ini_c_proc[0].print_trace("proc_1_0_0_ini_c"); +// clusters[1][0]->signal_vci_tgt_c_proc[0].print_trace("proc_1_0_0_tgt_c"); + clusters[1][0]->signal_vci_tgt_d_memc.print_trace("memc_1_0_tgt_d "); +// clusters[1][0]->signal_vci_ini_c_memc.print_trace("memc_1_0_ini_c "); +// clusters[1][0]->signal_vci_tgt_c_memc.print_trace("memc_1_0_tgt_c "); +// clusters[1][0]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); +// clusters[1][0]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); +// clusters[1][0]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); +// clusters[1][0]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); + clusters[1][0]->signal_vci_tgt_d_mtty.print_trace("mtty_1_0_tgt_d "); + clusters[1][0]->signal_vci_xram.print_trace("memc_1_0_xram"); + + // components cluster 11 ///////////////////// +// clusters[1][1]->proc[0]->print_trace(); +// clusters[1][1]->memc->print_trace(); + + // signals cluster 11 //////////////////////// +// clusters[1][1]->signal_vci_ini_d_proc[0].print_trace("proc_1_1_0_ini_d"); +// clusters[1][1]->signal_vci_ini_c_proc[0].print_trace("proc_1_1_0_ini_c"); +// clusters[1][1]->signal_vci_tgt_c_proc[0].print_trace("proc_1_1_0_tgt_c"); +// clusters[1][1]->signal_vci_xram.print_trace("memc_1_1_xram"); + } + + sc_start(sc_core::sc_time(1, SC_NS)); + } + return EXIT_SUCCESS; +} + +int sc_main (int argc, char *argv[]) +{ + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} Index: /trunk/platforms/tsarv4_generic_mmu/top.desc =================================================================== --- /trunk/platforms/tsarv4_generic_mmu/top.desc (revision 189) +++ /trunk/platforms/tsarv4_generic_mmu/top.desc (revision 189) @@ -0,0 +1,24 @@ + +# -*- python -*- + +todo = Platform('caba', 'top.cpp', + uses = [ + Uses('caba:tsarv4_cluster_mmu', + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el', + cmd_width = 40, + rsp_width = 33), + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + cell_size = 4, + plen_size = 8, + addr_size = 32, + rerror_size = 2, + clen_size = 1, + rflag_size = 1, + srcid_size = 14, + pktid_size = 4, + trdid_size = 4, + wrplen_size = 1, +) Index: /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd =================================================================== --- /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd (revision 189) +++ /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd (revision 189) @@ -0,0 +1,77 @@ + +# -*- python -*- + +Module('caba:tsarv4_cluster_mmu', + classname = 'soclib::caba::TsarV4ClusterMmu', + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + parameter.Module('iss_t'), + parameter.Int('cmd_width'), + parameter.Int('rsp_width'), + ], + header_files = [ '../source/include/tsarv4_cluster_mmu.h', ], + implementation_files = [ '../source/src/tsarv4_cluster_mmu.cpp', ], + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + Uses('caba:vci_cc_vcache_wrapper_v4', + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + Uses('caba:vci_mem_cache_v4'), + Uses('caba:vci_simple_ram'), + Uses('caba:vci_xicu'), + Uses('caba:vci_local_crossbar'), + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('cmd_width')), + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('rsp_width')), + Uses('caba:vci_vdspin_target_wrapper', + dspin_cmd_width = parameter.Reference('cmd_width'), + dspin_rsp_width = parameter.Reference('rsp_width')), + Uses('caba:vci_vdspin_initiator_wrapper', + dspin_cmd_width = parameter.Reference('cmd_width'), + dspin_rsp_width = parameter.Reference('rsp_width')), + Uses('caba:vci_multi_tty'), + Uses('caba:vci_framebuffer'), + Uses('caba:vci_block_device_tsar_v4'), + Uses('caba:vci_multi_dma'), + Uses('common:elf_file_loader'), + ], + instance_parameters = [ + parameter.Int('n_x'), + parameter.Int('n_y'), + parameter.Int('n_cluster'), + parameter.Module('mtd', 'common:mapping_table'), + parameter.Module('mtc', 'common:mapping_table'), + parameter.Module('mtx', 'common:mapping_table'), + parameter.Int('x_width'), + parameter.Int('y_width'), + parameter.Int('memc_tgtid'), + parameter.Int('xicu_tgtid'), + parameter.Int('fbuf_tgtid'), + parameter.Int('mtty_tgtid'), + parameter.Int('brom_tgtid'), + parameter.Int('bdev_tgtid'), + parameter.Int('cdma_tgtid'), + parameter.Int('memc_ways'), + parameter.Int('memc_sets'), + parameter.Int('l1_i_ways'), + parameter.Int('l1_i_sets'), + parameter.Int('l1_d_ways'), + parameter.Int('l1_d_sets'), + parameter.Int('xram_latency'), + parameter.Bool('io'), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), + Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), + Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), + ], +) + + Index: /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h =================================================================== --- /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h (revision 189) +++ /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h (revision 189) @@ -0,0 +1,177 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsarv4_cluster_mmu.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2011 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// This file define a TSAR cluster architecture with virtual memory: +// - It uses the virtual_dspin_router as distributed global interconnect +// - It uses the vci_local_crossbar as local interconnect +// - It uses the vci_cc_vcache_wrapper_v4 +// - It uses the vci_mem_cache_v4 +// - It contains a private RAM with a variable latency to emulate the L3 cache +// - It can contains 1, 2 or 4 processors +// - Each processor has a private dma channel (vci_multi_dma) +// - It uses the vci_xicu interrupt controller +// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster +// containing address 0xBFC00000. +// - The Multi-TTY component controls 4 terminals. +// - The nprocs dma irqs are connected to IRQ_IN[0]...IRQ_IN[3] +// - The four tty irqs are connected to IRQ_IN[4]...IRQ_IN[7] +// - The bdev irq is connected to IRQ_IN[8] +////////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H +#define SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_xicu.h" +#include "vci_local_crossbar.h" +#include "virtual_dspin_router.h" +#include "vci_vdspin_target_wrapper.h" +#include "vci_vdspin_initiator_wrapper.h" +#include "vci_multi_tty.h" +#include "vci_block_device_tsar_v4.h" +#include "vci_framebuffer.h" +#include "vci_multi_dma.h" +#include "vci_mem_cache_v4.h" +#include "vci_cc_vcache_wrapper_v4.h" + +namespace soclib { +namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template +class TsarV4ClusterMmu +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + + public: + + // Ports + sc_in p_clk; + sc_in p_resetn; + soclib::caba::DspinOutput **p_cmd_out; + soclib::caba::DspinInput **p_cmd_in; + soclib::caba::DspinOutput **p_rsp_out; + soclib::caba::DspinInput **p_rsp_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_it[4]; + sc_signal signal_irq_mdma[4]; + sc_signal signal_irq_tty0; + sc_signal signal_irq_tty1; + sc_signal signal_irq_tty2; + sc_signal signal_irq_tty3; + sc_signal signal_irq_bdev; + + // DSPIN signals between DSPIN routers and VCI/DSPIN wrappers + DspinSignals signal_dspin_cmd_l2g_d; + DspinSignals signal_dspin_cmd_g2l_d; + DspinSignals signal_dspin_cmd_l2g_c; + DspinSignals signal_dspin_cmd_g2l_c; + DspinSignals signal_dspin_rsp_l2g_d; + DspinSignals signal_dspin_rsp_g2l_d; + DspinSignals signal_dspin_rsp_l2g_c; + DspinSignals signal_dspin_rsp_g2l_c; + + // VCI signals between VCI/DSPIN wrappers and local crossbars + VciSignals signal_vci_l2g_d; + VciSignals signal_vci_g2l_d; + VciSignals signal_vci_l2g_c; + VciSignals signal_vci_g2l_c; + + // Direct VCI signals + VciSignals signal_vci_ini_d_proc[4]; + VciSignals signal_vci_ini_d_bdev; + VciSignals signal_vci_ini_d_mdma; + + VciSignals signal_vci_tgt_d_memc; + VciSignals signal_vci_tgt_d_mtty; + VciSignals signal_vci_tgt_d_xicu; + VciSignals signal_vci_tgt_d_bdev; + VciSignals signal_vci_tgt_d_mdma; + VciSignals signal_vci_tgt_d_brom; + VciSignals signal_vci_tgt_d_fbuf; + + // Coherence VCi signals + VciSignals signal_vci_ini_c_proc[4]; + VciSignals signal_vci_tgt_c_proc[4]; + VciSignals signal_vci_ini_c_memc; + VciSignals signal_vci_tgt_c_memc; + + // external RAM VCI signal + VciSignals signal_vci_xram; + + // Components + + VciCcVCacheWrapperV4* proc[4]; + VciMemCacheV4* memc; + VciXicu* xicu; + VciLocalCrossbar* xbard; + VciLocalCrossbar* xbarc; + VciVdspinTargetWrapper* tgtwrapperd; + VciVdspinInitiatorWrapper* iniwrapperd; + VciVdspinTargetWrapper* tgtwrapperc; + VciVdspinInitiatorWrapper* iniwrapperc; + VirtualDspinRouter* cmdrouter; + VirtualDspinRouter* rsprouter; + VciSimpleRam* brom; + VciMultiTty* mtty; + VciFrameBuffer* fbuf; + VciBlockDeviceTsarV4* bdev; + VciMultiDma* mdma; + VciSimpleRam* xram; + + TsarV4ClusterMmu(sc_module_name insname, + size_t nprocs, // number of processors + size_t n_x, // x coordinate + size_t n_y, // y coordinate + size_t n_cluster, // y + ymax*x + const soclib::common::MappingTable &mtd, // direct mapping table + const soclib::common::MappingTable &mtc, // coherence mapping table + const soclib::common::MappingTable &mtx, // xram mapping table + size_t x_width, // x field number of bits + size_t y_width, // y field number of bits + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_bdev, + size_t tgtid_mdma, + size_t memc_ways, // number of ways for MEMC + size_t memc_sets, // number of sets for MEMC + size_t l1_i_ways, // number of ways for L1 ICACHE + size_t l1_i_sets, // number of sets for L1 ICACHE + size_t l1_d_ways, // number of ways for L1 DCACHE + size_t l1_d_sets, // number of sets for L1 DCACHE + size_t xram_latency, // external ram latency + bool io, // I/O cluster if true + size_t xfb, // frame buffer pixels + size_t yfb, // frame buffer lines + char* disk_name, // virtual disk name for BDEV + size_t block_size, // block size for BDEV + Loader loader, // loader for BROM + uint32_t frozen_cycles, // max frozen cycles + uint32_t start_debug_cycle, + bool debug_ok); + + ~TsarV4ClusterMmu(); +}; +}} + +#endif Index: /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp =================================================================== --- /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (revision 189) +++ /trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (revision 189) @@ -0,0 +1,492 @@ +#include "../include/tsarv4_cluster_mmu.h" + +namespace soclib { +namespace caba { + +////////////////////////////////////////////////////////////////////////// +// Constructor +////////////////////////////////////////////////////////////////////////// +template +TsarV4ClusterMmu::TsarV4ClusterMmu( + sc_module_name insname, + size_t nprocs, + size_t x_id, + size_t y_id, + size_t cluster_id, + const soclib::common::MappingTable &mtd, + const soclib::common::MappingTable &mtc, + const soclib::common::MappingTable &mtx, + size_t x_width, + size_t y_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_bdev, + size_t tgtid_mdma, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + bool io, + size_t xfb, + size_t yfb, + char* disk_name, + size_t block_size, + Loader loader, + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool debug_ok) + : soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn"), + + signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), + signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), + signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), + signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), + signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), + signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), + signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), + signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), + + signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), + signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), + + signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), + signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), + signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), + signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), + signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), + signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), + signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), + + signal_vci_ini_c_memc("signal_vci_ini_c_memc"), + signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), + + signal_vci_xram("signal_vci_xram") + +{ + // Vectors of ports definition + + p_cmd_in = alloc_elems >("p_cmd_in", 2, 4); + p_cmd_out = alloc_elems >("p_cmd_out", 2, 4); + p_rsp_in = alloc_elems >("p_rsp_in", 2, 4); + p_rsp_out = alloc_elems >("p_rsp_out", 2, 4); + + // Components definition + + // on direct network : local srcid[proc] in [0...nprocs-1] + // on direct network : local srcid[mdma] = nprocs + // on direct network : local srcid[bdev] = nprocs + 1 + + // on coherence network : local srcid[proc] in [0...nprocs-1] + // on coherence network : local srcid[memc] = nprocs + +std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; + + for ( size_t p=0 ; p( + sproc.str().c_str(), + cluster_id*nprocs + p, + mtd, // Mapping Table Direct + mtc, // Mapping Table Coherence + IntTab(cluster_id,p), // SRCID_D + IntTab(cluster_id,p), // SRCID_C + IntTab(cluster_id,p), // TGTID_C + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways,l1_i_sets,16, // ICACHE size + l1_d_ways,l1_d_sets,16, // DCACHE size + 4, // WBUF width + 4, // WBUF depth + frozen_cycles, // max frozen cycles + debug_start_cycle, + debug_ok); + } + +std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; + + std::ostringstream smemc; + smemc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCacheV4( + smemc.str().c_str(), + mtd, mtc, mtx, + IntTab(cluster_id), // SRCID_X + IntTab(cluster_id, nprocs), // SRCID_C + IntTab(cluster_id, tgtid_memc), // TGTID_D + IntTab(cluster_id, nprocs), // TGTID_C + memc_ways, memc_sets, 16, // CACHE SIZE + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + debug_start_cycle, + debug_ok); + + +std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sxram; + sxram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + sxram.str().c_str(), + IntTab(cluster_id), + mtx, + loader, + xram_latency); + +std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; + + size_t nhwi = 4; // always 4 (or 9) ports, even if + if( io == true ) nhwi = 9; // there if less than 4 processors + std::ostringstream sicu; + sicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + sicu.str().c_str(), + mtd, // mapping table + IntTab(cluster_id, tgtid_xicu), // TGTID_D + 0, // number of timer IRQs + nhwi, // number of hard IRQs + 0, // number of soft IRQs + nprocs); // number of output IRQs + +std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; + + // dma multi-canaux + std::ostringstream sdma; + sdma << "dma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( + sdma.str().c_str(), + mtd, + IntTab(cluster_id, nprocs), // SRCID + IntTab(cluster_id, tgtid_mdma), // TGTID + 64, // burst size + nprocs); // number of IRQs + +std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; + + // direct local crossbar + size_t nb_direct_initiators = nprocs + 1; + size_t nb_direct_targets = 3; + if( io == true ) + { + nb_direct_initiators = nprocs + 2; + nb_direct_targets = 7; + } + std::ostringstream sd; + sd << "xbard_" << x_id << "_" << y_id; + xbard = new VciLocalCrossbar( + sd.str().c_str(), + mtd, + IntTab(cluster_id), // cluster initiator index + IntTab(cluster_id), // cluster target index + nb_direct_initiators, // number of initiators + nb_direct_targets); // number of targets + +std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; + + // coherence local crossbar + std::ostringstream sc; + sc << "xbarc_" << x_id << "_" << y_id; + xbarc = new VciLocalCrossbar( + sc.str().c_str(), + mtc, + IntTab(cluster_id), // cluster initiator index + IntTab(cluster_id), // cluster target index + nprocs + 1, // number of initiators + nprocs + 1); // number of targets + +std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; + + // direct initiator wrapper + std::ostringstream wid; + wid << "iniwrapperd_" << x_id << "_" << y_id; + iniwrapperd = new VciVdspinInitiatorWrapper( + wid.str().c_str(), + 4, // cmd fifo depth + 4); // rsp fifo depth + + // direct target wrapper + std::ostringstream wtd; + wtd << "tgtwrapperd_" << x_id << "_" << y_id; + tgtwrapperd = new VciVdspinTargetWrapper( + wtd.str().c_str(), + 4, // cmd fifo depth + 4); // rsp fifo depth + + // coherence initiator wrapper + std::ostringstream wic; + wic << "iniwrapperc_" << x_id << "_" << y_id; + iniwrapperc = new VciVdspinInitiatorWrapper( + wic.str().c_str(), + 4, // cmd fifo depth + 4); // rsp fifo depth + + // coherence target wrapper + std::ostringstream wtc; + wtc << "tgtwrapperc_" << x_id << "_" << y_id; + tgtwrapperc = new VciVdspinTargetWrapper( + wtc.str().c_str(), + 4, // cmd fifo depth + 4); // rsp fifo depth + +std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; + + // CMD router + std::ostringstream scmd; + scmd << "cmdrouter_" << x_id << "_" << y_id; + cmdrouter = new VirtualDspinRouter( + scmd.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + +std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; + + // RSP router + std::ostringstream srsp; + srsp << "rsprouter_" << x_id << "_" << y_id; + rsprouter = new VirtualDspinRouter( + srsp.str().c_str(), + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + // IO cluster components + if ( io == true ) + { + brom = new VciSimpleRam( + "brom", + IntTab(cluster_id, tgtid_brom), + mtd, + loader); + + fbuf = new VciFrameBuffer( + "fbuf", + IntTab(cluster_id, tgtid_fbuf), + mtd, + xfb, yfb); + + bdev = new VciBlockDeviceTsarV4( + "bdev", + mtd, + IntTab(cluster_id, nprocs+1), + IntTab(cluster_id, tgtid_bdev), + disk_name, + block_size); + + mtty = new VciMultiTty( + "mtty", + IntTab(cluster_id, tgtid_mtty), + mtd, + "tty0", "tty1", "tty2", "tty3", NULL); + } + +std::cout << " - all components constructed" << std::endl; + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + // CMDROUTER and RSPROUTER + cmdrouter->p_clk (this->p_clk); + cmdrouter->p_resetn (this->p_resetn); + rsprouter->p_clk (this->p_clk); + rsprouter->p_resetn (this->p_resetn); + for(int x = 0; x < 2; x++) + { + for(int y = 0; y < 4; y++) + { + cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); + cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); + rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); + rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); + } + } + + cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); + cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); + cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); + cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); + + rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); + rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); + rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); + rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); + + // VCI/DSPIN WRAPPERS + iniwrapperd->p_clk (this->p_clk); + iniwrapperd->p_resetn (this->p_resetn); + iniwrapperd->p_vci (signal_vci_l2g_d); + iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); + iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); + + tgtwrapperd->p_clk (this->p_clk); + tgtwrapperd->p_resetn (this->p_resetn); + tgtwrapperd->p_vci (signal_vci_g2l_d); + tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); + tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); + + iniwrapperc->p_clk (this->p_clk); + iniwrapperc->p_resetn (this->p_resetn); + iniwrapperc->p_vci (signal_vci_l2g_c); + iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); + iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); + + tgtwrapperc->p_clk (this->p_clk); + tgtwrapperc->p_resetn (this->p_resetn); + tgtwrapperc->p_vci (signal_vci_g2l_c); + tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); + tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); + + // CROSSBAR direct + xbard->p_clk (this->p_clk); + xbard->p_resetn (this->p_resetn); + xbard->p_initiator_to_up (signal_vci_l2g_d); + xbard->p_target_to_up (signal_vci_g2l_d); + + xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); + xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); + xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); + + xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); + + for ( size_t p=0 ; pp_to_initiator[p] (signal_vci_ini_d_proc[p]); + } + + if ( io == true ) + { + xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); + xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); + xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); + xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); + + xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); + } + + // CROSSBAR coherence + xbarc->p_clk (this->p_clk); + xbarc->p_resetn (this->p_resetn); + xbarc->p_initiator_to_up (signal_vci_l2g_c); + xbarc->p_target_to_up (signal_vci_g2l_c); + xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); + xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); + for ( size_t p=0 ; pp_to_target[p] (signal_vci_tgt_c_proc[p]); + xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); + } + + // Processors + for ( size_t p=0 ; pp_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); + proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); + proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); + proc[p]->p_irq[0] (signal_proc_it[p]); + for ( size_t j = 1 ; j < 6 ; j++ ) + { + proc[p]->p_irq[j] (signal_false); + } + } + + // XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_vci_tgt_d_xicu); + for ( size_t p=0 ; pp_irq[p] (signal_proc_it[p]); + } + for ( size_t p=0 ; pp_hwi[p] (signal_irq_mdma[p]); + } + for ( size_t x=nprocs ; x<4 ; x++) + { + xicu->p_hwi[x] (signal_false); + } + if ( io == true ) + { + xicu->p_hwi[4] (signal_irq_tty0); + xicu->p_hwi[5] (signal_irq_tty1); + xicu->p_hwi[6] (signal_irq_tty2); + xicu->p_hwi[7] (signal_irq_tty3); + xicu->p_hwi[8] (signal_irq_bdev); + } + + // MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_vci_ixr (signal_vci_xram); + memc->p_vci_tgt (signal_vci_tgt_d_memc); + memc->p_vci_ini (signal_vci_ini_c_memc); + memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); + + // XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_vci_xram); + + // CDMA + mdma->p_clk (this->p_clk); + mdma->p_resetn (this->p_resetn); + mdma->p_vci_target (signal_vci_tgt_d_mdma); + mdma->p_vci_initiator (signal_vci_ini_d_mdma); + for (size_t p=0 ; pp_irq[p] (signal_irq_mdma[p]); + } + + // Components in IO cluster + + if ( io == true ) + { + // BDEV + bdev->p_clk (this->p_clk); + bdev->p_resetn (this->p_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_d_bdev); + bdev->p_vci_initiator (signal_vci_ini_d_bdev); + + // FBUF + fbuf->p_clk (this->p_clk); + fbuf->p_resetn (this->p_resetn); + fbuf->p_vci (signal_vci_tgt_d_fbuf); + + // BROM + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_vci_tgt_d_brom); + + // MTTY + mtty->p_clk (this->p_clk); + mtty->p_resetn (this->p_resetn); + mtty->p_vci (signal_vci_tgt_d_mtty); + mtty->p_irq[0] (signal_irq_tty0); + mtty->p_irq[1] (signal_irq_tty1); + mtty->p_irq[2] (signal_irq_tty2); + mtty->p_irq[3] (signal_irq_tty3); + } +} // end constructor + +/////////////////////////////////////////////////////////////////////////// +// destructor +/////////////////////////////////////////////////////////////////////////// +template +TsarV4ClusterMmu::~TsarV4ClusterMmu() {} + +}}