Index: /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp =================================================================== --- /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (revision 197) +++ /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (revision 198) @@ -34,9 +34,4 @@ #define DEBUG_INVAL_ITLB 1 #define DEBUG_INVAL_DTLB 1 - -#define _CMD_INIT_VAL 0x00 -#define _CMD_ITLB 0x01 -#define _CMD_DTLB 0x02 -#define _CMD_USR 0x04 namespace soclib { @@ -398,21 +393,11 @@ "icache_words and dcache_words parameters must be equal"); - { - uint32_t val; - - val = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | - (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | - (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | - (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | - (uint32_log2(m_icache_words<<2)); - - //r_mmu_params = val; - m_mmu_params = val; - - val = (1 << 16) | 0x1; - //r_mmu_release = val; - m_mmu_release = val; - } - + r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | + (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | + (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | + (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | + (uint32_log2(m_icache_words<<2)); + + r_mmu_release = (uint32_t)(1 << 16) | 0x1; r_tgt_buf = new uint32_t[dcache_words]; @@ -420,39 +405,4 @@ r_dcache_in_itlb = new bool[dcache_ways*dcache_sets]; r_dcache_in_dtlb = new bool[dcache_ways*dcache_sets]; - - - m_proc_id = proc_id; - - m_tm_start = 0; - m_tm_end = 0; - m_period = 0; - - char *ptr; - - ptr = getenv("TSAR_L1_TM_START"); - - if(ptr != NULL) - m_tm_start = (size_t) atol(ptr); - - ptr = getenv("TSAR_L1_TM_END"); - - if(ptr != NULL) - m_tm_end = (size_t) atol(ptr); - - ptr = getenv("TSAR_L1_PERIOD"); - - if(ptr != NULL) - m_period = (size_t) atol(ptr); - - if(m_period != 0) - m_log.open(name, std::ios::out); - - if(m_proc_id == 0) - { - std::cout << "TSAR_L1_TM_START =" << m_tm_start << std::endl - << "TSAR_L1_TM_END =" << m_tm_end << std::endl - << "TSAR_L1_PERIOD =" << m_period << std::endl; - } - SC_METHOD(transition); @@ -585,53 +535,52 @@ + +/* //////////////////////// tmpl(void)::print_stats() //////////////////////// { - std::ostream &output = (m_period == 0) ? std::cout : m_log; - float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); - output << name() << std::endl - << "CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl - << "READ_RATE = " << (float)m_cpt_data_read/run_cycles << std::endl - << "WRITE_RATE = " << (float)m_cpt_data_write/run_cycles << std::endl - << "IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl - << "DMISS_RATE = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl - << "INS_MISS_COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl - << "DATA_MISS_COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl - << "WRITE_COST = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl - << "UNC_COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl - << "UNCACHED_READ_RATE = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl - << "CACHED_WRITE_RATE = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl - << "INS_TLB_MISS_RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl - << "DATA_TLB_MISS_RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl - << "ITLB_MISS_COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl - << "DTLB_MISS_COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl - << "ITLB_UPDATE_ACC_COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl - << "DTLB_UPDATE_ACC_COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl - << "DTLB_UPDATE_DIRTY_COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl - << "ITLB_HIT_IN_DCACHE_RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl - << "DTLB_HIT_IN_DCACHE_RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl - << "DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl - << "DCACHE_FOR_TLB_% = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl - << "NB_CC_BROADCAST = " << m_cpt_cc_broadcast << std::endl - << "NB_CC_UPDATE_DATA = " << m_cpt_cc_update_dcache << std::endl - << "NB_CC_INVAL_DATA = " << m_cpt_cc_inval_dcache << std::endl - << "NB_CC_INVAL_INS = " << m_cpt_cc_inval_icache << std::endl - << "NB_CC_CLEANUP_DATA = " << m_cpt_cc_cleanup_data << std::endl - << "NB_CC_CLEANUP_INS = " << m_cpt_cc_cleanup_ins << std::endl - << "CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl - << "CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl - << "CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl - << "CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl - << "IMISS_TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl - << "DMISS_TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl - << "UNC_TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl - << "WRITE_TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl - << "WRITE_LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl - << "ITLB_MISS_TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl - << "DTLB_MISS_TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; + std::cout << name() << std::endl + << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl + << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl + << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl + << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl + << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl + << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl + << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl + << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl + << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl + << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl + << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl + << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl + << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl + << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl + << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl + << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl + << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl + << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl + << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl + << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl + << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl + << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl + << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl + << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl + << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl + << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl + << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl + << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl + << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl + << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl + << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl + << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl + << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl + << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl + << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl + << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl + << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl + << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl + << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; } - //////////////////////// @@ -652,6 +601,6 @@ m_cpt_total_cycles = 0; - m_cpt_data_read = 0; - m_cpt_data_write = 0; + m_cpt_read = 0; + m_cpt_write = 0; m_cpt_data_miss = 0; m_cpt_ins_miss = 0; @@ -681,12 +630,12 @@ m_cpt_ins_tlb_miss = 0; m_cpt_ins_tlb_update_acc = 0; - m_cpt_ins_tlb_occup_cache = 0; - m_cpt_ins_tlb_hit_dcache = 0; - + m_cpt_data_tlb_read = 0; m_cpt_data_tlb_miss = 0; m_cpt_data_tlb_update_acc = 0; m_cpt_data_tlb_update_dirty = 0; + m_cpt_ins_tlb_hit_dcache = 0; m_cpt_data_tlb_hit_dcache = 0; + m_cpt_ins_tlb_occup_cache = 0; m_cpt_data_tlb_occup_cache = 0; @@ -717,9 +666,8 @@ m_cost_dtlb_sc_dirty_transaction = 0; - m_cpt_cc_update_icache = 0; - m_cpt_cc_update_dcache = 0; - m_cpt_cc_inval_icache = 0; - m_cpt_cc_inval_dcache = 0; - m_cpt_cc_broadcast = 0; + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; + m_cpt_cc_broadcast = 0; m_cost_updt_data_frz = 0; @@ -730,15 +678,7 @@ m_cpt_cc_cleanup_data = 0; m_cpt_cc_cleanup_ins = 0; - - m_cpt_icleanup_transaction = 0; - m_cpt_dcleanup_transaction = 0; - m_cost_icleanup_transaction = 0; - m_cost_dcleanup_transaction = 0; - - m_cpt_ins_tlb_inval = 0; - m_cost_data_tlb_inval_frz = 0; - m_cost_ins_tlb_inval_frz = 0; } +*/ ///////////////////////// @@ -776,5 +716,5 @@ r_mmu_mode = 0x3; - // No request from ICACHE FSM to CMD FSM + // No request from ICACHE FSM to CMD FSM r_icache_miss_req = false; r_icache_unc_req = false; @@ -799,5 +739,5 @@ // No LL reservation - r_dcache_ll_valid = false; + r_dcache_ll_valid = false; // No request from DCACHE FSM to INVAL TLB FSMs @@ -831,7 +771,102 @@ m_debug_inval_dtlb_fsm = false; - clear_stats(); - - /* +/* + // activity counters + m_cpt_dcache_data_read = 0; + m_cpt_dcache_data_write = 0; + m_cpt_dcache_dir_read = 0; + m_cpt_dcache_dir_write = 0; + m_cpt_icache_data_read = 0; + m_cpt_icache_data_write = 0; + m_cpt_icache_dir_read = 0; + m_cpt_icache_dir_write = 0; + + m_cpt_frz_cycles = 0; + m_cpt_dcache_frz_cycles = 0; + m_cpt_total_cycles = 0; + + m_cpt_read = 0; + m_cpt_write = 0; + m_cpt_data_miss = 0; + m_cpt_ins_miss = 0; + m_cpt_unc_read = 0; + m_cpt_write_cached = 0; + m_cpt_ins_read = 0; + + m_cost_write_frz = 0; + m_cost_data_miss_frz = 0; + m_cost_unc_read_frz = 0; + m_cost_ins_miss_frz = 0; + + m_cpt_imiss_transaction = 0; + m_cpt_dmiss_transaction = 0; + m_cpt_unc_transaction = 0; + m_cpt_write_transaction = 0; + m_cpt_icache_unc_transaction = 0; + + m_cost_imiss_transaction = 0; + m_cost_dmiss_transaction = 0; + m_cost_unc_transaction = 0; + m_cost_write_transaction = 0; + m_cost_icache_unc_transaction = 0; + m_length_write_transaction = 0; + + m_cpt_ins_tlb_read = 0; + m_cpt_ins_tlb_miss = 0; + m_cpt_ins_tlb_update_acc = 0; + + m_cpt_data_tlb_read = 0; + m_cpt_data_tlb_miss = 0; + m_cpt_data_tlb_update_acc = 0; + m_cpt_data_tlb_update_dirty = 0; + m_cpt_ins_tlb_hit_dcache = 0; + m_cpt_data_tlb_hit_dcache = 0; + m_cpt_ins_tlb_occup_cache = 0; + m_cpt_data_tlb_occup_cache = 0; + + m_cost_ins_tlb_miss_frz = 0; + m_cost_data_tlb_miss_frz = 0; + m_cost_ins_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_dirty_frz = 0; + m_cost_ins_tlb_occup_cache_frz = 0; + m_cost_data_tlb_occup_cache_frz = 0; + + m_cpt_ins_tlb_inval = 0; + m_cpt_data_tlb_inval = 0; + m_cost_ins_tlb_inval_frz = 0; + m_cost_data_tlb_inval_frz = 0; + + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; + m_cpt_cc_broadcast = 0; + + m_cost_updt_data_frz = 0; + m_cost_inval_ins_frz = 0; + m_cost_inval_data_frz = 0; + m_cost_broadcast_frz = 0; + + m_cpt_cc_cleanup_data = 0; + m_cpt_cc_cleanup_ins = 0; + + m_cpt_itlbmiss_transaction = 0; + m_cpt_itlb_ll_transaction = 0; + m_cpt_itlb_sc_transaction = 0; + m_cpt_dtlbmiss_transaction = 0; + m_cpt_dtlb_ll_transaction = 0; + m_cpt_dtlb_sc_transaction = 0; + m_cpt_dtlb_ll_dirty_transaction = 0; + m_cpt_dtlb_sc_dirty_transaction = 0; + + m_cost_itlbmiss_transaction = 0; + m_cost_itlb_ll_transaction = 0; + m_cost_itlb_sc_transaction = 0; + m_cost_dtlbmiss_transaction = 0; + m_cost_dtlb_ll_transaction = 0; + m_cost_dtlb_sc_transaction = 0; + m_cost_dtlb_ll_dirty_transaction = 0; + m_cost_dtlb_sc_dirty_transaction = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; @@ -841,10 +876,6 @@ for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0; - */ - - //// For instrumentation only - r_ireq_isUser_save = false; - r_dreq_isUser_save = false; - r_tlb_access_type_save = _CMD_INIT_VAL; + +*/ return; } @@ -869,11 +900,4 @@ m_cpt_total_cycles++; - - - if((m_period != 0) && ((m_cpt_total_cycles % m_period) == 0)) - { - print_stats(); - clear_stats(); - } m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; @@ -1186,11 +1210,11 @@ // - Coherence operation => ICACHE_CC_CHEK // Five configurations corresponding to XTN processor requests sent by DCACHE FSM : - // - Flush TLB => ICACHE_XTN_TLB_FLUSH - // - Flush cache => ICACHE_XTN_CACHE_FLUSH + // - Flush TLB => ICACHE_XTN_TLB_FLUSH + // - Flush cache => ICACHE_XTN_CACHE_FLUSH // - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL // - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@ // - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA // three configurations corresponding to instruction processor requests : - // - tlb miss => ICACHE_TLB_WAIT + // - tlb miss => ICACHE_TLB_WAIT // - cacheable read miss => ICACHE_MISS_VICTIM // - uncacheable read miss => ICACHE_UNC_REQ @@ -1240,9 +1264,5 @@ // for itlb, and with a speculative physical address for icache, // computed during the previous cycle. - { - - // For instrumentation: flag reset - r_ireq_isUser_save = false; - + { // coherence request from the target FSM if ( r_tgt_icache_req.read() ) @@ -1302,7 +1322,4 @@ uint32_t cache_inst = 0; bool cache_hit = false; - - // For instrumentation: is User access ? - r_ireq_isUser_save = (ireq.mode == iss_t::MODE_USER) ? true : false; if ( r_mmu_mode.read() & INS_CACHE_MASK ) @@ -1422,5 +1439,4 @@ r_icache_fsm = ICACHE_MISS_VICTIM; r_icache_miss_req = true; - r_tlb_access_type_save = _CMD_INIT_VAL; } } @@ -1685,6 +1701,6 @@ } - if ( r_vci_rsp_ins_error.read() ) // bus error - { + if ( r_vci_rsp_ins_error.read() ) // bus error + { r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; r_mmu_ibvar = r_icache_vaddr_save.read(); @@ -1698,5 +1714,5 @@ r_icache_miss_word = 0; r_icache_fsm = ICACHE_MISS_UPDT; - } + } break; } @@ -2026,11 +2042,11 @@ case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state : // 1) Long write request (DCACHE FSM) => DCACHE_WRITE_*** - // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK + // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS - // 4) XTN request (processor) => DCACHE_XTN_* - // 5) DTLB miss (processor) => DCACHE_TLB_MISS + // 4) XTN request (processor) => DCACHE_XTN_* + // 5) DTLB miss (processor) => DCACHE_TLB_MISS // 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM - // 7) Uncacheable read (processor) => DCACHE_UNC_REQ - // 8) SC access (processor) => DCACHE_SC + // 7) Uncacheable read (processor) => DCACHE_UNC_REQ + // 8) SC access (processor) => DCACHE_SC // There is 4 configurations to access the cache, // depending on the pipe-line state, defined @@ -2061,7 +2077,4 @@ bool long_write_set_dirty = false; bool tlb_inval_frozen = false; - - // For instrumentation: flag reset - r_dreq_isUser_save = false; if ( r_dcache_p1_valid.read() ) // P2 stage activated @@ -2128,17 +2141,17 @@ #if DEBUG_DCACHE - if ( m_debug_dcache_fsm ) - { - if ( cache_updt ) - std::cout << " P2 stage: cache update" << std::dec - << " / way = " << cache_way - << " / set = " << cache_set - << " / word = " << cache_word << std::hex - << " / wdata = " << wdata - << " / be = " << be << std::endl; - if ( long_write_set_dirty ) - std::cout << " P2 stage: dirty bit update required" - << " / pte_paddr = " << std::hex << pte_paddr << std::endl; - } +if ( m_debug_dcache_fsm ) +{ + if ( cache_updt ) + std::cout << " P2 stage: cache update" << std::dec + << " / way = " << cache_way + << " / set = " << cache_set + << " / word = " << cache_word << std::hex + << " / wdata = " << wdata + << " / be = " << be << std::endl; + if ( long_write_set_dirty ) + std::cout << " P2 stage: dirty bit update required" + << " / pte_paddr = " << std::hex << pte_paddr << std::endl; +} #endif } // end P2 stage @@ -2395,12 +2408,10 @@ case iss_t::XTN_MMU_PARAMS: - //drsp.rdata = r_mmu_params.read(); - drsp.rdata = m_mmu_params; + drsp.rdata = r_mmu_params.read(); drsp.valid = true; break; case iss_t::XTN_MMU_RELEASE: - //drsp.rdata = r_mmu_release.read(); - drsp.rdata = m_mmu_release; + drsp.rdata = r_mmu_release.read(); drsp.valid = true; break; @@ -2552,8 +2563,4 @@ else { - - // For instrumentation: is User access ? - r_dreq_isUser_save = (dreq.mode == iss_t::MODE_USER) ? true : false; - bool valid_req = false; bool cacheable = false; @@ -2652,9 +2659,8 @@ if ( not r_dcache_cleanup_req.read() ) { - r_dcache_vci_paddr = paddr; - r_dcache_vci_miss_req = true; - r_dcache_miss_type = PROC_MISS; - r_dcache_fsm = DCACHE_MISS_VICTIM; - r_tlb_access_type_save = _CMD_INIT_VAL; + r_dcache_vci_paddr = paddr; + r_dcache_vci_miss_req = true; + r_dcache_miss_type = PROC_MISS; + r_dcache_fsm = DCACHE_MISS_VICTIM; } } @@ -2832,5 +2838,5 @@ if ( m_debug_dcache_fsm ) { - std::cout << " HIT in dcache, but unmapped:" << std::hex + std::cout << " HIT in dcache, but unmapped:" << std::dec << " way = " << way << std::dec << " / set = " << set @@ -2863,5 +2869,5 @@ if ( m_debug_dcache_fsm ) { - std::cout << " HIT in dcache " << std::hex + std::cout << " HIT in dcache " << std::dec << " way = " << way << std::dec << " / set = " << set @@ -2886,5 +2892,5 @@ if ( m_debug_dcache_fsm ) { - std::cout << " HIT in dcache:" << std::hex + std::cout << " HIT in dcache:" << std::dec << " way = " << way << std::dec << " / set = " << set @@ -2901,5 +2907,4 @@ r_dcache_fsm = DCACHE_MISS_VICTIM; r_dcache_vci_miss_req = true; - r_tlb_access_type_save = (r_dcache_tlb_ins.read()) ? _CMD_ITLB : _CMD_DTLB; #if DEBUG_DCACHE @@ -3116,5 +3121,4 @@ r_dcache_fsm = DCACHE_MISS_VICTIM; r_dcache_vci_miss_req = true; - r_tlb_access_type_save = (r_dcache_tlb_ins.read()) ? _CMD_ITLB : _CMD_DTLB; #if DEBUG_DCACHE @@ -3267,16 +3271,5 @@ // we don't analyse the response, because // we don't care if the L/R bit update is not done - // we must take the coherence requests because - // there is a risk of dead-lock - - { - // external coherence request - if ( r_tgt_dcache_req ) - { - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_fsm_save = r_dcache_fsm; - break; - } - + { if ( not r_dcache_vci_sc_req.read() ) // response available { @@ -3326,5 +3319,4 @@ r_dcache_fsm = DCACHE_IDLE; } - break; } @@ -3376,6 +3368,6 @@ bool cleanup_req = r_dcache.inval( way, - set, - &nline ); + set, + &nline ); if ( cleanup_req ) { @@ -3570,5 +3562,5 @@ if ( m_debug_dcache_fsm ) { - std::cout << " Select a slot:" << std::hex + std::cout << " Select a slot:" << " / way = " << way << " / set = " << set @@ -3581,21 +3573,13 @@ /////////////////////// case DCACHE_MISS_INVAL: // invalidate the victim line - // and possibly request itlb or dtlb invalidate + // and possibly request itlb or dtlb invalidate { paddr_t nline; size_t way = r_dcache_miss_way.read(); size_t set = r_dcache_miss_set.read(); - bool isValid; - - isValid = r_dcache.inval( way, - set, - &nline ); - - - std::cout << "DMISS_INVAL: way " << way - << " / set " << set - << " / nline " << std::hex << nline - << " / isValid " << isValid - << std::endl; + + r_dcache.inval( way, + set, + &nline ); // if itlb & dtlb invalidate are required @@ -3604,17 +3588,16 @@ ( r_dcache_in_itlb[way*m_dcache_sets+set] or r_dcache_in_dtlb[m_dcache_sets*way+set] ) ) - { - r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2); - r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set]; - r_dcache_in_itlb[way*m_dcache_sets+set] = false; - r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set]; - r_dcache_in_dtlb[way*m_dcache_sets+set] = false; + { + r_dcache_tlb_inval_line = r_dcache_vci_paddr.read() >> (uint32_log2(m_dcache_words)+2); + r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set]; + r_dcache_in_itlb[way*m_dcache_sets+set] = false; + r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set]; + r_dcache_in_dtlb[way*m_dcache_sets+set] = false; r_dcache_fsm = DCACHE_MISS_INVAL_WAIT; - } + } else { r_dcache_fsm = DCACHE_MISS_WAIT; } - break; } @@ -3698,5 +3681,5 @@ { r_dcache_miss_word = 0; - r_dcache_fsm = DCACHE_MISS_UPDT; + r_dcache_fsm = DCACHE_MISS_UPDT; } break; @@ -3784,5 +3767,5 @@ else { - std::cout << " Write one word:" << std::hex + std::cout << " Write one word:" << " address = " << r_dcache_vci_paddr.read() << " / data = " << r_vci_rsp_fifo_dcache.read() @@ -3851,10 +3834,10 @@ m_cpt_dcache_data_read++; m_cpt_dcache_dir_read++; -#endif +#endif; #if DEBUG_DCACHE if ( m_debug_dcache_fsm ) { - std::cout << " Set PTE dirty bit in dtlb:" << std::hex + std::cout << " Set PTE dirty bit in dtlb:" << " paddr = " << r_dcache_p2_pte_paddr.read() << " / tlb_way = " << r_dcache_p2_tlb_way.read() @@ -3889,5 +3872,5 @@ if ( m_debug_dcache_fsm ) { - std::cout << " Set PTE dirty bit in dcache:" << std::hex + std::cout << " Set PTE dirty bit in dcache:" << " / way = " << r_dcache_p2_pte_way.read() << " / set = " << r_dcache_p2_pte_set.read() @@ -4156,5 +4139,5 @@ std::cout << " Update one word :" << std::dec << " way = " << way - << " / set = " << set + << " / set = " << set << " / word = " << word << " / value = " << std::hex << r_tgt_buf[word] << std::endl; @@ -4262,8 +4245,4 @@ { m_cpt_frz_cycles++; // used for instrumentation - - if(dreq.valid and not drsp.valid) - m_cpt_dcache_frz_cycles++; - m_cpt_stop_simulation++; // used for debug if ( m_cpt_stop_simulation > m_max_frozen_cycles ) @@ -4363,5 +4342,5 @@ r_icache_miss_req = false; r_vci_cmd_imiss_prio = false; -// m_cpt_imiss_transaction++; +// m_cpt_imiss_transaction++; } // 4 - Instruction Uncachable @@ -4370,5 +4349,5 @@ r_vci_cmd_fsm = CMD_INS_UNC; r_icache_unc_req = false; -// m_cpt_iunc_transaction++; +// m_cpt_iunc_transaction++; } // 5 - Data Write @@ -4379,6 +4358,6 @@ r_vci_cmd_min = wbuf_min; r_vci_cmd_max = wbuf_max; -// m_cpt_write_transaction++; -// m_length_write_transaction += (wbuf_max-wbuf_min+1); +// m_cpt_write_transaction++; +// m_length_write_transaction += (wbuf_max-wbuf_min+1); } // 6 - Data Store Conditionnal @@ -4827,5 +4806,4 @@ p_vci_ini_d.cmd = vci_param::CMD_READ; p_vci_ini_d.eop = true; - p_vci_ini_d.pktid = (r_ireq_isUser_save == true) ? _CMD_USR : 0; break; @@ -4839,5 +4817,4 @@ p_vci_ini_d.cmd = vci_param::CMD_READ; p_vci_ini_d.eop = true; - p_vci_ini_d.pktid = (r_ireq_isUser_save == true) ? _CMD_USR : 0; break; @@ -4851,5 +4828,4 @@ p_vci_ini_d.cmd = vci_param::CMD_READ; p_vci_ini_d.eop = true; - p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR | r_tlb_access_type_save.read() : 0; break; @@ -4863,5 +4839,4 @@ p_vci_ini_d.cmd = vci_param::CMD_READ; p_vci_ini_d.eop = true; - p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0; break; @@ -4875,5 +4850,4 @@ p_vci_ini_d.cmd = vci_param::CMD_WRITE; p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); - p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0; break; @@ -4888,5 +4862,4 @@ p_vci_ini_d.cmd = vci_param::CMD_STORE_COND; p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1); - p_vci_ini_d.pktid = (r_dreq_isUser_save == true) ? _CMD_USR : 0; break; } // end switch r_vci_cmd_fsm