Changeset 200 for trunk/modules

Timestamp:

Feb 21, 2012, 7:55:14 PM (13 years ago)

Author:

alain

Message:

 

Location:

trunk/modules/vci_mem_cache_v4/caba/source

Files:

• include/update_tab_v4.h (modified) (2 diffs)
• include/vci_mem_cache_v4.h (modified) (3 diffs)
• src/vci_mem_cache_v4.cpp (modified) (100 diffs)

trunk/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h

@@ -15 +15 @@
 
   public:
-  bool  valid;                // It is a valid pending transaction
-  bool  update;               // It is an update transaction
-  bool  brdcast;              // It is a broadcast invalidate
-  bool  rsp;                  // It needs a response to the initiator
-  size_t        srcid;        // The srcid of the initiator which wrote the data
-  size_t        trdid;        // The trdid of the initiator which wrote the data
-  size_t        pktid;        // The pktid of the initiator which wrote the data
-  addr_t        nline;        // The identifier of the cache line
-  size_t        count;        // The number of acknowledge responses to receive
+  bool      valid;      // It is a valid pending transaction
+  bool      update;     // It is an update transaction
+  bool      brdcast;    // It is a broadcast invalidate
+  bool      rsp;        // It needs a response to the initiator
+  size_t        srcid;      // The srcid of the initiator which wrote the data
+  size_t        trdid;      // The trdid of the initiator which wrote the data
+  size_t        pktid;      // The pktid of the initiator which wrote the data
+  addr_t        nline;      // The identifier of the cache line
+  size_t        count;      // The number of acknowledge responses to receive
 
   UpdateTabEntry(){
@@ -49 +49 @@
     valid       = i_valid;
     update      = i_update;
-    brdcast     = i_brdcast;
-    rsp         = i_rsp;
+    brdcast = i_brdcast;
+    rsp     = i_rsp;
     srcid       = i_srcid;
     trdid       = i_trdid;

trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

@@ -146 +146 @@
         WRITE_NEXT,
         WRITE_DIR_LOCK,
-        WRITE_DIR_HIT_READ,
+        WRITE_DIR_READ,
         WRITE_DIR_HIT,
         WRITE_UPT_LOCK,
-        WRITE_HEAP_LOCK,
+        WRITE_UPT_HEAP_LOCK,
         WRITE_UPT_REQ,
-        WRITE_UPDATE,
+        WRITE_UPT_NEXT,
         WRITE_UPT_DEC,
         WRITE_RSP,
-        WRITE_TRT_LOCK,
-        WRITE_TRT_DATA,
-        WRITE_TRT_SET,
+        WRITE_MISS_TRT_LOCK,
+        WRITE_MISS_TRT_DATA,
+        WRITE_MISS_TRT_SET,
+        WRITE_MISS_XRAM_REQ,
+        WRITE_BC_TRT_LOCK,
+        WRITE_BC_UPT_LOCK,
+        WRITE_BC_DIR_INVAL,
+        WRITE_BC_CC_SEND,
+        WRITE_BC_XRAM_REQ,
         WRITE_WAIT,
-        WRITE_XRAM_REQ,
-        WRITE_TRT_WRITE_LOCK,
-        WRITE_INVAL_LOCK,
-        WRITE_DIR_INVAL,
-        WRITE_INVAL,
-        WRITE_XRAM_SEND,
       };
 
@@ -211 +211 @@
         SC_DIR_HIT_WRITE,
         SC_UPT_LOCK,
-        SC_WAIT,
-        SC_HEAP_LOCK,
+        SC_UPT_HEAP_LOCK,
         SC_UPT_REQ,
         SC_UPT_NEXT,
-        SC_TRT_PUT_LOCK,
-        SC_INVAL_LOCK,
-        SC_DIR_INVAL,
-        SC_INVAL,
-        SC_TRT_PUT_REQ,
+        SC_BC_TRT_LOCK,
+        SC_BC_UPT_LOCK,
+        SC_BC_DIR_INVAL,
+        SC_BC_CC_SEND,
+        SC_BC_XRAM_REQ,
         SC_RSP_FAIL,
         SC_RSP_SUCCESS,
-        SC_TRT_GET_LOCK,
-        SC_TRT_GET_SET,
-        SC_TRT_GET_REQ,
+        SC_MISS_TRT_LOCK,
+        SC_MISS_TRT_SET,
+        SC_MISS_XRAM_REQ,
+        SC_WAIT,
       };
 
@@ -473 +473 @@
       sc_signal<data_t>   *r_write_data;            // data (one cache line)    
       sc_signal<be_t>     *r_write_be;              // one byte enable per word
-      sc_signal<bool>      r_write_byte;            // is it a byte write
+      sc_signal<bool>      r_write_byte;            // (BE != 0X0) and (BE != 0xF)
       sc_signal<bool>      r_write_is_cnt;          // is_cnt bit (in directory)
       sc_signal<bool>      r_write_lock;            // lock bit (in directory)

trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp

@@ -40 +40 @@
 #define DEBUG_MEMC_READ         1       // detailed trace of READ FSM
 #define DEBUG_MEMC_WRITE        1       // detailed trace of WRITE FSM  
-#define DEBUG_MEMC_SC           0       // detailed trace of SC FSM     
+#define DEBUG_MEMC_SC           1       // detailed trace of SC FSM     
 #define DEBUG_MEMC_IXR_CMD      1       // detailed trace of IXR_RSP FSM
 #define DEBUG_MEMC_IXR_RSP      1       // detailed trace of IXR_RSP FSM
 #define DEBUG_MEMC_XRAM_RSP     1       // detailed trace of XRAM_RSP FSM       
-#define DEBUG_MEMC_INIT_CMD     0       // detailed trace of INIT_CMD FSM       
-#define DEBUG_MEMC_INIT_RSP     0       // detailed trace of INIT_RSP FSM       
+#define DEBUG_MEMC_INIT_CMD     1       // detailed trace of INIT_CMD FSM       
+#define DEBUG_MEMC_INIT_RSP     1       // detailed trace of INIT_RSP FSM       
 #define DEBUG_MEMC_TGT_CMD      0       // detailed trace of TGT_CMD FSM        
 #define DEBUG_MEMC_TGT_RSP      0       // detailed trace of TGT_RSP FSM        
@@ -113 +113 @@
     "WRITE_NEXT",
     "WRITE_DIR_LOCK",
-    "WRITE_DIR_HIT_READ",
+    "WRITE_DIR_READ",
     "WRITE_DIR_HIT",
     "WRITE_UPT_LOCK",
-    "WRITE_HEAP_LOCK",
+    "WRITE_UPT_HEAP_LOCK",
     "WRITE_UPT_REQ",
-    "WRITE_UPDATE",
+    "WRITE_UPT_NEXT",
     "WRITE_UPT_DEC",
     "WRITE_RSP",
-    "WRITE_TRT_LOCK",
-    "WRITE_TRT_DATA",
-    "WRITE_TRT_SET",
+    "WRITE_MISS_TRT_LOCK",
+    "WRITE_MISS_TRT_DATA",
+    "WRITE_MISS_TRT_SET",
+    "WRITE_MISS_XRAM_REQ",
+    "WRITE_BC_TRT_LOCK",
+    "WRITE_BC_UPT_LOCK",
+    "WRITE_BC_DIR_INVAL",
+    "WRITE_BC_CC_SEND",
+    "WRITE_BC_XRAM_REQ",
     "WRITE_WAIT",
-    "WRITE_XRAM_REQ",
-    "WRITE_TRT_WRITE_LOCK",
-    "WRITE_INVAL_LOCK",
-    "WRITE_DIR_INVAL",
-    "WRITE_INVAL",
-    "WRITE_XRAM_SEND",
   };
   const char *ixr_rsp_fsm_str[] = {
@@ -170 +170 @@
     "SC_DIR_HIT_WRITE",
     "SC_UPT_LOCK",
-    "SC_WAIT",
-    "SC_HEAP_LOCK",
+    "SC_UPT_HEAP_LOCK",
     "SC_UPT_REQ",
     "SC_UPT_NEXT",
-    "SC_TRT_PUT_LOCK",
-    "SC_INVAL_LOCK",
-    "SC_DIR_INVAL",
-    "SC_INVAL",
-    "SC_TRT_PUT_REQ",
+    "SC_BC_TRT_LOCK",
+    "SC_BC_UPT_LOCK",
+    "SC_BC_DIR_INVAL",
+    "SC_BC_CC_SEND",
+    "SC_BC_XRAM_REQ",
     "SC_RSP_FAIL",
     "SC_RSP_SUCCESS",
-    "SC_TRT_GET_LOCK",
-    "SC_TRT_GET_SET",
-    "SC_TRT_GET_REQ",
+    "SC_MISS_TRT_LOCK",
+    "SC_MISS_TRT_SET",
+    "SC_MISS_XRAM_REQ",
+    "SC_WAIT",
   };
   const char *cleanup_fsm_str[] = {
@@ -289 +289 @@
 
     //  FIFOs 
+
     m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
     m_cmd_read_length_fifo("m_cmd_read_length_fifo", 4),
@@ -316 +317 @@
 
     r_read_fsm("r_read_fsm"),
+
     r_write_fsm("r_write_fsm"),
+
     m_write_to_init_cmd_inst_fifo("m_write_to_init_cmd_inst_fifo",8),
     m_write_to_init_cmd_srcid_fifo("m_write_to_init_cmd_srcid_fifo",8),
@@ -322 +325 @@
     m_write_to_init_cmd_cache_id_fifo("m_write_to_init_cmd_cache_id_fifo",8),
 #endif
+
     r_init_rsp_fsm("r_init_rsp_fsm"),
     r_cleanup_fsm("r_cleanup_fsm"),
+
     r_sc_fsm("r_sc_fsm"),
+
     m_sc_to_init_cmd_inst_fifo("m_sc_to_init_cmd_inst_fifo",8),
     m_sc_to_init_cmd_srcid_fifo("m_sc_to_init_cmd_srcid_fifo",8),
@@ -330 +336 @@
     m_sc_to_init_cmd_cache_id_fifo("m_sc_to_init_cmd_cache_id_fifo",8),
 #endif
+
     r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
     r_xram_rsp_fsm("r_xram_rsp_fsm"),
+
     m_xram_rsp_to_init_cmd_inst_fifo("m_xram_rsp_to_init_cmd_inst_fifo",8),
     m_xram_rsp_to_init_cmd_srcid_fifo("m_xram_rsp_to_init_cmd_srcid_fifo",8),
@@ -337 +345 @@
     m_xram_rsp_to_init_cmd_cache_id_fifo("m_xram_rsp_to_init_cmd_cache_id_fifo",8),
 #endif
+
     r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
+
     r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
+
     r_init_cmd_fsm("r_init_cmd_fsm"),
+
     r_alloc_dir_fsm("r_alloc_dir_fsm"),
     r_alloc_trt_fsm("r_alloc_trt_fsm"),
     r_alloc_upt_fsm("r_alloc_upt_fsm")
+
     {
       assert(IS_POW_OF_2(nsets));
@@ -879 +892 @@
     /////////////////////////////////////////////////////////////////////////
     // This FSM controls the response to the update or inval coherence
-    // requests sent by the memory cache to the L1 caches :
-    //
+    // requests sent by the memory cache to the L1 caches and update the UPT.
+    // 
     // It can be update or inval requests initiated by the WRITE FSM,
     // or inval requests initiated by the XRAM_RSP FSM.  
+    // It can also be a direct request from the WRITE FSM.
+    //
     // The FSM decrements the proper entry in UPT.
     // It sends a request to the TGT_RSP FSM to complete the pending 
@@ -912 +927 @@
                 {
                     std::cout << "VCI_MEM_CACHE ERROR " << name() 
-                              << " INIT_RSP_IDLE state" << std::endl;
-                    std::cout << "index too large for UPT: " 
+                              << " INIT_RSP_IDLE state" << std::endl
+                              << "index too large for UPT: " 
                               << " / rtrdid = " << p_vci_ini.rtrdid.read()
                               << " / UPT size = " << m_update_tab.size() << std::endl;
@@ -955 +970 @@
                 if ( not valid )
                 {
-                    std::cout << "VCI_MEM_CACHE ERROR " << name() << " INIT_RSP_UPT_LOCK state" << std::endl;
-                    std::cout << "unsuccessful access to decrement the UPT" << std::endl;
+                    std::cout << "VCI_MEM_CACHE ERROR " << name() 
+                              << " INIT_RSP_UPT_LOCK state" << std::endl
+                              << "unsuccessful access to decrement the UPT" << std::endl;
                     exit(0);
                 }
@@ -1511 +1527 @@
     //   If the UPT is full, it releases the lock(s) and retry. Then, it sends 
     //   a multi-update request to all owners of the line (but the writer), 
-    //   through the INIT_CMD FSM. In case of multi-update transaction, the WRITE FSM 
+    //   through the INIT_CMD FSM. In case of coherence transaction, the WRITE FSM 
     //   does not respond to the writing processor, as this response will be sent by 
     //   the INIT_RSP FSM when all update responses have been received.
@@ -1635 +1651 @@
                     if( entry.is_cnt && entry.count ) 
                     {
-                        r_write_fsm      = WRITE_DIR_HIT_READ;
+                        r_write_fsm      = WRITE_DIR_READ;
                     } 
                     else 
                     {
-                        if (r_write_byte.read())        r_write_fsm = WRITE_DIR_HIT_READ;
+                        if (r_write_byte.read())        r_write_fsm = WRITE_DIR_READ;
                         else                                    r_write_fsm = WRITE_DIR_HIT;
                     }
@@ -1645 +1661 @@
                 else    // miss
                 {
-                    r_write_fsm = WRITE_TRT_LOCK;
+                    r_write_fsm = WRITE_MISS_TRT_LOCK;
                 }
 
@@ -1652 +1668 @@
 {
     std::cout << "  <MEMC.WRITE_DIR_LOCK> Check the directory: "
-              << " address = " << r_write_address.read()
+              << " address = " << std::hex << r_write_address.read()
               << " hit = " << entry.valid 
               << " count = " << std::dec << entry.count 
@@ -1661 +1677 @@
             break;
         }
-        ////////////////////////
-        case WRITE_DIR_HIT_READ:        // read the cache and complete the buffer when be!=0xF
+        ////////////////////
+        case WRITE_DIR_READ:    // read the cache and complete the buffer when be!=0xF
         {
             // update local buffer
@@ -1684 +1700 @@
 
             // test if a coherence broadcast is required
-            if( r_write_is_cnt.read() && r_write_count.read() ) r_write_fsm = WRITE_TRT_WRITE_LOCK;
-            else                                                r_write_fsm = WRITE_DIR_HIT;
+            if( r_write_is_cnt.read() && r_write_count.read() ) r_write_fsm = WRITE_BC_TRT_LOCK;
+            else                                                                        r_write_fsm = WRITE_DIR_HIT;
 
 #if DEBUG_MEMC_WRITE
@@ -1692 +1708 @@
     if( r_write_is_cnt.read() && r_write_count.read() )
     {
-        std::cout << "  <MEMC.WRITE_DIR_HIT_READ> Read the cache to complete local buffer /" 
+        std::cout << "  <MEMC.WRITE_DIR_READ> Read the cache to complete local buffer /" 
                   << " coherence broadcast required" << std::endl;
     }
     else
     {
-        std::cout << "  <MEMC.WRITE_DIR_HIT_READ> Read the cache to complete local buffer" 
+        std::cout << "  <MEMC.WRITE_DIR_READ> Read the cache to complete local buffer" 
                   << std::endl;
     } 
@@ -1705 +1721 @@
         }
         ///////////////////
-        case WRITE_DIR_HIT:        // update the cache (data & directory)
+        case WRITE_DIR_HIT:        // update the cache directory
         {
             // update directory with Dirty bit
@@ -1727 +1743 @@
             m_cache_directory.write(set, way, entry);
 
-            // owner is true when the writer is the owner
+            // owner is true when the  the first registered copy is the writer itself
             bool owner = (((r_write_copy.read() == r_write_srcid.read())
 #if L1_MULTI_CACHE
@@ -1737 +1753 @@
             bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1));
 
-            // write data in the cache if no transaction on the coherence network
+            // write data in the cache if no coherence transaction 
             if( no_update ) 
             {
@@ -1747 +1763 @@
 
             if ( owner )   r_write_count = r_write_count.read() - 1;
-            r_write_to_dec = false;
 
             if ( no_update )      // Write transaction completed
@@ -1757 +1772 @@
                 if( !r_write_to_init_cmd_multi_req.read() && 
                    !r_write_to_init_cmd_brdcast_req.read()  )   r_write_fsm = WRITE_UPT_LOCK;
-                else                                            r_write_fsm = WRITE_WAIT;
+                else                                                                r_write_fsm = WRITE_WAIT;
             }
 
@@ -1779 +1794 @@
             break;
         }
-        /////////////////////
+        ////////////////////
         case WRITE_UPT_LOCK:    // Try to register the update request in UPT
         {
@@ -1818 +1833 @@
         std::cout << "  <MEMC.WRITE_UPT_LOCK> Register the multicast update in UPT / " 
                   << " nb_copies = " << r_write_count.read() << std::endl;
-        //m_update_tab.print();
     }
 }
 #endif
                 r_write_upt_index = index;
-                //  releases the lock protecting the Update Table and the Directory if no entry...
-                if ( wok ) r_write_fsm = WRITE_HEAP_LOCK;
+                //  releases the lock protecting UPT and the DIR if no entry...
+                if ( wok ) r_write_fsm = WRITE_UPT_HEAP_LOCK;
                 else       r_write_fsm = WRITE_WAIT;
             }
@@ -1830 +1844 @@
         }
         /////////////////////
-        case WRITE_HEAP_LOCK:
+        case WRITE_UPT_HEAP_LOCK:   // get access to heap
         {
             if( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE )
@@ -1838 +1852 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_HEAP_LOCK> Get acces to the HEAP" << std::endl;
+    std::cout << "  <MEMC.WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
 }
 #endif
@@ -1846 +1860 @@
         }
         //////////////////
-        case WRITE_UPT_REQ:
-        {
-            if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_WRITE )
-            {
-                std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_REQ state" << std::endl;
-                std::cout << "bad HEAP allocation" << std::endl;
-                exit(0);
-            }
-
+        case WRITE_UPT_REQ:     //  prepare the request to INIT_CMD FSM
+                                //  and write the first srcid in the FIFO
+                                //  send the request if only one copy
+        {
             if( !r_write_to_init_cmd_multi_req.read() && 
-                !r_write_to_init_cmd_brdcast_req.read()  )
+                !r_write_to_init_cmd_brdcast_req.read()  )  // no pending coherence request
             {
                 r_write_to_init_cmd_brdcast_req  = false;
@@ -1864 +1873 @@
                 r_write_to_init_cmd_count        = r_write_word_count.read();
 
-                for(size_t i=0; i<m_words ; i++)
-                {
-                    r_write_to_init_cmd_be[i]=r_write_be[i].read();
-                }
+                for(size_t i=0; i<m_words ; i++) r_write_to_init_cmd_be[i]=r_write_be[i].read();
 
                 size_t min = r_write_word_index.read();
                 size_t max = r_write_word_index.read() + r_write_word_count.read();
-                for (size_t i=min ; i<max ; i++)  r_write_to_init_cmd_data[i] = r_write_data[i];
+                for (size_t i=min ; i<max ; i++) r_write_to_init_cmd_data[i] = r_write_data[i];
             
                 if( (r_write_copy.read() != r_write_srcid.read()) or
@@ -1879 +1885 @@
                     r_write_copy_inst.read() ) 
                 {
-                    // We put the first copy in the fifo
+                    // put the first srcid in the fifo
                     write_to_init_cmd_fifo_put     = true;
                     write_to_init_cmd_fifo_inst    = r_write_copy_inst.read();
@@ -1893 +1899 @@
                     else 
                     {
-                        r_write_fsm = WRITE_UPDATE;
+                        r_write_fsm = WRITE_UPT_NEXT;
+                        r_write_to_dec = false;
+
                     }
                 } 
                 else 
                 {
-                    r_write_fsm = WRITE_UPDATE;
-                }
-            }
-            break;
-        }
-        //////////////////
-        case WRITE_UPDATE:      // send a multi-update request to INIT_CMD fsm
-        {
-            if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_WRITE )
-            {
-                std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPDATE state" << std::endl;
-                std::cout << "bad HEAP allocation" << std::endl;
-                exit(0);
-            }
-
+                    r_write_fsm = WRITE_UPT_NEXT;
+                    r_write_to_dec = false;
+                }
+            }
+            break;
+        }
+        ///////////////////
+        case WRITE_UPT_NEXT:    // continue the multi-update request to INIT_CMD fsm
+                                // when there is copies in the heap.
+                                // if one copy in the heap is the writer itself
+                                // the corresponding SRCID should not be written in the fifo,
+                                // but the UPT counter must be decremented.
+                                // As this decrement is done in the WRITE_UPT_DEC state,
+                                // after the last copy has been found, the decrement request
+                                // must be  registered in the r_write_to_dec flip-flop.
+        {
             HeapEntry entry = m_heap.read(r_write_ptr.read());
-            write_to_init_cmd_fifo_inst     = entry.owner.inst;
-            write_to_init_cmd_fifo_srcid    = entry.owner.srcid;
-#if L1_MULTI_CACHE
-            write_to_init_cmd_fifo_cache_id = entry.owner.cache_id;
-#endif
           
-            bool dec_upt_counter = r_write_to_dec.read();
+            bool dec_upt_counter; // = r_write_to_dec.read();
+
             if( (entry.owner.srcid != r_write_srcid.read()) or
 #if L1_MULTI_CACHE
                 (entry.owner.cache_id != r_write_pktid.read()) or
 #endif
-                entry.owner.inst)
-            {
-                write_to_init_cmd_fifo_put = true;
+                entry.owner.inst)   // put te next srcid in the fifo
+            {
+                dec_upt_counter                 = false;
+                write_to_init_cmd_fifo_put      = true;
+                write_to_init_cmd_fifo_inst     = entry.owner.inst;
+                write_to_init_cmd_fifo_srcid    = entry.owner.srcid;
+#if L1_MULTI_CACHE
+                write_to_init_cmd_fifo_cache_id = entry.owner.cache_id;
+#endif
             } 
-            else 
+            else                    // the UPT counter must be decremented
             {
                 dec_upt_counter = true;
             }
-            r_write_to_dec = dec_upt_counter;
-
-            if( m_write_to_init_cmd_inst_fifo.wok() )
-            {
-                r_write_ptr = entry.next;
-                if( entry.next == r_write_ptr.read() )  // last copy
-                {
-                    r_write_to_init_cmd_multi_req = true;
-                    if(dec_upt_counter) r_write_fsm = WRITE_UPT_DEC;
-                    else                r_write_fsm = WRITE_IDLE;
-                } 
-                else 
-                {
-                    r_write_fsm = WRITE_UPDATE;
-                }
+
+            // register the possible UPT decrement request
+            r_write_to_dec = dec_upt_counter or r_write_to_dec.read();
+
+            if( not m_write_to_init_cmd_inst_fifo.wok() ) 
+            {
+                std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl
+                          << "The write_to_cmd_write_fifo should not be full" << std::endl
+                          << "as the depth should be larger than the max number of copies" << std::endl;
+                exit(0);
+            }
+
+            r_write_ptr = entry.next;
+
+            if( entry.next == r_write_ptr.read() )  // last copy
+            {
+                r_write_to_init_cmd_multi_req = true;
+                if( r_write_to_dec.read() or dec_upt_counter)   r_write_fsm = WRITE_UPT_DEC;
+                else                                                r_write_fsm = WRITE_IDLE;
             } 
-            else 
-            {
-                r_write_fsm = WRITE_UPDATE;
-            }
             break;
         }
         //////////////////
-        case WRITE_UPT_DEC:     // Post another coherence update request
+        case WRITE_UPT_DEC:     // If the initial writer has a copy, it should not
+                                // receive an update request, but the counter in the
+                                // update table must be decremented by the INIT_RSP FSM.
         {
             if ( !r_write_to_init_rsp_req.read() )
@@ -1983 +1996 @@
                 r_write_to_tgt_rsp_trdid = r_write_trdid.read();
                 r_write_to_tgt_rsp_pktid = r_write_pktid.read();
-                r_write_fsm              = WRITE_IDLE;
-            }
-            break;
-        }
-        ////////////////////
-        case WRITE_TRT_LOCK:    // Miss : check Transaction Table
+                r_write_fsm              = WRITE_IDLE;
+            }
+            break;
+        }
+        /////////////////////////
+        case WRITE_MISS_TRT_LOCK:       // Miss : check Transaction Table
         {
             if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
@@ -1996 +2009 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_TRT_LOCK> Check the TRT" << std::endl;
+    std::cout << "  <MEMC.WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
 }
 #endif
@@ -2009 +2022 @@
                 {
                     r_write_trt_index = hit_index;
-                    r_write_fsm       = WRITE_TRT_DATA;
+                    r_write_fsm       = WRITE_MISS_TRT_DATA;
                     m_cpt_write_miss++;
                 } 
@@ -2015 +2028 @@
                 {
                     r_write_trt_index = wok_index;
-                    r_write_fsm       = WRITE_TRT_SET;
+                    r_write_fsm       = WRITE_MISS_TRT_SET;
                     m_cpt_write_miss++;
                 } 
@@ -2039 +2052 @@
             break;
         }
-        ///////////////////
-        case WRITE_TRT_SET:     // register a new transaction in TRT (Write Buffer)
+        ////////////////////////
+        case WRITE_MISS_TRT_SET:        // register a new transaction in TRT (Write Buffer)
         {  
             if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
@@ -2064 +2077 @@
                                       be_vector,
                                       data_vector);
-                r_write_fsm = WRITE_XRAM_REQ;
+                r_write_fsm = WRITE_MISS_XRAM_REQ;
 
 #if DEBUG_MEMC_WRITE
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_TRT_SET> Set a new entry in TRT" << std::endl;
+    std::cout << "  <MEMC.WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
 }
 #endif
@@ -2075 +2088 @@
             break;
         }  
-        ////////////////////
-        case WRITE_TRT_DATA:    // update an entry in TRT (Write Buffer)
+        /////////////////////////
+        case WRITE_MISS_TRT_DATA:       // update an entry in TRT (used as a Write Buffer)
         { 
             if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
@@ -2097 +2110 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_TRT_DATA> Modify an existing entry in TRT" << std::endl;
+    std::cout << "  <MEMC.WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
     m_transaction_tab.print( r_write_trt_index.read() );
 }
@@ -2104 +2117 @@
             break;
         }
-        ////////////////////
-        case WRITE_XRAM_REQ:    // send a request to IXR_CMD FSM
+        /////////////////////////
+        case WRITE_MISS_XRAM_REQ:       // send a GET request to IXR_CMD FSM
         {  
             if ( !r_write_to_ixr_cmd_req ) 
@@ -2118 +2131 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_XRAM_REQ> Post a request to the IXR_CMD FSM" << std::endl;
-}
-#endif
-            }
-            break;
-        }
-        //////////////////////////
-        case WRITE_TRT_WRITE_LOCK:      // Check TRT not full
+    std::cout << "  <MEMC.WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        ///////////////////////
+        case WRITE_BC_TRT_LOCK:     // Check TRT not full
         {
             if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
@@ -2134 +2147 @@
                 {
                     r_write_trt_index = wok_index;
-                    r_write_fsm       = WRITE_INVAL_LOCK;
+                    r_write_fsm       = WRITE_BC_UPT_LOCK;
                 } 
                 else    // wait an empty entry in TRT
@@ -2144 +2157 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_TRT_WRITE_LOCK> Check TRT : wok = "
-              << wok << " index = " << wok_index << std::endl;
+    std::cout << "  <MEMC.WRITE_BC_TRT_LOCK> Check TRT : wok = "
+              << wok << " / index = " << wok_index << std::endl;
 }
 #endif
@@ -2152 +2165 @@
         }
         //////////////////////
-        case WRITE_INVAL_LOCK:
+        case WRITE_BC_UPT_LOCK:      // register BC transaction in UPT
         {
             if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) 
@@ -2179 +2192 @@
     if ( wok )
     { 
-        std::cout << "  <MEMC.WRITE_INVAL_LOCK> Register the broadcast inval in UPT / " 
+        std::cout << "  <MEMC.WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / " 
                   << " nb_copies = " << r_write_count.read() << std::endl;
-        //m_update_tab.print();
     }
 }
@@ -2187 +2199 @@
                 r_write_upt_index = index;
 
-                if ( wok ) r_write_fsm = WRITE_DIR_INVAL;
+                if ( wok ) r_write_fsm = WRITE_BC_DIR_INVAL;
                 else       r_write_fsm = WRITE_WAIT;
             }
             break;
         }
-        /////////////////////
-        case WRITE_DIR_INVAL:   // Register a put transaction to XRAM in TRT
+        ////////////////////////
+        case WRITE_BC_DIR_INVAL:        // Register a put transaction to XRAM in TRT
                                 // and invalidate the line in directory
         {
@@ -2200 +2212 @@
                  (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) )
             {
-                std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_DIR_INVAL state" << std::endl;
+                std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl;
                 std::cout << "bad TRT, DIR, or UPT allocation" << std::endl;
                 exit(0);
@@ -2239 +2251 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_DIR_INVAL> Invalidate the directory entry: @ = "
+    std::cout << "  <MEMC.WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
               << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
 }
 #endif
-            r_write_fsm = WRITE_INVAL;
-            break;
-        }
-        /////////////////
-        case WRITE_INVAL:    // Post a coherence broadcast request to INIT_CMD FSM
+            r_write_fsm = WRITE_BC_CC_SEND;
+            break;
+        }
+        //////////////////////
+        case WRITE_BC_CC_SEND:    // Post a coherence broadcast request to INIT_CMD FSM
         {
             if ( !r_write_to_init_cmd_multi_req.read() && !r_write_to_init_cmd_brdcast_req.read() ) 
@@ -2263 +2275 @@
                     r_write_to_init_cmd_data[i] = 0;
                 }
-                r_write_fsm = WRITE_XRAM_SEND;
+                r_write_fsm = WRITE_BC_XRAM_REQ;
 
 #if DEBUG_MEMC_WRITE
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_INVAL> Post a broadcast request to INIT_CMD FSM" << std::endl;
-}
-#endif
-            }
-            break;
-        }
-        /////////////////////
-        case WRITE_XRAM_SEND:   // Post a put request to IXR_CMD FSM
+    std::cout << "  <MEMC.WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        ///////////////////////
+        case WRITE_BC_XRAM_REQ:   // Post a put request to IXR_CMD FSM
         {
             if ( !r_write_to_ixr_cmd_req ) 
@@ -2291 +2303 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_XRAM_SEND> Post a put request to IXR_CMD FSM" << std::endl;
+    std::cout << "  <MEMC.WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
 }
 #endif
@@ -2303 +2315 @@
     ///////////////////////////////////////////////////////////////////////
     // The IXR_CMD fsm controls the command packets to the XRAM :
-    // - It sends a single cell VCI get request to the XRAM in case of MISS
+    // - It sends a single cell VCI read request to the XRAM in case of MISS
     // posted by the READ, WRITE or SC FSMs : the TRDID field contains 
     // the Transaction Tab index.
@@ -2345 +2357 @@
         else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
         break;
-        /////////////////////////
+        /////////////////////////       // send a get request to XRAM
         case IXR_CMD_READ_NLINE:
         if ( p_vci_ixr.cmdack ) 
@@ -2355 +2367 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram" ;
+    std::cout << "  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
 }
 #endif
@@ -2361 +2373 @@
         break;
         //////////////////////////
-        case IXR_CMD_WRITE_NLINE:       
+        case IXR_CMD_WRITE_NLINE:           // send a put or get command to XRAM
         if ( p_vci_ixr.cmdack ) 
         {
@@ -2380 +2392 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a put request to xram" ;
+    std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
 }
 #endif
@@ -2392 +2404 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a get request to xram" ;
+    std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
 }
 #endif
@@ -2399 +2411 @@
         break;
         //////////////////////
-        case IXR_CMD_SC_NLINE:
+        case IXR_CMD_SC_NLINE:      // send a put or get command to XRAM
         if ( p_vci_ixr.cmdack ) 
         {
@@ -2418 +2430 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a put request to xram" ;
+    std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a put request to xram" << std::endl;
 }
 #endif
@@ -2430 +2442 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a get request to xram" ;
+    std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a get request to xram" << std::endl;
 }
 #endif
@@ -2437 +2449 @@
         break;
         ////////////////////////
-        case IXR_CMD_XRAM_DATA:
+        case IXR_CMD_XRAM_DATA:     // send a put command to XRAM
         if ( p_vci_ixr.cmdack ) 
         {
@@ -2454 +2466 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_XRAM_DATA> Send a put request to xram" ;
+    std::cout << "  <MEMC.IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
 }
 #endif
@@ -2483 +2495 @@
     switch ( r_ixr_rsp_fsm.read() ) 
     {
-        ///////////////////
+        //////////////////
         case IXR_RSP_IDLE:      // test if it's a get or a put transaction
         {
@@ -3751 +3763 @@
 
                 if ( entry.valid )      r_sc_fsm = SC_DIR_HIT_READ; 
-                else                    r_sc_fsm = SC_TRT_GET_LOCK;
+                else                        r_sc_fsm = SC_MISS_TRT_LOCK;
 
 #if DEBUG_MEMC_SC
@@ -3820 +3832 @@
             break;
         }
-        ///// ////////////////
+        //////////////////////
         case SC_DIR_HIT_WRITE:          // write data in the cache
                                     // and test if a coherence request is required
@@ -3838 +3850 @@
                 if ( r_sc_is_cnt.read() )
                 {
-                    r_sc_fsm = SC_TRT_PUT_LOCK;                 // broadcast invalidate required
+                    r_sc_fsm = SC_BC_TRT_LOCK;          // broadcast invalidate required
                 }
                 else if( !r_sc_to_init_cmd_multi_req.read() && 
@@ -3893 +3905 @@
                 {
                     r_sc_upt_index = index;
-                    r_sc_fsm = SC_HEAP_LOCK;
+                    r_sc_fsm = SC_UPT_HEAP_LOCK;
                 }
                 else       //  releases the locks protecting UPT and DIR if no entry
@@ -3926 +3938 @@
         }
         //////////////////
-        case SC_HEAP_LOCK:      // lock the heap
+        case SC_UPT_HEAP_LOCK:  // lock the heap
         {
             if( r_alloc_heap_fsm.read() == ALLOC_HEAP_SC ) 
@@ -3934 +3946 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_HEAP_LOCK> Get access to the heap" << std::endl;
+    std::cout << "  <MEMC.SC_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
 }
 #endif
@@ -4039 +4051 @@
         }
         /////////////////////
-        case SC_TRT_PUT_LOCK:           // check the TRT to register a PUT transaction     
+        case SC_BC_TRT_LOCK:            // check the TRT to register a PUT transaction     
         {
             if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) 
@@ -4069 +4081 @@
                     {
                         r_sc_trt_index = wok_index;
-                        r_sc_fsm       = SC_INVAL_LOCK; 
+                        r_sc_fsm       = SC_BC_UPT_LOCK; 
                     } 
                     else 
@@ -4084 +4096 @@
         }
         ///////////////////
-        case SC_INVAL_LOCK:  // Register a broadcast inval transaction in UPT
+        case SC_BC_UPT_LOCK:  // Register a broadcast inval transaction in UPT
         {
             if ( r_alloc_upt_fsm.read() == ALLOC_UPT_SC ) 
@@ -4110 +4122 @@
                 {
                     r_sc_upt_index = index;
-                    r_sc_fsm = SC_DIR_INVAL;
+                    r_sc_fsm = SC_BC_DIR_INVAL;
 #if DEBUG_MEMC_SC
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_INVAL_LOCK> Register a broadcast inval transaction in UPT"
+    std::cout << "  <MEMC.SC_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
               << " / nline = " << nline 
               << " / count = " << nb_copies 
@@ -4129 +4141 @@
         }
         //////////////////
-        case SC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
+        case SC_BC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
         {
             if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) &&
@@ -4166 +4178 @@
                 m_cache_directory.write(set, way, entry);
 
-                r_sc_fsm = SC_INVAL;
+                r_sc_fsm = SC_BC_CC_SEND;
 
 #if DEBUG_MEMC_SC
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
+    std::cout << "  <MEMC.SC_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
               << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]
               << " / set = " << std::dec << set << " / way = " << way << std::endl;
@@ -4179 +4191 @@
             else 
             {
-                assert(false and "LOCK ERROR in SC_FSM, STATE = SC_DIR_INVAL");
-            }
-            break;
-        }
-        //////////////
-        case SC_INVAL:  // Request the broadcast inval to INIT_CMD FSM
+                assert(false and "LOCK ERROR in SC_FSM, STATE = SC_BC_DIR_INVAL");
+            }
+            break;
+        }
+        ///////////////////
+        case SC_BC_CC_SEND:  // Request the broadcast inval to INIT_CMD FSM
         {
             if ( !r_sc_to_init_cmd_multi_req.read() &&
@@ -4196 +4208 @@
                 r_sc_to_init_cmd_wdata        = 0;
 
-                r_sc_fsm = SC_TRT_PUT_REQ;
+                r_sc_fsm = SC_BC_XRAM_REQ;
             }
             break;
         }
         ////////////////////
-        case SC_TRT_PUT_REQ: // request the IXR FSM to start a put transaction
+        case SC_BC_XRAM_REQ: // request the IXR FSM to start a put transaction
         {
             if ( !r_sc_to_ixr_cmd_req ) 
@@ -4216 +4228 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_TRT_PUT_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
+    std::cout << "  <MEMC.SC_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
               << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
               << " / trt_index = " << r_sc_trt_index.read() << std::endl;
@@ -4224 +4236 @@
             else 
             {
-               std::cout << "MEM_CACHE, SC_TRT_PUT_REQ state : request should not have been previously set"
+               std::cout << "MEM_CACHE, SC_BC_XRAM_REQ state : request should not have been previously set"
                          << std::endl;
             }
@@ -4276 +4288 @@
         }
         /////////////////////
-        case SC_TRT_GET_LOCK:         // cache miss : request access to transaction Table
+        case SC_MISS_TRT_LOCK:         // cache miss : request access to transaction Table
         {
             if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) 
@@ -4290 +4302 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_TRT_GET_LOCK> Check TRT state" 
+    std::cout << "  <MEMC.SC_MISS_TRT_LOCK> Check TRT state" 
               << " / hit_read = "  << hit_read
               << " / hit_write = " << hit_write
@@ -4305 +4317 @@
                 {
                     r_sc_trt_index = index;
-                    r_sc_fsm       = SC_TRT_GET_SET;
+                    r_sc_fsm       = SC_MISS_TRT_SET;
                 }
             }
@@ -4311 +4323 @@
         }
         ////////////////////
-        case SC_TRT_GET_SET:    // register the GET transaction in TRT
+        case SC_MISS_TRT_SET:   // register the GET transaction in TRT
         {
             if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) 
@@ -4336 +4348 @@
                                       be_vector,
                                       data_vector);
-                r_sc_fsm = SC_TRT_GET_REQ;        
+                r_sc_fsm = SC_MISS_XRAM_REQ;        
 
 #if DEBUG_MEMC_SC
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_TRT_GET_SET> Register a GET transaction in TRT" << std::hex
+    std::cout << "  <MEMC.SC_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
               << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] 
               << " / trt_index = " << r_sc_trt_index.read() << std::endl;
@@ -4349 +4361 @@
             break;
         }
-        ////////////////////
-        case SC_TRT_GET_REQ:    // request the IXR_CMD FSM to fetch the missing line
+        //////////////////////
+        case SC_MISS_XRAM_REQ:  // request the IXR_CMD FSM to fetch the missing line
         {
             if ( !r_sc_to_ixr_cmd_req ) 
@@ -4363 +4375 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_TRT_GET_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
+    std::cout << "  <MEMC.SC_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
               << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
               << " / trt_index = " << r_sc_trt_index.read() << std::endl;
@@ -4377 +4389 @@
     //          INIT_CMD FSM
     //////////////////////////////////////////////////////////////////////////////
-    // The INIT_CMD fsm controls the VCI CMD initiator port, used to update
-    // or invalidate cache lines in L1 caches.
+    // The INIT_CMD fsm controls the VCI CMD initiator port on the coherence
+    // network, used to update or invalidate cache lines in L1 caches.
     //
     // It implements a round-robin priority between the three possible client FSMs
@@ -4959 +4971 @@
         {
           if      ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
-                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+                   (r_write_fsm.read() == WRITE_BC_UPT_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
           else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
           else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
           else if ((r_sc_fsm.read() == SC_UPT_LOCK) ||
-                   (r_sc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
+                   (r_sc_fsm.read() == SC_BC_UPT_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
         }
         break;
@@ -4970 +4982 @@
       case ALLOC_UPT_WRITE:
         if ( (r_write_fsm.read() != WRITE_UPT_LOCK) &&
-             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+             (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) 
         {
           if      (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
           else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
           else if ((r_sc_fsm.read() == SC_UPT_LOCK) ||
-                   (r_sc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
+                   (r_sc_fsm.read() == SC_BC_UPT_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
           else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
         }
@@ -4986 +4998 @@
           if       (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)       r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
           else if ((r_sc_fsm.read() == SC_UPT_LOCK) ||
-                   (r_sc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
+                   (r_sc_fsm.read() == SC_BC_UPT_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
           else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
           else if ((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
-                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+                   (r_write_fsm.read() == WRITE_BC_UPT_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
         }
         break;
@@ -4998 +5010 @@
         {
           if      ((r_sc_fsm.read() == SC_UPT_LOCK) ||
-                   (r_sc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
+                   (r_sc_fsm.read() == SC_BC_UPT_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
           else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
           else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
-                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+                   (r_write_fsm.read() == WRITE_BC_UPT_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
           else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
         }
@@ -5009 +5021 @@
       case ALLOC_UPT_SC:
         if( (r_sc_fsm.read() != SC_UPT_LOCK) && 
-            (r_sc_fsm.read() != SC_INVAL_LOCK))
+            (r_sc_fsm.read() != SC_BC_UPT_LOCK))
         {
           if      (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
           else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
-                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+                   (r_write_fsm.read() == WRITE_BC_UPT_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
           else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
           else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
@@ -5054 +5066 @@
         /////////////////////
       case ALLOC_DIR_WRITE:
-        if ( ( (r_write_fsm.read() != WRITE_DIR_LOCK)     &&
-              (r_write_fsm.read() != WRITE_TRT_LOCK)     &&
-              (r_write_fsm.read() != WRITE_DIR_HIT_READ) &&
+        if ( ((r_write_fsm.read() != WRITE_DIR_LOCK) &&
+              (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) &&
+              (r_write_fsm.read() != WRITE_DIR_READ) &&
               (r_write_fsm.read() != WRITE_DIR_HIT) &&
-              (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
-              (r_write_fsm.read() != WRITE_INVAL_LOCK) &&
+              (r_write_fsm.read() != WRITE_BC_TRT_LOCK) &&
+              (r_write_fsm.read() != WRITE_BC_UPT_LOCK) &&
               (r_write_fsm.read() != WRITE_UPT_LOCK) &&
-              (r_write_fsm.read() != WRITE_HEAP_LOCK))
+              (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK))
             ||
-            ( (r_write_fsm.read()       == WRITE_HEAP_LOCK) &&
+            ( (r_write_fsm.read()       == WRITE_UPT_HEAP_LOCK) &&
               (r_alloc_heap_fsm.read()  == ALLOC_HEAP_WRITE) )
             ||
-            ( (r_write_fsm.read()     == WRITE_TRT_LOCK) &&
+            ( (r_write_fsm.read()     == WRITE_MISS_TRT_LOCK) &&
               (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)   )   )
         {
@@ -5081 +5093 @@
               (r_sc_fsm.read() != SC_DIR_HIT_READ )  &&
               (r_sc_fsm.read() != SC_DIR_HIT_WRITE ) &&
-//              (r_sc_fsm.read() != SC_TRT_GET_LOCK )    &&
-              (r_sc_fsm.read() != SC_TRT_PUT_LOCK)       &&
-              (r_sc_fsm.read() != SC_INVAL_LOCK)     &&
+//              (r_sc_fsm.read() != SC_MISS_TRT_LOCK )    &&
+              (r_sc_fsm.read() != SC_BC_TRT_LOCK)       &&
+              (r_sc_fsm.read() != SC_BC_UPT_LOCK)     &&
               (r_sc_fsm.read() != SC_UPT_LOCK)       &&
-              (r_sc_fsm.read() != SC_HEAP_LOCK))
+              (r_sc_fsm.read() != SC_UPT_HEAP_LOCK))
             ||
-            ( (r_sc_fsm.read()       == SC_HEAP_LOCK) &&
+            ( (r_sc_fsm.read()       == SC_UPT_HEAP_LOCK) &&
               (r_alloc_heap_fsm.read() == ALLOC_HEAP_SC) )
             ||
-            ( (r_sc_fsm.read()      == SC_TRT_GET_LOCK ) &&
+            ( (r_sc_fsm.read()      == SC_MISS_TRT_LOCK ) &&
               (r_alloc_trt_fsm.read() == ALLOC_TRT_SC)    ) )
         {
@@ -5142 +5154 @@
         if ( r_read_fsm.read() != READ_TRT_LOCK ) 
         {
-          if      ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
-                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
-          else if ((r_sc_fsm.read() == SC_TRT_GET_LOCK) ||
-                   (r_sc_fsm.read() == SC_TRT_PUT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
+          if      ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_BC_TRT_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) ||
+                   (r_sc_fsm.read() == SC_BC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
           else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
           else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
@@ -5153 +5165 @@
         /////////////////////
       case ALLOC_TRT_WRITE:
-        if ( (r_write_fsm.read() != WRITE_TRT_LOCK) &&
-             (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
-             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
-        {
-          if      ((r_sc_fsm.read() == SC_TRT_GET_LOCK) ||
-                   (r_sc_fsm.read() == SC_TRT_PUT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
+        if ( (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) &&
+             (r_write_fsm.read() != WRITE_BC_TRT_LOCK) &&
+             (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) 
+        {
+          if      ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) ||
+                   (r_sc_fsm.read() == SC_BC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
           else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
           else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
@@ -5167 +5179 @@
         ////////////////////
       case ALLOC_TRT_SC:
-        if ( (r_sc_fsm.read() != SC_TRT_GET_LOCK) &&
-             (r_sc_fsm.read() != SC_TRT_PUT_LOCK) &&
-             (r_sc_fsm.read() != SC_INVAL_LOCK))
+        if ( (r_sc_fsm.read() != SC_MISS_TRT_LOCK) &&
+             (r_sc_fsm.read() != SC_BC_TRT_LOCK) &&
+             (r_sc_fsm.read() != SC_BC_UPT_LOCK))
         { 
           if      (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
@@ -5175 +5187 @@
                     (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
           else if (r_read_fsm.read() == READ_TRT_LOCK)              r_alloc_trt_fsm = ALLOC_TRT_READ;
-          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)     ||
-                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK)     ||
+                   (r_write_fsm.read() == WRITE_BC_TRT_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
         }
         break;
@@ -5187 +5199 @@
                     (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
           else if (r_read_fsm.read() == READ_TRT_LOCK)              r_alloc_trt_fsm = ALLOC_TRT_READ;
-          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)    ||
-                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
-          else if ((r_sc_fsm.read() == SC_TRT_GET_LOCK) ||
-                   (r_sc_fsm.read() == SC_TRT_PUT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
+          else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK)    ||
+                   (r_write_fsm.read() == WRITE_BC_TRT_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) ||
+                   (r_sc_fsm.read() == SC_BC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
         }
         break;
@@ -5198 +5210 @@
             (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) {
           if      (r_read_fsm.read() == READ_TRT_LOCK)              r_alloc_trt_fsm = ALLOC_TRT_READ;
-          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
-                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
-          else if ((r_sc_fsm.read() == SC_TRT_GET_LOCK) ||
-                   (r_sc_fsm.read() == SC_TRT_PUT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
+          else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_BC_TRT_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) ||
+                   (r_sc_fsm.read() == SC_BC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
           else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
         }
@@ -5219 +5231 @@
     switch ( r_alloc_heap_fsm.read() ) 
     {
-
-      ////////////////////
-      case ALLOC_HEAP_READ:
+        ////////////////////
+        case ALLOC_HEAP_READ:
         if (  (r_read_fsm.read() != READ_HEAP_LOCK) &&
               (r_read_fsm.read() != READ_HEAP_ERASE)     ) 
         {
-          if        (r_write_fsm.read() == WRITE_HEAP_LOCK)         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
-          else if   (r_sc_fsm.read() == SC_HEAP_LOCK)             r_alloc_heap_fsm = ALLOC_HEAP_SC;
-          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
-          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          if      (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if (r_sc_fsm.read() == SC_UPT_HEAP_LOCK)              r_alloc_heap_fsm = ALLOC_HEAP_SC;
+          else if (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
         }
         break;
 
         /////////////////////
-      case ALLOC_HEAP_WRITE:
-        if (  (r_write_fsm.read() != WRITE_HEAP_LOCK)   &&
+        case ALLOC_HEAP_WRITE:
+        if (  (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)   &&
               (r_write_fsm.read() != WRITE_UPT_REQ)     &&
-              (r_write_fsm.read() != WRITE_UPDATE)  )
-        {
-          if        (r_sc_fsm.read() == SC_HEAP_LOCK)             r_alloc_heap_fsm = ALLOC_HEAP_SC;
-          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
-          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
-          else if   (r_read_fsm.read() == READ_HEAP_LOCK)               r_alloc_heap_fsm = ALLOC_HEAP_READ;
+              (r_write_fsm.read() != WRITE_UPT_NEXT)  )
+        {
+          if      (r_sc_fsm.read() == SC_UPT_HEAP_LOCK)          r_alloc_heap_fsm = ALLOC_HEAP_SC;
+          else if (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_HEAP_LOCK)              r_alloc_heap_fsm = ALLOC_HEAP_READ;
         }
         break;
 
         ////////////////////
-      case ALLOC_HEAP_SC:
-        if (  (r_sc_fsm.read() != SC_HEAP_LOCK)  &&
+        case ALLOC_HEAP_SC:
+        if (  (r_sc_fsm.read() != SC_UPT_HEAP_LOCK)  &&
               (r_sc_fsm.read() != SC_UPT_REQ )    &&
               (r_sc_fsm.read() != SC_UPT_NEXT)  )
         {
-          if      (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
-          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
-          else if (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
-          else if (r_write_fsm.read() == WRITE_HEAP_LOCK)         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          if      (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_HEAP_LOCK)          r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
         }
         break;
 
         ///////////////////////
-      case ALLOC_HEAP_CLEANUP:
+        case ALLOC_HEAP_CLEANUP:
         if ( (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) &&
             (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH)&&
             (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)    )
         {
-          if        (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
-          else if   (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
-          else if   (r_write_fsm.read() == WRITE_HEAP_LOCK)         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
-          else if   (r_sc_fsm.read() == SC_HEAP_LOCK)             r_alloc_heap_fsm = ALLOC_HEAP_SC;
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_HEAP_LOCK)          r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if (r_sc_fsm.read() == SC_UPT_HEAP_LOCK)          r_alloc_heap_fsm = ALLOC_HEAP_SC;
         }
         break;
         ////////////////////////
-      case ALLOC_HEAP_XRAM_RSP:
+        case ALLOC_HEAP_XRAM_RSP:
         if ( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE )
         {
-          if        (r_read_fsm.read() == READ_HEAP_LOCK)               r_alloc_heap_fsm = ALLOC_HEAP_READ;
-          else if   (r_write_fsm.read() == WRITE_HEAP_LOCK)         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
-          else if   (r_sc_fsm.read() == SC_HEAP_LOCK)             r_alloc_heap_fsm = ALLOC_HEAP_SC;
-          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          if        (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if   (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if   (r_sc_fsm.read() == SC_UPT_HEAP_LOCK)       r_alloc_heap_fsm = ALLOC_HEAP_SC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
         }
         break;