Ignore:
Timestamp:
Feb 21, 2012, 7:55:14 PM (13 years ago)
Author:
alain
Message:
 
Location:
trunk/modules/vci_mem_cache_v4/caba/source
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h

    r184 r200  
    1515
    1616  public:
    17   bool  valid;                // It is a valid pending transaction
    18   bool  update;               // It is an update transaction
    19   bool  brdcast;              // It is a broadcast invalidate
    20   bool  rsp;                  // It needs a response to the initiator
    21   size_t        srcid;        // The srcid of the initiator which wrote the data
    22   size_t        trdid;        // The trdid of the initiator which wrote the data
    23   size_t        pktid;        // The pktid of the initiator which wrote the data
    24   addr_t        nline;        // The identifier of the cache line
    25   size_t        count;        // The number of acknowledge responses to receive
     17  bool      valid;      // It is a valid pending transaction
     18  bool      update;     // It is an update transaction
     19  bool      brdcast;    // It is a broadcast invalidate
     20  bool      rsp;        // It needs a response to the initiator
     21  size_t        srcid;      // The srcid of the initiator which wrote the data
     22  size_t        trdid;      // The trdid of the initiator which wrote the data
     23  size_t        pktid;      // The pktid of the initiator which wrote the data
     24  addr_t        nline;      // The identifier of the cache line
     25  size_t        count;      // The number of acknowledge responses to receive
    2626
    2727  UpdateTabEntry(){
     
    4949    valid       = i_valid;
    5050    update      = i_update;
    51     brdcast     = i_brdcast;
    52     rsp         = i_rsp;
     51    brdcast = i_brdcast;
     52    rsp     = i_rsp;
    5353    srcid       = i_srcid;
    5454    trdid       = i_trdid;
  • trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

    r184 r200  
    146146        WRITE_NEXT,
    147147        WRITE_DIR_LOCK,
    148         WRITE_DIR_HIT_READ,
     148        WRITE_DIR_READ,
    149149        WRITE_DIR_HIT,
    150150        WRITE_UPT_LOCK,
    151         WRITE_HEAP_LOCK,
     151        WRITE_UPT_HEAP_LOCK,
    152152        WRITE_UPT_REQ,
    153         WRITE_UPDATE,
     153        WRITE_UPT_NEXT,
    154154        WRITE_UPT_DEC,
    155155        WRITE_RSP,
    156         WRITE_TRT_LOCK,
    157         WRITE_TRT_DATA,
    158         WRITE_TRT_SET,
     156        WRITE_MISS_TRT_LOCK,
     157        WRITE_MISS_TRT_DATA,
     158        WRITE_MISS_TRT_SET,
     159        WRITE_MISS_XRAM_REQ,
     160        WRITE_BC_TRT_LOCK,
     161        WRITE_BC_UPT_LOCK,
     162        WRITE_BC_DIR_INVAL,
     163        WRITE_BC_CC_SEND,
     164        WRITE_BC_XRAM_REQ,
    159165        WRITE_WAIT,
    160         WRITE_XRAM_REQ,
    161         WRITE_TRT_WRITE_LOCK,
    162         WRITE_INVAL_LOCK,
    163         WRITE_DIR_INVAL,
    164         WRITE_INVAL,
    165         WRITE_XRAM_SEND,
    166166      };
    167167
     
    211211        SC_DIR_HIT_WRITE,
    212212        SC_UPT_LOCK,
    213         SC_WAIT,
    214         SC_HEAP_LOCK,
     213        SC_UPT_HEAP_LOCK,
    215214        SC_UPT_REQ,
    216215        SC_UPT_NEXT,
    217         SC_TRT_PUT_LOCK,
    218         SC_INVAL_LOCK,
    219         SC_DIR_INVAL,
    220         SC_INVAL,
    221         SC_TRT_PUT_REQ,
     216        SC_BC_TRT_LOCK,
     217        SC_BC_UPT_LOCK,
     218        SC_BC_DIR_INVAL,
     219        SC_BC_CC_SEND,
     220        SC_BC_XRAM_REQ,
    222221        SC_RSP_FAIL,
    223222        SC_RSP_SUCCESS,
    224         SC_TRT_GET_LOCK,
    225         SC_TRT_GET_SET,
    226         SC_TRT_GET_REQ,
     223        SC_MISS_TRT_LOCK,
     224        SC_MISS_TRT_SET,
     225        SC_MISS_XRAM_REQ,
     226        SC_WAIT,
    227227      };
    228228
     
    473473      sc_signal<data_t>   *r_write_data;            // data (one cache line)   
    474474      sc_signal<be_t>     *r_write_be;              // one byte enable per word
    475       sc_signal<bool>      r_write_byte;            // is it a byte write
     475      sc_signal<bool>      r_write_byte;            // (BE != 0X0) and (BE != 0xF)
    476476      sc_signal<bool>      r_write_is_cnt;          // is_cnt bit (in directory)
    477477      sc_signal<bool>      r_write_lock;            // lock bit (in directory)
  • trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp

    r184 r200  
    4040#define DEBUG_MEMC_READ         1       // detailed trace of READ FSM
    4141#define DEBUG_MEMC_WRITE        1       // detailed trace of WRITE FSM 
    42 #define DEBUG_MEMC_SC           0       // detailed trace of SC FSM     
     42#define DEBUG_MEMC_SC           1       // detailed trace of SC FSM     
    4343#define DEBUG_MEMC_IXR_CMD      1       // detailed trace of IXR_RSP FSM
    4444#define DEBUG_MEMC_IXR_RSP      1       // detailed trace of IXR_RSP FSM
    4545#define DEBUG_MEMC_XRAM_RSP     1       // detailed trace of XRAM_RSP FSM       
    46 #define DEBUG_MEMC_INIT_CMD     0       // detailed trace of INIT_CMD FSM       
    47 #define DEBUG_MEMC_INIT_RSP     0       // detailed trace of INIT_RSP FSM       
     46#define DEBUG_MEMC_INIT_CMD     1       // detailed trace of INIT_CMD FSM       
     47#define DEBUG_MEMC_INIT_RSP     1       // detailed trace of INIT_RSP FSM       
    4848#define DEBUG_MEMC_TGT_CMD      0       // detailed trace of TGT_CMD FSM       
    4949#define DEBUG_MEMC_TGT_RSP      0       // detailed trace of TGT_RSP FSM       
     
    113113    "WRITE_NEXT",
    114114    "WRITE_DIR_LOCK",
    115     "WRITE_DIR_HIT_READ",
     115    "WRITE_DIR_READ",
    116116    "WRITE_DIR_HIT",
    117117    "WRITE_UPT_LOCK",
    118     "WRITE_HEAP_LOCK",
     118    "WRITE_UPT_HEAP_LOCK",
    119119    "WRITE_UPT_REQ",
    120     "WRITE_UPDATE",
     120    "WRITE_UPT_NEXT",
    121121    "WRITE_UPT_DEC",
    122122    "WRITE_RSP",
    123     "WRITE_TRT_LOCK",
    124     "WRITE_TRT_DATA",
    125     "WRITE_TRT_SET",
     123    "WRITE_MISS_TRT_LOCK",
     124    "WRITE_MISS_TRT_DATA",
     125    "WRITE_MISS_TRT_SET",
     126    "WRITE_MISS_XRAM_REQ",
     127    "WRITE_BC_TRT_LOCK",
     128    "WRITE_BC_UPT_LOCK",
     129    "WRITE_BC_DIR_INVAL",
     130    "WRITE_BC_CC_SEND",
     131    "WRITE_BC_XRAM_REQ",
    126132    "WRITE_WAIT",
    127     "WRITE_XRAM_REQ",
    128     "WRITE_TRT_WRITE_LOCK",
    129     "WRITE_INVAL_LOCK",
    130     "WRITE_DIR_INVAL",
    131     "WRITE_INVAL",
    132     "WRITE_XRAM_SEND",
    133133  };
    134134  const char *ixr_rsp_fsm_str[] = {
     
    170170    "SC_DIR_HIT_WRITE",
    171171    "SC_UPT_LOCK",
    172     "SC_WAIT",
    173     "SC_HEAP_LOCK",
     172    "SC_UPT_HEAP_LOCK",
    174173    "SC_UPT_REQ",
    175174    "SC_UPT_NEXT",
    176     "SC_TRT_PUT_LOCK",
    177     "SC_INVAL_LOCK",
    178     "SC_DIR_INVAL",
    179     "SC_INVAL",
    180     "SC_TRT_PUT_REQ",
     175    "SC_BC_TRT_LOCK",
     176    "SC_BC_UPT_LOCK",
     177    "SC_BC_DIR_INVAL",
     178    "SC_BC_CC_SEND",
     179    "SC_BC_XRAM_REQ",
    181180    "SC_RSP_FAIL",
    182181    "SC_RSP_SUCCESS",
    183     "SC_TRT_GET_LOCK",
    184     "SC_TRT_GET_SET",
    185     "SC_TRT_GET_REQ",
     182    "SC_MISS_TRT_LOCK",
     183    "SC_MISS_TRT_SET",
     184    "SC_MISS_XRAM_REQ",
     185    "SC_WAIT",
    186186  };
    187187  const char *cleanup_fsm_str[] = {
     
    289289
    290290    //  FIFOs
     291
    291292    m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
    292293    m_cmd_read_length_fifo("m_cmd_read_length_fifo", 4),
     
    316317
    317318    r_read_fsm("r_read_fsm"),
     319
    318320    r_write_fsm("r_write_fsm"),
     321
    319322    m_write_to_init_cmd_inst_fifo("m_write_to_init_cmd_inst_fifo",8),
    320323    m_write_to_init_cmd_srcid_fifo("m_write_to_init_cmd_srcid_fifo",8),
     
    322325    m_write_to_init_cmd_cache_id_fifo("m_write_to_init_cmd_cache_id_fifo",8),
    323326#endif
     327
    324328    r_init_rsp_fsm("r_init_rsp_fsm"),
    325329    r_cleanup_fsm("r_cleanup_fsm"),
     330
    326331    r_sc_fsm("r_sc_fsm"),
     332
    327333    m_sc_to_init_cmd_inst_fifo("m_sc_to_init_cmd_inst_fifo",8),
    328334    m_sc_to_init_cmd_srcid_fifo("m_sc_to_init_cmd_srcid_fifo",8),
     
    330336    m_sc_to_init_cmd_cache_id_fifo("m_sc_to_init_cmd_cache_id_fifo",8),
    331337#endif
     338
    332339    r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
    333340    r_xram_rsp_fsm("r_xram_rsp_fsm"),
     341
    334342    m_xram_rsp_to_init_cmd_inst_fifo("m_xram_rsp_to_init_cmd_inst_fifo",8),
    335343    m_xram_rsp_to_init_cmd_srcid_fifo("m_xram_rsp_to_init_cmd_srcid_fifo",8),
     
    337345    m_xram_rsp_to_init_cmd_cache_id_fifo("m_xram_rsp_to_init_cmd_cache_id_fifo",8),
    338346#endif
     347
    339348    r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
     349
    340350    r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
     351
    341352    r_init_cmd_fsm("r_init_cmd_fsm"),
     353
    342354    r_alloc_dir_fsm("r_alloc_dir_fsm"),
    343355    r_alloc_trt_fsm("r_alloc_trt_fsm"),
    344356    r_alloc_upt_fsm("r_alloc_upt_fsm")
     357
    345358    {
    346359      assert(IS_POW_OF_2(nsets));
     
    879892    /////////////////////////////////////////////////////////////////////////
    880893    // This FSM controls the response to the update or inval coherence
    881     // requests sent by the memory cache to the L1 caches :
    882     //
     894    // requests sent by the memory cache to the L1 caches and update the UPT.
     895    // 
    883896    // It can be update or inval requests initiated by the WRITE FSM,
    884897    // or inval requests initiated by the XRAM_RSP FSM. 
     898    // It can also be a direct request from the WRITE FSM.
     899    //
    885900    // The FSM decrements the proper entry in UPT.
    886901    // It sends a request to the TGT_RSP FSM to complete the pending
     
    912927                {
    913928                    std::cout << "VCI_MEM_CACHE ERROR " << name()
    914                               << " INIT_RSP_IDLE state" << std::endl;
    915                     std::cout << "index too large for UPT: "
     929                              << " INIT_RSP_IDLE state" << std::endl
     930                              << "index too large for UPT: "
    916931                              << " / rtrdid = " << p_vci_ini.rtrdid.read()
    917932                              << " / UPT size = " << m_update_tab.size() << std::endl;
     
    955970                if ( not valid )
    956971                {
    957                     std::cout << "VCI_MEM_CACHE ERROR " << name() << " INIT_RSP_UPT_LOCK state" << std::endl;
    958                     std::cout << "unsuccessful access to decrement the UPT" << std::endl;
     972                    std::cout << "VCI_MEM_CACHE ERROR " << name()
     973                              << " INIT_RSP_UPT_LOCK state" << std::endl
     974                              << "unsuccessful access to decrement the UPT" << std::endl;
    959975                    exit(0);
    960976                }
     
    15111527    //   If the UPT is full, it releases the lock(s) and retry. Then, it sends
    15121528    //   a multi-update request to all owners of the line (but the writer),
    1513     //   through the INIT_CMD FSM. In case of multi-update transaction, the WRITE FSM
     1529    //   through the INIT_CMD FSM. In case of coherence transaction, the WRITE FSM
    15141530    //   does not respond to the writing processor, as this response will be sent by
    15151531    //   the INIT_RSP FSM when all update responses have been received.
     
    16351651                    if( entry.is_cnt && entry.count )
    16361652                    {
    1637                         r_write_fsm      = WRITE_DIR_HIT_READ;
     1653                        r_write_fsm      = WRITE_DIR_READ;
    16381654                    }
    16391655                    else
    16401656                    {
    1641                         if (r_write_byte.read())        r_write_fsm = WRITE_DIR_HIT_READ;
     1657                        if (r_write_byte.read())        r_write_fsm = WRITE_DIR_READ;
    16421658                        else                                    r_write_fsm = WRITE_DIR_HIT;
    16431659                    }
     
    16451661                else    // miss
    16461662                {
    1647                     r_write_fsm = WRITE_TRT_LOCK;
     1663                    r_write_fsm = WRITE_MISS_TRT_LOCK;
    16481664                }
    16491665
     
    16521668{
    16531669    std::cout << "  <MEMC.WRITE_DIR_LOCK> Check the directory: "
    1654               << " address = " << r_write_address.read()
     1670              << " address = " << std::hex << r_write_address.read()
    16551671              << " hit = " << entry.valid
    16561672              << " count = " << std::dec << entry.count
     
    16611677            break;
    16621678        }
    1663         ////////////////////////
    1664         case WRITE_DIR_HIT_READ:        // read the cache and complete the buffer when be!=0xF
     1679        ////////////////////
     1680        case WRITE_DIR_READ:    // read the cache and complete the buffer when be!=0xF
    16651681        {
    16661682            // update local buffer
     
    16841700
    16851701            // test if a coherence broadcast is required
    1686             if( r_write_is_cnt.read() && r_write_count.read() ) r_write_fsm = WRITE_TRT_WRITE_LOCK;
    1687             else                                                r_write_fsm = WRITE_DIR_HIT;
     1702            if( r_write_is_cnt.read() && r_write_count.read() ) r_write_fsm = WRITE_BC_TRT_LOCK;
     1703            else                                                                        r_write_fsm = WRITE_DIR_HIT;
    16881704
    16891705#if DEBUG_MEMC_WRITE
     
    16921708    if( r_write_is_cnt.read() && r_write_count.read() )
    16931709    {
    1694         std::cout << "  <MEMC.WRITE_DIR_HIT_READ> Read the cache to complete local buffer /"
     1710        std::cout << "  <MEMC.WRITE_DIR_READ> Read the cache to complete local buffer /"
    16951711                  << " coherence broadcast required" << std::endl;
    16961712    }
    16971713    else
    16981714    {
    1699         std::cout << "  <MEMC.WRITE_DIR_HIT_READ> Read the cache to complete local buffer"
     1715        std::cout << "  <MEMC.WRITE_DIR_READ> Read the cache to complete local buffer"
    17001716                  << std::endl;
    17011717    }
     
    17051721        }
    17061722        ///////////////////
    1707         case WRITE_DIR_HIT:        // update the cache (data & directory)
     1723        case WRITE_DIR_HIT:        // update the cache directory
    17081724        {
    17091725            // update directory with Dirty bit
     
    17271743            m_cache_directory.write(set, way, entry);
    17281744
    1729             // owner is true when the writer is the owner
     1745            // owner is true when the  the first registered copy is the writer itself
    17301746            bool owner = (((r_write_copy.read() == r_write_srcid.read())
    17311747#if L1_MULTI_CACHE
     
    17371753            bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1));
    17381754
    1739             // write data in the cache if no transaction on the coherence network
     1755            // write data in the cache if no coherence transaction
    17401756            if( no_update )
    17411757            {
     
    17471763
    17481764            if ( owner )   r_write_count = r_write_count.read() - 1;
    1749             r_write_to_dec = false;
    17501765
    17511766            if ( no_update )      // Write transaction completed
     
    17571772                if( !r_write_to_init_cmd_multi_req.read() &&
    17581773                   !r_write_to_init_cmd_brdcast_req.read()  )   r_write_fsm = WRITE_UPT_LOCK;
    1759                 else                                            r_write_fsm = WRITE_WAIT;
     1774                else                                                                r_write_fsm = WRITE_WAIT;
    17601775            }
    17611776
     
    17791794            break;
    17801795        }
    1781         /////////////////////
     1796        ////////////////////
    17821797        case WRITE_UPT_LOCK:    // Try to register the update request in UPT
    17831798        {
     
    18181833        std::cout << "  <MEMC.WRITE_UPT_LOCK> Register the multicast update in UPT / "
    18191834                  << " nb_copies = " << r_write_count.read() << std::endl;
    1820         //m_update_tab.print();
    18211835    }
    18221836}
    18231837#endif
    18241838                r_write_upt_index = index;
    1825                 //  releases the lock protecting the Update Table and the Directory if no entry...
    1826                 if ( wok ) r_write_fsm = WRITE_HEAP_LOCK;
     1839                //  releases the lock protecting UPT and the DIR if no entry...
     1840                if ( wok ) r_write_fsm = WRITE_UPT_HEAP_LOCK;
    18271841                else       r_write_fsm = WRITE_WAIT;
    18281842            }
     
    18301844        }
    18311845        /////////////////////
    1832         case WRITE_HEAP_LOCK:
     1846        case WRITE_UPT_HEAP_LOCK:   // get access to heap
    18331847        {
    18341848            if( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE )
     
    18381852if( m_debug_write_fsm )
    18391853{
    1840     std::cout << "  <MEMC.WRITE_HEAP_LOCK> Get acces to the HEAP" << std::endl;
     1854    std::cout << "  <MEMC.WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
    18411855}
    18421856#endif
     
    18461860        }
    18471861        //////////////////
    1848         case WRITE_UPT_REQ:
    1849         {
    1850             if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_WRITE )
    1851             {
    1852                 std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_REQ state" << std::endl;
    1853                 std::cout << "bad HEAP allocation" << std::endl;
    1854                 exit(0);
    1855             }
    1856 
     1862        case WRITE_UPT_REQ:     //  prepare the request to INIT_CMD FSM
     1863                                //  and write the first srcid in the FIFO
     1864                                //  send the request if only one copy
     1865        {
    18571866            if( !r_write_to_init_cmd_multi_req.read() &&
    1858                 !r_write_to_init_cmd_brdcast_req.read()  )
     1867                !r_write_to_init_cmd_brdcast_req.read()  )  // no pending coherence request
    18591868            {
    18601869                r_write_to_init_cmd_brdcast_req  = false;
     
    18641873                r_write_to_init_cmd_count        = r_write_word_count.read();
    18651874
    1866                 for(size_t i=0; i<m_words ; i++)
    1867                 {
    1868                     r_write_to_init_cmd_be[i]=r_write_be[i].read();
    1869                 }
     1875                for(size_t i=0; i<m_words ; i++) r_write_to_init_cmd_be[i]=r_write_be[i].read();
    18701876
    18711877                size_t min = r_write_word_index.read();
    18721878                size_t max = r_write_word_index.read() + r_write_word_count.read();
    1873                 for (size_t i=min ; i<max ; i++)  r_write_to_init_cmd_data[i] = r_write_data[i];
     1879                for (size_t i=min ; i<max ; i++) r_write_to_init_cmd_data[i] = r_write_data[i];
    18741880           
    18751881                if( (r_write_copy.read() != r_write_srcid.read()) or
     
    18791885                    r_write_copy_inst.read() )
    18801886                {
    1881                     // We put the first copy in the fifo
     1887                    // put the first srcid in the fifo
    18821888                    write_to_init_cmd_fifo_put     = true;
    18831889                    write_to_init_cmd_fifo_inst    = r_write_copy_inst.read();
     
    18931899                    else
    18941900                    {
    1895                         r_write_fsm = WRITE_UPDATE;
     1901                        r_write_fsm = WRITE_UPT_NEXT;
     1902                        r_write_to_dec = false;
     1903
    18961904                    }
    18971905                }
    18981906                else
    18991907                {
    1900                     r_write_fsm = WRITE_UPDATE;
    1901                 }
    1902             }
    1903             break;
    1904         }
    1905         //////////////////
    1906         case WRITE_UPDATE:      // send a multi-update request to INIT_CMD fsm
    1907         {
    1908             if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_WRITE )
    1909             {
    1910                 std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPDATE state" << std::endl;
    1911                 std::cout << "bad HEAP allocation" << std::endl;
    1912                 exit(0);
    1913             }
    1914 
     1908                    r_write_fsm = WRITE_UPT_NEXT;
     1909                    r_write_to_dec = false;
     1910                }
     1911            }
     1912            break;
     1913        }
     1914        ///////////////////
     1915        case WRITE_UPT_NEXT:    // continue the multi-update request to INIT_CMD fsm
     1916                                // when there is copies in the heap.
     1917                                // if one copy in the heap is the writer itself
     1918                                // the corresponding SRCID should not be written in the fifo,
     1919                                // but the UPT counter must be decremented.
     1920                                // As this decrement is done in the WRITE_UPT_DEC state,
     1921                                // after the last copy has been found, the decrement request
     1922                                // must be  registered in the r_write_to_dec flip-flop.
     1923        {
    19151924            HeapEntry entry = m_heap.read(r_write_ptr.read());
    1916             write_to_init_cmd_fifo_inst     = entry.owner.inst;
    1917             write_to_init_cmd_fifo_srcid    = entry.owner.srcid;
    1918 #if L1_MULTI_CACHE
    1919             write_to_init_cmd_fifo_cache_id = entry.owner.cache_id;
    1920 #endif
    19211925         
    1922             bool dec_upt_counter = r_write_to_dec.read();
     1926            bool dec_upt_counter; // = r_write_to_dec.read();
     1927
    19231928            if( (entry.owner.srcid != r_write_srcid.read()) or
    19241929#if L1_MULTI_CACHE
    19251930                (entry.owner.cache_id != r_write_pktid.read()) or
    19261931#endif
    1927                 entry.owner.inst)
    1928             {
    1929                 write_to_init_cmd_fifo_put = true;
     1932                entry.owner.inst)   // put te next srcid in the fifo
     1933            {
     1934                dec_upt_counter                 = false;
     1935                write_to_init_cmd_fifo_put      = true;
     1936                write_to_init_cmd_fifo_inst     = entry.owner.inst;
     1937                write_to_init_cmd_fifo_srcid    = entry.owner.srcid;
     1938#if L1_MULTI_CACHE
     1939                write_to_init_cmd_fifo_cache_id = entry.owner.cache_id;
     1940#endif
    19301941            }
    1931             else
     1942            else                    // the UPT counter must be decremented
    19321943            {
    19331944                dec_upt_counter = true;
    19341945            }
    1935             r_write_to_dec = dec_upt_counter;
    1936 
    1937             if( m_write_to_init_cmd_inst_fifo.wok() )
    1938             {
    1939                 r_write_ptr = entry.next;
    1940                 if( entry.next == r_write_ptr.read() )  // last copy
    1941                 {
    1942                     r_write_to_init_cmd_multi_req = true;
    1943                     if(dec_upt_counter) r_write_fsm = WRITE_UPT_DEC;
    1944                     else                r_write_fsm = WRITE_IDLE;
    1945                 }
    1946                 else
    1947                 {
    1948                     r_write_fsm = WRITE_UPDATE;
    1949                 }
     1946
     1947            // register the possible UPT decrement request
     1948            r_write_to_dec = dec_upt_counter or r_write_to_dec.read();
     1949
     1950            if( not m_write_to_init_cmd_inst_fifo.wok() )
     1951            {
     1952                std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl
     1953                          << "The write_to_cmd_write_fifo should not be full" << std::endl
     1954                          << "as the depth should be larger than the max number of copies" << std::endl;
     1955                exit(0);
     1956            }
     1957
     1958            r_write_ptr = entry.next;
     1959
     1960            if( entry.next == r_write_ptr.read() )  // last copy
     1961            {
     1962                r_write_to_init_cmd_multi_req = true;
     1963                if( r_write_to_dec.read() or dec_upt_counter)   r_write_fsm = WRITE_UPT_DEC;
     1964                else                                                r_write_fsm = WRITE_IDLE;
    19501965            }
    1951             else
    1952             {
    1953                 r_write_fsm = WRITE_UPDATE;
    1954             }
    19551966            break;
    19561967        }
    19571968        //////////////////
    1958         case WRITE_UPT_DEC:     // Post another coherence update request
     1969        case WRITE_UPT_DEC:     // If the initial writer has a copy, it should not
     1970                                // receive an update request, but the counter in the
     1971                                // update table must be decremented by the INIT_RSP FSM.
    19591972        {
    19601973            if ( !r_write_to_init_rsp_req.read() )
     
    19831996                r_write_to_tgt_rsp_trdid = r_write_trdid.read();
    19841997                r_write_to_tgt_rsp_pktid = r_write_pktid.read();
    1985                 r_write_fsm             = WRITE_IDLE;
    1986             }
    1987             break;
    1988         }
    1989         ////////////////////
    1990         case WRITE_TRT_LOCK:    // Miss : check Transaction Table
     1998                r_write_fsm             = WRITE_IDLE;
     1999            }
     2000            break;
     2001        }
     2002        /////////////////////////
     2003        case WRITE_MISS_TRT_LOCK:       // Miss : check Transaction Table
    19912004        {
    19922005            if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE )
     
    19962009if( m_debug_write_fsm )
    19972010{
    1998     std::cout << "  <MEMC.WRITE_TRT_LOCK> Check the TRT" << std::endl;
     2011    std::cout << "  <MEMC.WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
    19992012}
    20002013#endif
     
    20092022                {
    20102023                    r_write_trt_index = hit_index;
    2011                     r_write_fsm       = WRITE_TRT_DATA;
     2024                    r_write_fsm       = WRITE_MISS_TRT_DATA;
    20122025                    m_cpt_write_miss++;
    20132026                }
     
    20152028                {
    20162029                    r_write_trt_index = wok_index;
    2017                     r_write_fsm       = WRITE_TRT_SET;
     2030                    r_write_fsm       = WRITE_MISS_TRT_SET;
    20182031                    m_cpt_write_miss++;
    20192032                }
     
    20392052            break;
    20402053        }
    2041         ///////////////////
    2042         case WRITE_TRT_SET:     // register a new transaction in TRT (Write Buffer)
     2054        ////////////////////////
     2055        case WRITE_MISS_TRT_SET:        // register a new transaction in TRT (Write Buffer)
    20432056        { 
    20442057            if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE )
     
    20642077                                      be_vector,
    20652078                                      data_vector);
    2066                 r_write_fsm = WRITE_XRAM_REQ;
     2079                r_write_fsm = WRITE_MISS_XRAM_REQ;
    20672080
    20682081#if DEBUG_MEMC_WRITE
    20692082if( m_debug_write_fsm )
    20702083{
    2071     std::cout << "  <MEMC.WRITE_TRT_SET> Set a new entry in TRT" << std::endl;
     2084    std::cout << "  <MEMC.WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
    20722085}
    20732086#endif
     
    20752088            break;
    20762089        } 
    2077         ////////////////////
    2078         case WRITE_TRT_DATA:    // update an entry in TRT (Write Buffer)
     2090        /////////////////////////
     2091        case WRITE_MISS_TRT_DATA:       // update an entry in TRT (used as a Write Buffer)
    20792092        {
    20802093            if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE )
     
    20972110if( m_debug_write_fsm )
    20982111{
    2099     std::cout << "  <MEMC.WRITE_TRT_DATA> Modify an existing entry in TRT" << std::endl;
     2112    std::cout << "  <MEMC.WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
    21002113    m_transaction_tab.print( r_write_trt_index.read() );
    21012114}
     
    21042117            break;
    21052118        }
    2106         ////////////////////
    2107         case WRITE_XRAM_REQ:    // send a request to IXR_CMD FSM
     2119        /////////////////////////
     2120        case WRITE_MISS_XRAM_REQ:       // send a GET request to IXR_CMD FSM
    21082121        { 
    21092122            if ( !r_write_to_ixr_cmd_req )
     
    21182131if( m_debug_write_fsm )
    21192132{
    2120     std::cout << "  <MEMC.WRITE_XRAM_REQ> Post a request to the IXR_CMD FSM" << std::endl;
    2121 }
    2122 #endif
    2123             }
    2124             break;
    2125         }
    2126         //////////////////////////
    2127         case WRITE_TRT_WRITE_LOCK:      // Check TRT not full
     2133    std::cout << "  <MEMC.WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
     2134}
     2135#endif
     2136            }
     2137            break;
     2138        }
     2139        ///////////////////////
     2140        case WRITE_BC_TRT_LOCK:     // Check TRT not full
    21282141        {
    21292142            if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE )
     
    21342147                {
    21352148                    r_write_trt_index = wok_index;
    2136                     r_write_fsm       = WRITE_INVAL_LOCK;
     2149                    r_write_fsm       = WRITE_BC_UPT_LOCK;
    21372150                }
    21382151                else    // wait an empty entry in TRT
     
    21442157if( m_debug_write_fsm )
    21452158{
    2146     std::cout << "  <MEMC.WRITE_TRT_WRITE_LOCK> Check TRT : wok = "
    2147               << wok << " index = " << wok_index << std::endl;
     2159    std::cout << "  <MEMC.WRITE_BC_TRT_LOCK> Check TRT : wok = "
     2160              << wok << " / index = " << wok_index << std::endl;
    21482161}
    21492162#endif
     
    21522165        }
    21532166        //////////////////////
    2154         case WRITE_INVAL_LOCK:
     2167        case WRITE_BC_UPT_LOCK:      // register BC transaction in UPT
    21552168        {
    21562169            if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE )
     
    21792192    if ( wok )
    21802193    {
    2181         std::cout << "  <MEMC.WRITE_INVAL_LOCK> Register the broadcast inval in UPT / "
     2194        std::cout << "  <MEMC.WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "
    21822195                  << " nb_copies = " << r_write_count.read() << std::endl;
    2183         //m_update_tab.print();
    21842196    }
    21852197}
     
    21872199                r_write_upt_index = index;
    21882200
    2189                 if ( wok ) r_write_fsm = WRITE_DIR_INVAL;
     2201                if ( wok ) r_write_fsm = WRITE_BC_DIR_INVAL;
    21902202                else       r_write_fsm = WRITE_WAIT;
    21912203            }
    21922204            break;
    21932205        }
    2194         /////////////////////
    2195         case WRITE_DIR_INVAL:   // Register a put transaction to XRAM in TRT
     2206        ////////////////////////
     2207        case WRITE_BC_DIR_INVAL:        // Register a put transaction to XRAM in TRT
    21962208                                // and invalidate the line in directory
    21972209        {
     
    22002212                 (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) )
    22012213            {
    2202                 std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_DIR_INVAL state" << std::endl;
     2214                std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl;
    22032215                std::cout << "bad TRT, DIR, or UPT allocation" << std::endl;
    22042216                exit(0);
     
    22392251if( m_debug_write_fsm )
    22402252{
    2241     std::cout << "  <MEMC.WRITE_DIR_INVAL> Invalidate the directory entry: @ = "
     2253    std::cout << "  <MEMC.WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
    22422254              << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
    22432255}
    22442256#endif
    2245             r_write_fsm = WRITE_INVAL;
    2246             break;
    2247         }
    2248         /////////////////
    2249         case WRITE_INVAL:    // Post a coherence broadcast request to INIT_CMD FSM
     2257            r_write_fsm = WRITE_BC_CC_SEND;
     2258            break;
     2259        }
     2260        //////////////////////
     2261        case WRITE_BC_CC_SEND:    // Post a coherence broadcast request to INIT_CMD FSM
    22502262        {
    22512263            if ( !r_write_to_init_cmd_multi_req.read() && !r_write_to_init_cmd_brdcast_req.read() )
     
    22632275                    r_write_to_init_cmd_data[i] = 0;
    22642276                }
    2265                 r_write_fsm = WRITE_XRAM_SEND;
     2277                r_write_fsm = WRITE_BC_XRAM_REQ;
    22662278
    22672279#if DEBUG_MEMC_WRITE
    22682280if( m_debug_write_fsm )
    22692281{
    2270     std::cout << "  <MEMC.WRITE_INVAL> Post a broadcast request to INIT_CMD FSM" << std::endl;
    2271 }
    2272 #endif
    2273             }
    2274             break;
    2275         }
    2276         /////////////////////
    2277         case WRITE_XRAM_SEND:   // Post a put request to IXR_CMD FSM
     2282    std::cout << "  <MEMC.WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl;
     2283}
     2284#endif
     2285            }
     2286            break;
     2287        }
     2288        ///////////////////////
     2289        case WRITE_BC_XRAM_REQ:   // Post a put request to IXR_CMD FSM
    22782290        {
    22792291            if ( !r_write_to_ixr_cmd_req )
     
    22912303if( m_debug_write_fsm )
    22922304{
    2293     std::cout << "  <MEMC.WRITE_XRAM_SEND> Post a put request to IXR_CMD FSM" << std::endl;
     2305    std::cout << "  <MEMC.WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
    22942306}
    22952307#endif
     
    23032315    ///////////////////////////////////////////////////////////////////////
    23042316    // The IXR_CMD fsm controls the command packets to the XRAM :
    2305     // - It sends a single cell VCI get request to the XRAM in case of MISS
     2317    // - It sends a single cell VCI read request to the XRAM in case of MISS
    23062318    // posted by the READ, WRITE or SC FSMs : the TRDID field contains
    23072319    // the Transaction Tab index.
     
    23452357        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
    23462358        break;
    2347         /////////////////////////
     2359        /////////////////////////       // send a get request to XRAM
    23482360        case IXR_CMD_READ_NLINE:
    23492361        if ( p_vci_ixr.cmdack )
     
    23552367if( m_debug_ixr_cmd_fsm )
    23562368{
    2357     std::cout << "  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram" ;
     2369    std::cout << "  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
    23582370}
    23592371#endif
     
    23612373        break;
    23622374        //////////////////////////
    2363         case IXR_CMD_WRITE_NLINE:       
     2375        case IXR_CMD_WRITE_NLINE:           // send a put or get command to XRAM
    23642376        if ( p_vci_ixr.cmdack )
    23652377        {
     
    23802392if( m_debug_ixr_cmd_fsm )
    23812393{
    2382     std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a put request to xram" ;
     2394    std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
    23832395}
    23842396#endif
     
    23922404if( m_debug_ixr_cmd_fsm )
    23932405{
    2394     std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a get request to xram" ;
     2406    std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
    23952407}
    23962408#endif
     
    23992411        break;
    24002412        //////////////////////
    2401         case IXR_CMD_SC_NLINE:
     2413        case IXR_CMD_SC_NLINE:      // send a put or get command to XRAM
    24022414        if ( p_vci_ixr.cmdack )
    24032415        {
     
    24182430if( m_debug_ixr_cmd_fsm )
    24192431{
    2420     std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a put request to xram" ;
     2432    std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a put request to xram" << std::endl;
    24212433}
    24222434#endif
     
    24302442if( m_debug_ixr_cmd_fsm )
    24312443{
    2432     std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a get request to xram" ;
     2444    std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a get request to xram" << std::endl;
    24332445}
    24342446#endif
     
    24372449        break;
    24382450        ////////////////////////
    2439         case IXR_CMD_XRAM_DATA:
     2451        case IXR_CMD_XRAM_DATA:     // send a put command to XRAM
    24402452        if ( p_vci_ixr.cmdack )
    24412453        {
     
    24542466if( m_debug_ixr_cmd_fsm )
    24552467{
    2456     std::cout << "  <MEMC.IXR_CMD_XRAM_DATA> Send a put request to xram" ;
     2468    std::cout << "  <MEMC.IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
    24572469}
    24582470#endif
     
    24832495    switch ( r_ixr_rsp_fsm.read() )
    24842496    {
    2485         ///////////////////
     2497        //////////////////
    24862498        case IXR_RSP_IDLE:      // test if it's a get or a put transaction
    24872499        {
     
    37513763
    37523764                if ( entry.valid )      r_sc_fsm = SC_DIR_HIT_READ;
    3753                 else                    r_sc_fsm = SC_TRT_GET_LOCK;
     3765                else                        r_sc_fsm = SC_MISS_TRT_LOCK;
    37543766
    37553767#if DEBUG_MEMC_SC
     
    38203832            break;
    38213833        }
    3822         ///// ////////////////
     3834        //////////////////////
    38233835        case SC_DIR_HIT_WRITE:          // write data in the cache
    38243836                                    // and test if a coherence request is required
     
    38383850                if ( r_sc_is_cnt.read() )
    38393851                {
    3840                     r_sc_fsm = SC_TRT_PUT_LOCK;                 // broadcast invalidate required
     3852                    r_sc_fsm = SC_BC_TRT_LOCK;          // broadcast invalidate required
    38413853                }
    38423854                else if( !r_sc_to_init_cmd_multi_req.read() &&
     
    38933905                {
    38943906                    r_sc_upt_index = index;
    3895                     r_sc_fsm = SC_HEAP_LOCK;
     3907                    r_sc_fsm = SC_UPT_HEAP_LOCK;
    38963908                }
    38973909                else       //  releases the locks protecting UPT and DIR if no entry
     
    39263938        }
    39273939        //////////////////
    3928         case SC_HEAP_LOCK:      // lock the heap
     3940        case SC_UPT_HEAP_LOCK:  // lock the heap
    39293941        {
    39303942            if( r_alloc_heap_fsm.read() == ALLOC_HEAP_SC )
     
    39343946if( m_debug_sc_fsm )
    39353947{
    3936     std::cout << "  <MEMC.SC_HEAP_LOCK> Get access to the heap" << std::endl;
     3948    std::cout << "  <MEMC.SC_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
    39373949}
    39383950#endif
     
    40394051        }
    40404052        /////////////////////
    4041         case SC_TRT_PUT_LOCK:           // check the TRT to register a PUT transaction     
     4053        case SC_BC_TRT_LOCK:            // check the TRT to register a PUT transaction     
    40424054        {
    40434055            if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC )
     
    40694081                    {
    40704082                        r_sc_trt_index = wok_index;
    4071                         r_sc_fsm       = SC_INVAL_LOCK;
     4083                        r_sc_fsm       = SC_BC_UPT_LOCK;
    40724084                    }
    40734085                    else
     
    40844096        }
    40854097        ///////////////////
    4086         case SC_INVAL_LOCK:  // Register a broadcast inval transaction in UPT
     4098        case SC_BC_UPT_LOCK:  // Register a broadcast inval transaction in UPT
    40874099        {
    40884100            if ( r_alloc_upt_fsm.read() == ALLOC_UPT_SC )
     
    41104122                {
    41114123                    r_sc_upt_index = index;
    4112                     r_sc_fsm = SC_DIR_INVAL;
     4124                    r_sc_fsm = SC_BC_DIR_INVAL;
    41134125#if DEBUG_MEMC_SC
    41144126if( m_debug_sc_fsm )
    41154127{
    4116     std::cout << "  <MEMC.SC_INVAL_LOCK> Register a broadcast inval transaction in UPT"
     4128    std::cout << "  <MEMC.SC_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
    41174129              << " / nline = " << nline
    41184130              << " / count = " << nb_copies
     
    41294141        }
    41304142        //////////////////
    4131         case SC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
     4143        case SC_BC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
    41324144        {
    41334145            if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) &&
     
    41664178                m_cache_directory.write(set, way, entry);
    41674179
    4168                 r_sc_fsm = SC_INVAL;
     4180                r_sc_fsm = SC_BC_CC_SEND;
    41694181
    41704182#if DEBUG_MEMC_SC
    41714183if( m_debug_sc_fsm )
    41724184{
    4173     std::cout << "  <MEMC.SC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
     4185    std::cout << "  <MEMC.SC_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
    41744186              << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]
    41754187              << " / set = " << std::dec << set << " / way = " << way << std::endl;
     
    41794191            else
    41804192            {
    4181                 assert(false and "LOCK ERROR in SC_FSM, STATE = SC_DIR_INVAL");
    4182             }
    4183             break;
    4184         }
    4185         //////////////
    4186         case SC_INVAL:  // Request the broadcast inval to INIT_CMD FSM
     4193                assert(false and "LOCK ERROR in SC_FSM, STATE = SC_BC_DIR_INVAL");
     4194            }
     4195            break;
     4196        }
     4197        ///////////////////
     4198        case SC_BC_CC_SEND:  // Request the broadcast inval to INIT_CMD FSM
    41874199        {
    41884200            if ( !r_sc_to_init_cmd_multi_req.read() &&
     
    41964208                r_sc_to_init_cmd_wdata        = 0;
    41974209
    4198                 r_sc_fsm = SC_TRT_PUT_REQ;
     4210                r_sc_fsm = SC_BC_XRAM_REQ;
    41994211            }
    42004212            break;
    42014213        }
    42024214        ////////////////////
    4203         case SC_TRT_PUT_REQ: // request the IXR FSM to start a put transaction
     4215        case SC_BC_XRAM_REQ: // request the IXR FSM to start a put transaction
    42044216        {
    42054217            if ( !r_sc_to_ixr_cmd_req )
     
    42164228if( m_debug_sc_fsm )
    42174229{
    4218     std::cout << "  <MEMC.SC_TRT_PUT_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
     4230    std::cout << "  <MEMC.SC_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
    42194231              << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
    42204232              << " / trt_index = " << r_sc_trt_index.read() << std::endl;
     
    42244236            else
    42254237            {
    4226                std::cout << "MEM_CACHE, SC_TRT_PUT_REQ state : request should not have been previously set"
     4238               std::cout << "MEM_CACHE, SC_BC_XRAM_REQ state : request should not have been previously set"
    42274239                         << std::endl;
    42284240            }
     
    42764288        }
    42774289        /////////////////////
    4278         case SC_TRT_GET_LOCK:         // cache miss : request access to transaction Table
     4290        case SC_MISS_TRT_LOCK:         // cache miss : request access to transaction Table
    42794291        {
    42804292            if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC )
     
    42904302if( m_debug_sc_fsm )
    42914303{
    4292     std::cout << "  <MEMC.SC_TRT_GET_LOCK> Check TRT state"
     4304    std::cout << "  <MEMC.SC_MISS_TRT_LOCK> Check TRT state"
    42934305              << " / hit_read = "  << hit_read
    42944306              << " / hit_write = " << hit_write
     
    43054317                {
    43064318                    r_sc_trt_index = index;
    4307                     r_sc_fsm       = SC_TRT_GET_SET;
     4319                    r_sc_fsm       = SC_MISS_TRT_SET;
    43084320                }
    43094321            }
     
    43114323        }
    43124324        ////////////////////
    4313         case SC_TRT_GET_SET:    // register the GET transaction in TRT
     4325        case SC_MISS_TRT_SET:   // register the GET transaction in TRT
    43144326        {
    43154327            if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC )
     
    43364348                                      be_vector,
    43374349                                      data_vector);
    4338                 r_sc_fsm = SC_TRT_GET_REQ;       
     4350                r_sc_fsm = SC_MISS_XRAM_REQ;       
    43394351
    43404352#if DEBUG_MEMC_SC
    43414353if( m_debug_sc_fsm )
    43424354{
    4343     std::cout << "  <MEMC.SC_TRT_GET_SET> Register a GET transaction in TRT" << std::hex
     4355    std::cout << "  <MEMC.SC_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
    43444356              << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
    43454357              << " / trt_index = " << r_sc_trt_index.read() << std::endl;
     
    43494361            break;
    43504362        }
    4351         ////////////////////
    4352         case SC_TRT_GET_REQ:    // request the IXR_CMD FSM to fetch the missing line
     4363        //////////////////////
     4364        case SC_MISS_XRAM_REQ:  // request the IXR_CMD FSM to fetch the missing line
    43534365        {
    43544366            if ( !r_sc_to_ixr_cmd_req )
     
    43634375if( m_debug_sc_fsm )
    43644376{
    4365     std::cout << "  <MEMC.SC_TRT_GET_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
     4377    std::cout << "  <MEMC.SC_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
    43664378              << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
    43674379              << " / trt_index = " << r_sc_trt_index.read() << std::endl;
     
    43774389    //          INIT_CMD FSM
    43784390    //////////////////////////////////////////////////////////////////////////////
    4379     // The INIT_CMD fsm controls the VCI CMD initiator port, used to update
    4380     // or invalidate cache lines in L1 caches.
     4391    // The INIT_CMD fsm controls the VCI CMD initiator port on the coherence
     4392    // network, used to update or invalidate cache lines in L1 caches.
    43814393    //
    43824394    // It implements a round-robin priority between the three possible client FSMs
     
    49594971        {
    49604972          if      ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
    4961                    (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
     4973                   (r_write_fsm.read() == WRITE_BC_UPT_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
    49624974          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
    49634975          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
    49644976          else if ((r_sc_fsm.read() == SC_UPT_LOCK) ||
    4965                    (r_sc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
     4977                   (r_sc_fsm.read() == SC_BC_UPT_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
    49664978        }
    49674979        break;
     
    49704982      case ALLOC_UPT_WRITE:
    49714983        if ( (r_write_fsm.read() != WRITE_UPT_LOCK) &&
    4972              (r_write_fsm.read() != WRITE_INVAL_LOCK))
     4984             (r_write_fsm.read() != WRITE_BC_UPT_LOCK))
    49734985        {
    49744986          if      (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
    49754987          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
    49764988          else if ((r_sc_fsm.read() == SC_UPT_LOCK) ||
    4977                    (r_sc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
     4989                   (r_sc_fsm.read() == SC_BC_UPT_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
    49784990          else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
    49794991        }
     
    49864998          if       (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)       r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
    49874999          else if ((r_sc_fsm.read() == SC_UPT_LOCK) ||
    4988                    (r_sc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
     5000                   (r_sc_fsm.read() == SC_BC_UPT_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
    49895001          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
    49905002          else if ((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
    4991                    (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
     5003                   (r_write_fsm.read() == WRITE_BC_UPT_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
    49925004        }
    49935005        break;
     
    49985010        {
    49995011          if      ((r_sc_fsm.read() == SC_UPT_LOCK) ||
    5000                    (r_sc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
     5012                   (r_sc_fsm.read() == SC_BC_UPT_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_SC;
    50015013          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
    50025014          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
    5003                    (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
     5015                   (r_write_fsm.read() == WRITE_BC_UPT_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
    50045016          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
    50055017        }
     
    50095021      case ALLOC_UPT_SC:
    50105022        if( (r_sc_fsm.read() != SC_UPT_LOCK) &&
    5011             (r_sc_fsm.read() != SC_INVAL_LOCK))
     5023            (r_sc_fsm.read() != SC_BC_UPT_LOCK))
    50125024        {
    50135025          if      (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
    50145026          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
    5015                    (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
     5027                   (r_write_fsm.read() == WRITE_BC_UPT_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
    50165028          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
    50175029          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
     
    50545066        /////////////////////
    50555067      case ALLOC_DIR_WRITE:
    5056         if ( ( (r_write_fsm.read() != WRITE_DIR_LOCK)    &&
    5057               (r_write_fsm.read() != WRITE_TRT_LOCK)    &&
    5058               (r_write_fsm.read() != WRITE_DIR_HIT_READ) &&
     5068        if ( ((r_write_fsm.read() != WRITE_DIR_LOCK) &&
     5069              (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) &&
     5070              (r_write_fsm.read() != WRITE_DIR_READ) &&
    50595071              (r_write_fsm.read() != WRITE_DIR_HIT) &&
    5060               (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
    5061               (r_write_fsm.read() != WRITE_INVAL_LOCK) &&
     5072              (r_write_fsm.read() != WRITE_BC_TRT_LOCK) &&
     5073              (r_write_fsm.read() != WRITE_BC_UPT_LOCK) &&
    50625074              (r_write_fsm.read() != WRITE_UPT_LOCK) &&
    5063               (r_write_fsm.read() != WRITE_HEAP_LOCK))
     5075              (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK))
    50645076            ||
    5065             ( (r_write_fsm.read()       == WRITE_HEAP_LOCK) &&
     5077            ( (r_write_fsm.read()       == WRITE_UPT_HEAP_LOCK) &&
    50665078              (r_alloc_heap_fsm.read()  == ALLOC_HEAP_WRITE) )
    50675079            ||
    5068             ( (r_write_fsm.read()     == WRITE_TRT_LOCK) &&
     5080            ( (r_write_fsm.read()     == WRITE_MISS_TRT_LOCK) &&
    50695081              (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)   )   )
    50705082        {
     
    50815093              (r_sc_fsm.read() != SC_DIR_HIT_READ )  &&
    50825094              (r_sc_fsm.read() != SC_DIR_HIT_WRITE ) &&
    5083 //              (r_sc_fsm.read() != SC_TRT_GET_LOCK )    &&
    5084               (r_sc_fsm.read() != SC_TRT_PUT_LOCK)       &&
    5085               (r_sc_fsm.read() != SC_INVAL_LOCK)     &&
     5095//              (r_sc_fsm.read() != SC_MISS_TRT_LOCK )    &&
     5096              (r_sc_fsm.read() != SC_BC_TRT_LOCK)       &&
     5097              (r_sc_fsm.read() != SC_BC_UPT_LOCK)     &&
    50865098              (r_sc_fsm.read() != SC_UPT_LOCK)       &&
    5087               (r_sc_fsm.read() != SC_HEAP_LOCK))
     5099              (r_sc_fsm.read() != SC_UPT_HEAP_LOCK))
    50885100            ||
    5089             ( (r_sc_fsm.read()       == SC_HEAP_LOCK) &&
     5101            ( (r_sc_fsm.read()       == SC_UPT_HEAP_LOCK) &&
    50905102              (r_alloc_heap_fsm.read() == ALLOC_HEAP_SC) )
    50915103            ||
    5092             ( (r_sc_fsm.read()      == SC_TRT_GET_LOCK ) &&
     5104            ( (r_sc_fsm.read()      == SC_MISS_TRT_LOCK ) &&
    50935105              (r_alloc_trt_fsm.read() == ALLOC_TRT_SC)    ) )
    50945106        {
     
    51425154        if ( r_read_fsm.read() != READ_TRT_LOCK )
    51435155        {
    5144           if      ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
    5145                    (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
    5146           else if ((r_sc_fsm.read() == SC_TRT_GET_LOCK) ||
    5147                    (r_sc_fsm.read() == SC_TRT_PUT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
     5156          if      ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK)   ||
     5157                   (r_write_fsm.read() == WRITE_BC_TRT_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
     5158          else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) ||
     5159                   (r_sc_fsm.read() == SC_BC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
    51485160          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
    51495161          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
     
    51535165        /////////////////////
    51545166      case ALLOC_TRT_WRITE:
    5155         if ( (r_write_fsm.read() != WRITE_TRT_LOCK) &&
    5156              (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
    5157              (r_write_fsm.read() != WRITE_INVAL_LOCK))
    5158         {
    5159           if      ((r_sc_fsm.read() == SC_TRT_GET_LOCK) ||
    5160                    (r_sc_fsm.read() == SC_TRT_PUT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
     5167        if ( (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) &&
     5168             (r_write_fsm.read() != WRITE_BC_TRT_LOCK) &&
     5169             (r_write_fsm.read() != WRITE_BC_UPT_LOCK))
     5170        {
     5171          if      ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) ||
     5172                   (r_sc_fsm.read() == SC_BC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
    51615173          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
    51625174          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
     
    51675179        ////////////////////
    51685180      case ALLOC_TRT_SC:
    5169         if ( (r_sc_fsm.read() != SC_TRT_GET_LOCK) &&
    5170              (r_sc_fsm.read() != SC_TRT_PUT_LOCK) &&
    5171              (r_sc_fsm.read() != SC_INVAL_LOCK))
     5181        if ( (r_sc_fsm.read() != SC_MISS_TRT_LOCK) &&
     5182             (r_sc_fsm.read() != SC_BC_TRT_LOCK) &&
     5183             (r_sc_fsm.read() != SC_BC_UPT_LOCK))
    51725184        {
    51735185          if      (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
     
    51755187                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
    51765188          else if (r_read_fsm.read() == READ_TRT_LOCK)              r_alloc_trt_fsm = ALLOC_TRT_READ;
    5177           else if ((r_write_fsm.read() == WRITE_TRT_LOCK)     ||
    5178                    (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
     5189          else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK)     ||
     5190                   (r_write_fsm.read() == WRITE_BC_TRT_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
    51795191        }
    51805192        break;
     
    51875199                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
    51885200          else if (r_read_fsm.read() == READ_TRT_LOCK)              r_alloc_trt_fsm = ALLOC_TRT_READ;
    5189           else if ((r_write_fsm.read() == WRITE_TRT_LOCK)    ||
    5190                    (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
    5191           else if ((r_sc_fsm.read() == SC_TRT_GET_LOCK) ||
    5192                    (r_sc_fsm.read() == SC_TRT_PUT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
     5201          else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK)    ||
     5202                   (r_write_fsm.read() == WRITE_BC_TRT_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
     5203          else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) ||
     5204                   (r_sc_fsm.read() == SC_BC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
    51935205        }
    51945206        break;
     
    51985210            (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) {
    51995211          if      (r_read_fsm.read() == READ_TRT_LOCK)              r_alloc_trt_fsm = ALLOC_TRT_READ;
    5200           else if ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
    5201                    (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
    5202           else if ((r_sc_fsm.read() == SC_TRT_GET_LOCK) ||
    5203                    (r_sc_fsm.read() == SC_TRT_PUT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
     5212          else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK)   ||
     5213                   (r_write_fsm.read() == WRITE_BC_TRT_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
     5214          else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) ||
     5215                   (r_sc_fsm.read() == SC_BC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_SC;
    52045216          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
    52055217        }
     
    52195231    switch ( r_alloc_heap_fsm.read() )
    52205232    {
    5221 
    5222       ////////////////////
    5223       case ALLOC_HEAP_READ:
     5233        ////////////////////
     5234        case ALLOC_HEAP_READ:
    52245235        if (  (r_read_fsm.read() != READ_HEAP_LOCK) &&
    52255236              (r_read_fsm.read() != READ_HEAP_ERASE)     )
    52265237        {
    5227           if        (r_write_fsm.read() == WRITE_HEAP_LOCK)         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
    5228           else if   (r_sc_fsm.read() == SC_HEAP_LOCK)             r_alloc_heap_fsm = ALLOC_HEAP_SC;
    5229           else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
    5230           else if   (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
     5238          if      (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
     5239          else if (r_sc_fsm.read() == SC_UPT_HEAP_LOCK)              r_alloc_heap_fsm = ALLOC_HEAP_SC;
     5240          else if (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
     5241          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
    52315242        }
    52325243        break;
    52335244
    52345245        /////////////////////
    5235       case ALLOC_HEAP_WRITE:
    5236         if (  (r_write_fsm.read() != WRITE_HEAP_LOCK)   &&
     5246        case ALLOC_HEAP_WRITE:
     5247        if (  (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)   &&
    52375248              (r_write_fsm.read() != WRITE_UPT_REQ)     &&
    5238               (r_write_fsm.read() != WRITE_UPDATE)  )
    5239         {
    5240           if        (r_sc_fsm.read() == SC_HEAP_LOCK)             r_alloc_heap_fsm = ALLOC_HEAP_SC;
    5241           else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
    5242           else if   (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
    5243           else if   (r_read_fsm.read() == READ_HEAP_LOCK)               r_alloc_heap_fsm = ALLOC_HEAP_READ;
     5249              (r_write_fsm.read() != WRITE_UPT_NEXT)  )
     5250        {
     5251          if      (r_sc_fsm.read() == SC_UPT_HEAP_LOCK)          r_alloc_heap_fsm = ALLOC_HEAP_SC;
     5252          else if (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
     5253          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
     5254          else if (r_read_fsm.read() == READ_HEAP_LOCK)              r_alloc_heap_fsm = ALLOC_HEAP_READ;
    52445255        }
    52455256        break;
    52465257
    52475258        ////////////////////
    5248       case ALLOC_HEAP_SC:
    5249         if (  (r_sc_fsm.read() != SC_HEAP_LOCK)  &&
     5259        case ALLOC_HEAP_SC:
     5260        if (  (r_sc_fsm.read() != SC_UPT_HEAP_LOCK)  &&
    52505261              (r_sc_fsm.read() != SC_UPT_REQ )    &&
    52515262              (r_sc_fsm.read() != SC_UPT_NEXT)  )
    52525263        {
    5253           if      (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
    5254           else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
    5255           else if (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
    5256           else if (r_write_fsm.read() == WRITE_HEAP_LOCK)         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
     5264          if      (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
     5265          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
     5266          else if (r_read_fsm.read() == READ_HEAP_LOCK)          r_alloc_heap_fsm = ALLOC_HEAP_READ;
     5267          else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
    52575268        }
    52585269        break;
    52595270
    52605271        ///////////////////////
    5261       case ALLOC_HEAP_CLEANUP:
     5272        case ALLOC_HEAP_CLEANUP:
    52625273        if ( (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) &&
    52635274            (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH)&&
    52645275            (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)    )
    52655276        {
    5266           if        (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
    5267           else if   (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
    5268           else if   (r_write_fsm.read() == WRITE_HEAP_LOCK)         r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
    5269           else if   (r_sc_fsm.read() == SC_HEAP_LOCK)             r_alloc_heap_fsm = ALLOC_HEAP_SC;
     5277          if      (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
     5278          else if (r_read_fsm.read() == READ_HEAP_LOCK)          r_alloc_heap_fsm = ALLOC_HEAP_READ;
     5279          else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)    r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
     5280          else if (r_sc_fsm.read() == SC_UPT_HEAP_LOCK)          r_alloc_heap_fsm = ALLOC_HEAP_SC;
    52705281        }
    52715282        break;
    52725283        ////////////////////////
    5273       case ALLOC_HEAP_XRAM_RSP:
     5284        case ALLOC_HEAP_XRAM_RSP:
    52745285        if ( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE )
    52755286        {
    5276           if        (r_read_fsm.read() == READ_HEAP_LOCK)               r_alloc_heap_fsm = ALLOC_HEAP_READ;
    5277           else if   (r_write_fsm.read() == WRITE_HEAP_LOCK)        r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
    5278           else if   (r_sc_fsm.read() == SC_HEAP_LOCK)             r_alloc_heap_fsm = ALLOC_HEAP_SC;
    5279           else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
     5287          if        (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
     5288          else if   (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
     5289          else if   (r_sc_fsm.read() == SC_UPT_HEAP_LOCK)       r_alloc_heap_fsm = ALLOC_HEAP_SC;
     5290          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
    52805291        }
    52815292        break;
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