- Timestamp:
- Mar 14, 2012, 10:22:45 PM (12 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h
r205 r206 116 116 DCACHE_XTN_DC_INVAL_GO, 117 117 DCACHE_XTN_DT_INVAL, 118 //handling long write (set dirty bit) 119 DCACHE_DIRTY_TLB_SET, 120 DCACHE_DIRTY_CACHE_SET, 118 //handling dirty bit update 119 DCACHE_DIRTY_GET_PTE, 121 120 DCACHE_DIRTY_SC_WAIT, 122 DCACHE_DIRTY_UNC_WAIT,123 121 // handling processor miss requests 124 122 DCACHE_MISS_VICTIM, 125 123 DCACHE_MISS_INVAL, 126 DCACHE_MISS_INVAL_WAIT,127 124 DCACHE_MISS_WAIT, 128 125 DCACHE_MISS_UPDT, … … 274 271 // debug variables (for each FSM) 275 272 ///////////////////////////////////////////// 276 uint32_t 277 bool 278 bool 279 bool 280 bool 281 bool 282 bool 283 bool 273 uint32_t m_debug_start_cycle; 274 bool m_debug_ok; 275 bool m_debug_previous_hit; 276 bool m_debug_dcache_fsm; 277 bool m_debug_icache_fsm; 278 bool m_debug_cleanup_fsm; 279 bool m_debug_inval_itlb_fsm; 280 bool m_debug_inval_dtlb_fsm; 284 281 285 282 /////////////////////////////// … … 344 341 sc_signal<paddr_t> r_dcache_p0_paddr; // physical address 345 342 sc_signal<bool> r_dcache_p0_cacheable; // address cacheable 346 sc_signal<size_t> r_dcache_p0_tlb_way; // selected way (from dtlb)347 sc_signal<size_t> r_dcache_p0_tlb_set; // selected set (from dtlb)348 sc_signal<paddr_t> r_dcache_p0_tlb_nline; // nline value (from dtlb)349 sc_signal<bool> r_dcache_p0_tlb_dirty; // dirty bit (from dtlb)350 sc_signal<bool> r_dcache_p0_tlb_big; // big page bit (from dtlb)351 343 // registers written in P1 stage (used in P2 stage) 352 344 sc_signal<bool> r_dcache_p1_valid; // P2 pipeline stage must be executed 353 sc_signal<bool> r_dcache_p1_updt_cache; // dcache must be updated354 sc_signal<bool> r_dcache_p1_set_dirty; // PTE dirty bit must be set355 sc_signal<uint32_t> r_dcache_p1_vaddr; // virtual address (from proc)356 345 sc_signal<uint32_t> r_dcache_p1_wdata; // write data (from proc) 357 346 sc_signal<vci_be_t> r_dcache_p1_be; // byte enable (from proc) … … 360 349 sc_signal<size_t> r_dcache_p1_cache_set; // selected set (from dcache) 361 350 sc_signal<size_t> r_dcache_p1_cache_word; // selected word (from dcache) 362 sc_signal<size_t> r_dcache_p1_tlb_way; // selected way (from dtlb) 363 sc_signal<size_t> r_dcache_p1_tlb_set; // selected set (from dtlb) 364 sc_signal<paddr_t> r_dcache_p1_tlb_nline; // nline value (from dtlb) 365 sc_signal<bool> r_dcache_p1_tlb_big; // big page bit (from dtlb) 366 // registers written in P2 stage (used in long write) 367 sc_signal<size_t> r_dcache_p2_way; // selected way in dtlb or dcache 368 sc_signal<size_t> r_dcache_p2_set; // selected set in dtlb or dcache 369 sc_signal<size_t> r_dcache_p2_word; // selected word in dcache 370 sc_signal<paddr_t> r_dcache_p2_pte_paddr; // PTE physical address 371 sc_signal<size_t> r_dcache_p2_pte_value; // PTE value 372 sc_signal<bool> r_dcache_p2_type_sc; // request type (WRITE or SC) 373 sc_signal<bool> r_dcache_p2_sc_success; // successful SC request 374 351 // registers used by the Dirty bit sub-fsm 352 sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address 353 sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache 354 sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache 355 375 356 // communication between DCACHE FSM and VCI_CMD FSM 376 357 sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command … … 422 403 423 404 // ITLB and DTLB invalidation 424 sc_signal<bool> r_dcache_itlb_inval_req; // inval request for itlb425 sc_signal<bool> r_dcache_dtlb_inval_req; // inval request for dtlb426 405 sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index 427 406 sc_signal<size_t> r_dcache_tlb_inval_count; // tlb entry counter … … 436 415 437 416 // dcache directory extension 438 bool *r_dcache_in_ itlb; // copy of dcache line initlb439 bool *r_dcache_ in_dtlb; // copy of dcache line in dtlb417 bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 418 bool *r_dcache_contains_ptd; // cache line contains a PTD 440 419 441 420 ///////////////////////////////////
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