Changeset 210 for trunk/modules/vci_cc_vcache_wrapper_v4/caba/source

Timestamp:

Mar 20, 2012, 4:32:16 PM (13 years ago)

Author:

bouyer

Message:

cache_monitor(): use read_neutral(), this should not change the cache state
If paddr_t is not larger than 32bits do not try to shift by 32bits,

and assert that the high bits are 0.

ICACHE_MISS_INVAL, DCACHE_MISS_INVAL: assert that inval() did something.
Add some more debug messages

File:

• trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (modified) (6 diffs)

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

@@ -478 +478 @@
     size_t      cache_word;
     uint32_t    cache_rdata;
-    bool        cache_hit = r_dcache.read( addr,
+    bool        cache_hit = r_dcache.read_neutral( addr,
                                            &cache_rdata,
                                            &cache_way,
@@ -938 +938 @@
             r_tgt_pktid = p_vci_tgt_c.pktid.read();
 
-            r_tgt_paddr  = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 |
-                          (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; 
+            if (sizeof(paddr_t) <= 32) {
+                assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr");
+                r_tgt_paddr  =
+                        (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; 
+            } else {
+                r_tgt_paddr  = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 |
+                        (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; 
+            }
 
             if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
@@ -1253 +1259 @@
             if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) 
             {
-                r_icache_vci_paddr   = (paddr_t)r_mmu_word_hi.read() << 32 | 
-                                       (paddr_t)r_mmu_word_lo.read();
+                if (sizeof(paddr_t) <= 32) {
+                        assert(r_mmu_word_hi.read() == 0 &&
+                            "high bits should be 0 for 32bit paddr");
+                        r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
+                } else {
+                        r_icache_vci_paddr =
+                                (paddr_t)r_mmu_word_hi.read() << 32 | 
+                                (paddr_t)r_mmu_word_lo.read();
+                }
                 r_icache_fsm         = ICACHE_XTN_CACHE_INVAL_PA;   
                 break;
@@ -1633 +1646 @@
     {
         paddr_t nline;
-
-        r_icache.inval( r_icache_miss_way.read(),
+        bool hit;
+
+        hit = r_icache.inval( r_icache_miss_way.read(),
                         r_icache_miss_set.read(),
                         &nline );       // unused
+        assert(hit && "selected way/set line should be in icache");
 
         r_icache_fsm = ICACHE_MISS_WAIT;
@@ -2335 +2350 @@
                     case iss_t::XTN_MMU_DCACHE_PA_INV:          // dcache, dtlb & itlb access
                         r_dcache_fsm   = DCACHE_XTN_DC_INVAL_PA;
-                        r_dcache_p0_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | 
-                                         (paddr_t)r_mmu_word_lo.read();
+                        if (sizeof(paddr_t) <= 32) {
+                                assert(r_mmu_word_hi.read() == 0 &&
+                                    "high bits should be 0 for 32bit paddr");
+                                r_dcache_p0_paddr =
+                                        (paddr_t)r_mmu_word_lo.read();
+                        } else {
+                                r_dcache_p0_paddr =
+                                        (paddr_t)r_mmu_word_hi.read() << 32 | 
+                                        (paddr_t)r_mmu_word_lo.read();
+                        }
                         break;
 
@@ -3586 +3609 @@
         size_t  way        = r_dcache_miss_way.read();
         size_t  set        = r_dcache_miss_set.read();
-
-        r_dcache.inval( way, 
+        bool hit;
+
+        hit = r_dcache.inval( way, 
                         set,
                         &nline );
-
+        assert(hit && "selected way/set line should be in dcache");
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC.DCACHE_MISS_INVAL> inval line:"
+              << " / way = "   << way 
+              << " / set = "   << set
+              << " / nline = "  << std::hex << nline << std::endl; 
+}
+#endif
         // if selective itlb & dtlb invalidate are required 
         // the miss response is not handled before invalidate completed