Changeset 211

Timestamp:

Mar 21, 2012, 12:43:18 PM (13 years ago)

Author:

bouyer

Message:

cache_monitor(): monitor the icache as well as the dcache
Add missing break for CLEANUP_INS_GO and CLEANUP_DATA_GO (this cause
the INS cleanup to be missed if one occurs one cycle after a DATA cleanup
is being sent)

Location:

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source

Files:

• include/vci_cc_vcache_wrapper_v4.h (modified) (1 diff)
• src/vci_cc_vcache_wrapper_v4.cpp (modified) (4 diffs)

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h

@@ -274 +274 @@
     bool                                m_debug_ok;
     bool                                m_debug_previous_hit;
+    bool                                m_idebug_previous_hit;
     bool                                m_debug_dcache_fsm;
     bool                                m_debug_icache_fsm;

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

@@ -483 +483 @@
                                            &cache_set,
                                            &cache_word );
+    bool        icache_hit = r_icache.read_neutral( addr,
+                                           &cache_rdata,
+                                           &cache_way,
+                                           &cache_set,
+                                           &cache_word );
     if ( cache_hit != m_debug_previous_hit )
     {
         std::cout << "PROC " << name() 
-                  << " cache change at cycle " << std::dec << m_cpt_total_cycles
+                  << " dcache change at cycle " << std::dec << m_cpt_total_cycles
                   << " for adresse " << std::hex << addr
                   << " / HIT = " << cache_hit << std::endl;
-    }
-    m_debug_previous_hit = cache_hit;
+        m_debug_previous_hit = cache_hit;
+    }
+    if ( icache_hit != m_idebug_previous_hit )
+    {
+        std::cout << "PROC " << name() 
+                  << " icache change at cycle " << std::dec << m_cpt_total_cycles
+                  << " for adresse " << std::hex << addr
+                  << " / HIT = " << icache_hit << std::endl;
+        m_idebug_previous_hit = icache_hit;
+    }
 }
-
-
 
 /*
@@ -721 +732 @@
         // Debug variables
         m_debug_previous_hit      = false;
+        m_idebug_previous_hit      = false;
         m_debug_dcache_fsm        = false;
         m_debug_icache_fsm        = false;
@@ -4709 +4721 @@
 #endif
             }
+            break;
         }
         ////////////////////////
@@ -4727 +4740 @@
 #endif
             }
+            break;
         }
     } // end switch CLEANUP FSM