- Timestamp:
- Mar 21, 2012, 7:10:45 PM (13 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
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trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
r211 r213 1609 1609 if ( not r_icache_cleanup_req.read() ) 1610 1610 { 1611 r_icache.inval( r_icache_miss_way.read(), 1612 r_icache_miss_set.read(), 1613 &nline ); 1611 bool hit; 1612 hit = r_icache.inval( r_icache_miss_way.read(), 1613 r_icache_miss_set.read(), 1614 &nline ); 1615 assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache"); 1614 1616 1615 1617 // request cleanup … … 1845 1847 { 1846 1848 paddr_t nline; 1847 r_icache.inval( r_icache_cc_way.read(), 1848 r_icache_cc_set.read(), 1849 &nline ); 1850 1849 bool hit; 1850 hit = r_icache.inval( r_icache_cc_way.read(), 1851 r_icache_cc_set.read(), 1852 &nline ); 1853 assert (hit && "ICACHE_CC_INVAL way/set should still be in icache"); 1851 1854 r_tgt_icache_req = false; 1852 1855 r_tgt_icache_rsp = true; … … 3525 3528 size_t way = r_dcache_xtn_way.read(); 3526 3529 size_t set = r_dcache_xtn_set.read(); 3530 bool hit; 3527 3531 3528 r_dcache.inval( way, 3529 set, 3530 &nline ); 3532 hit = r_dcache.inval( way, 3533 set, 3534 &nline ); 3535 assert(hit && "XTN_DC_INVAL way/set should still be in cache"); 3531 3536 3532 3537 // request cleanup … … 3980 3985 size_t way = r_dcache_dirty_way.read(); 3981 3986 size_t set = r_dcache_dirty_set.read(); 3982 3983 r_dcache.inval( r_dcache_dirty_way.read(), 3987 bool hit; 3988 3989 hit = r_dcache.inval( r_dcache_dirty_way.read(), 3984 3990 r_dcache_dirty_set.read(), 3985 3991 &nline ); 3992 assert(hit && "PTE should still be in dcache"); 3993 // request cleanup 3994 r_dcache_cleanup_req = true; 3995 r_dcache_cleanup_line = nline; 3986 3996 3987 3997 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE … … 4102 4112 size_t way = r_dcache_cc_way.read(); 4103 4113 size_t set = r_dcache_cc_set.read(); 4104 4105 r_dcache.inval( way, 4106 set, 4107 &nline ); 4114 bool hit; 4115 4116 hit = r_dcache.inval( way, 4117 set, 4118 &nline ); 4119 assert(hit && "CC_INVAL way/set should still be in dcache"); 4108 4120 4109 4121 // possible itlb & dtlb invalidate
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