Changeset 213 for trunk/modules/vci_cc_vcache_wrapper_v4/caba/source

Timestamp:

Mar 21, 2012, 7:10:45 PM (13 years ago)

Author:

bouyer

Message:

DCACHE_DIRTY_SC_WAIT: when the SC fails, send a cleanup as we invalidate the
data in the dcache.
while there, add assert() that the line we invalidate is really in the
cache at various places.

File:

• trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (modified) (5 diffs)

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

@@ -1609 +1609 @@
         if ( not r_icache_cleanup_req.read() )
         {
-            r_icache.inval( r_icache_miss_way.read(),
-                            r_icache_miss_set.read(),
-                            &nline );
+            bool hit;
+            hit = r_icache.inval( r_icache_miss_way.read(),
+                                  r_icache_miss_set.read(),
+                                  &nline );
+            assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache");
   
             // request cleanup 
@@ -1845 +1847 @@
     {                       
         paddr_t nline;
-        r_icache.inval( r_icache_cc_way.read(),
-                        r_icache_cc_set.read(), 
-                        &nline );
-
+        bool hit;
+        hit = r_icache.inval( r_icache_cc_way.read(),
+                              r_icache_cc_set.read(), 
+                              &nline );
+        assert (hit && "ICACHE_CC_INVAL way/set should still be in icache");
         r_tgt_icache_req = false;
         r_tgt_icache_rsp = true;
@@ -3525 +3528 @@
             size_t      way        = r_dcache_xtn_way.read();
             size_t      set        = r_dcache_xtn_set.read();
+            bool hit;
    
-            r_dcache.inval( way,
-                            set,
-                            &nline );
+            hit = r_dcache.inval( way,
+                                  set,
+                                  &nline );
+            assert(hit && "XTN_DC_INVAL way/set should still be in cache");
 
             // request cleanup
@@ -3980 +3985 @@
                 size_t  way = r_dcache_dirty_way.read();
                 size_t  set = r_dcache_dirty_set.read();
-
-                r_dcache.inval( r_dcache_dirty_way.read(), 
+                bool hit;
+
+                hit = r_dcache.inval( r_dcache_dirty_way.read(), 
                                 r_dcache_dirty_set.read(),
                                 &nline );
+                assert(hit && "PTE should still be in dcache");
+                // request cleanup
+                r_dcache_cleanup_req  = true;
+                r_dcache_cleanup_line = nline;
 
                 if ( r_dcache_in_tlb[way*m_dcache_sets+set] )           // contains PTE
@@ -4102 +4112 @@
         size_t  way        = r_dcache_cc_way.read();
         size_t  set        = r_dcache_cc_set.read();
-
-        r_dcache.inval( way, 
-                        set,
-                        &nline );
+        bool hit;
+
+        hit = r_dcache.inval( way, 
+                              set,
+                              &nline );
+        assert(hit && "CC_INVAL way/set should still be in dcache");
             
         // possible itlb & dtlb invalidate