Index: /trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h =================================================================== --- /trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 214) +++ /trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 215) @@ -296,4 +296,8 @@ size_t m_debug_previous_count; + bool m_monitor_ok; + vci_addr_t m_monitor_base; + vci_addr_t m_monitor_length; + // instrumentation counters uint32_t m_cpt_cycles; // Counter of cycles @@ -322,6 +326,6 @@ public: - sc_in p_clk; - sc_in p_resetn; + sc_in p_clk; + sc_in p_resetn; soclib::caba::VciTarget p_vci_tgt; soclib::caba::VciTarget p_vci_tgt_cleanup; @@ -344,16 +348,20 @@ size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT - size_t debug_start_cycle=0, + size_t debug_start_cycle=0, bool debug_ok=false); ~VciMemCacheV4(); + + void print_stats(); + void print_trace(); + void copies_monitor(vci_addr_t addr); + void start_monitor(vci_addr_t addr, vci_addr_t length); + void stop_monitor(); + + private: void transition(); void genMoore(); - void print_stats(); - void print_trace(); - void cache_monitor(vci_addr_t addr); - - private: + void check_monitor(vci_addr_t addr, data_t data); // Component attributes @@ -530,5 +538,5 @@ // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction) - sc_signal r_init_rsp_to_tgt_rsp_req; // valid request + sc_signal r_init_rsp_to_tgt_rsp_req; // valid request sc_signal r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid sc_signal r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid Index: /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp =================================================================== --- /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 214) +++ /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 215) @@ -46,7 +46,7 @@ #define DEBUG_MEMC_INIT_CMD 1 // detailed trace of INIT_CMD FSM #define DEBUG_MEMC_INIT_RSP 1 // detailed trace of INIT_RSP FSM -#define DEBUG_MEMC_TGT_CMD 0 // detailed trace of TGT_CMD FSM -#define DEBUG_MEMC_TGT_RSP 0 // detailed trace of TGT_RSP FSM -#define DEBUG_MEMC_CLEANUP 0 // detailed trace of CLEANUP FSM +#define DEBUG_MEMC_TGT_CMD 1 // detailed trace of TGT_CMD FSM +#define DEBUG_MEMC_TGT_RSP 1 // detailed trace of TGT_RSP FSM +#define DEBUG_MEMC_CLEANUP 1 // detailed trace of CLEANUP FSM #define RANDOMIZE_SC 1 @@ -444,6 +444,34 @@ } // end constructor +/////////////////////////////////////////////////////////////////////// +tmpl(void)::start_monitor( vci_addr_t addr, vci_addr_t length ) +/////////////////////////////////////////////////////////////////////// +{ + m_monitor_ok = true; + m_monitor_base = addr; + m_monitor_length = length; +} + +/////////////////////////////////////////////////////////////////////// +tmpl(void)::stop_monitor() +/////////////////////////////////////////////////////////////////////// +{ + m_monitor_ok = false; +} + +/////////////////////////////////////////////////////////////////////// +tmpl(void)::check_monitor( vci_addr_t addr, data_t data ) +/////////////////////////////////////////////////////////////////////// +{ + if ( (addr >= m_monitor_base) and + (addr < m_monitor_base + m_monitor_length) ) + { + std::cout << " MEMC Write Monitor : Address = " << std::hex << addr + << " / Data = " << data << std::endl; + } +} + ///////////////////////////////////////////////////// -tmpl(void)::cache_monitor( vci_addr_t addr ) +tmpl(void)::copies_monitor( vci_addr_t addr ) ///////////////////////////////////////////////////// { @@ -1694,5 +1722,5 @@ { r_write_data[i] = (r_write_data[i].read() & mask) | - (m_cache_data[way][set][i] & ~mask); + (m_cache_data[way][set][i] & ~mask); } } // end for @@ -1757,5 +1785,14 @@ for(size_t i=0 ; i Post a request to TGT_RSP FSM: rsrcid = " - << std::hex << r_write_srcid.read() << std:: endl; -} -#endif + // post the request to TGT_RSP_FSM r_write_to_tgt_rsp_req = true; r_write_to_tgt_rsp_srcid = r_write_srcid.read(); r_write_to_tgt_rsp_trdid = r_write_trdid.read(); r_write_to_tgt_rsp_pktid = r_write_pktid.read(); - r_write_fsm = WRITE_IDLE; + + // try to get a new write request from the FIFO + if ( m_cmd_write_addr_fifo.rok() ) + { + m_cpt_write++; + m_cpt_write_cells++; + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 1; + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_srcid = m_cmd_write_srcid_fifo.read(); + r_write_trdid = m_cmd_write_trdid_fifo.read(); + r_write_pktid = m_cmd_write_pktid_fifo.read(); + + // initialize the be field for all words + for ( size_t i=0 ; i Post a request to TGT_RSP FSM: rsrcid = " + << std::hex << r_write_srcid.read() << std::endl; + if ( m_cmd_write_addr_fifo.rok() ) + { + std::cout << " New Write request: " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; + } +} +#endif } break; @@ -2731,7 +2825,7 @@ } - else if (m_update_tab.is_full() && r_xram_rsp_victim_inval.read()) - { - r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + else if (m_update_tab.is_full() && r_xram_rsp_victim_inval.read()) + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; #if DEBUG_MEMC_XRAM_RSP @@ -2743,5 +2837,5 @@ } #endif - } + } else { @@ -2774,5 +2868,14 @@ size_t set = r_xram_rsp_victim_set.read(); size_t way = r_xram_rsp_victim_way.read(); - for(size_t i=0; i