- Timestamp:
- Mar 23, 2012, 8:04:01 PM (13 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper_v4/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h
r214 r217 334 334 /////////////////////////////// 335 335 sc_signal<int> r_dcache_fsm; // state register 336 sc_signal<int> r_dcache_fsm_save; // return state for coherence operation 336 sc_signal<int> r_dcache_fsm_cc_save; // return state for coherence operation 337 sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan operation 337 338 // registers written in P0 stage (used in P1 stage) 338 339 sc_signal<bool> r_dcache_p0_valid; // P1 pipeline stage must be executed -
trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
r213 r217 218 218 r_icache_fsm("r_icache_fsm"), 219 219 r_icache_fsm_save("r_icache_fsm_save"), 220 220 221 r_icache_vci_paddr("r_icache_vci_paddr"), 221 222 r_icache_vaddr_save("r_icache_vaddr_save"), … … 242 243 243 244 r_dcache_fsm("r_dcache_fsm"), 244 r_dcache_fsm_save("r_dcache_fsm_save"), 245 r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"), 246 r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"), 245 247 246 248 r_dcache_p0_valid("r_dcache_p0_valid"), … … 1764 1766 if ( r_tgt_icache_req.read() ) 1765 1767 { 1766 r_icache_fsm = ICACHE_CC_CHECK;1768 r_icache_fsm = ICACHE_CC_CHECK; 1767 1769 r_icache_fsm_save = r_icache_fsm.read(); 1768 1770 break; … … 2144 2146 if ( tlb_inval_required ) 2145 2147 { 2146 r_dcache_fsm_s ave = DCACHE_IDLE;2147 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;2148 r_dcache_p0_valid = false;2148 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 2149 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 2150 r_dcache_p0_valid = false; 2149 2151 } 2150 2152 // external coherence request 2151 2153 else if ( r_tgt_dcache_req.read() ) 2152 2154 { 2153 r_dcache_fsm_ save = DCACHE_IDLE;2154 r_dcache_fsm = DCACHE_CC_CHECK;2155 r_dcache_p0_valid = false;2155 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 2156 r_dcache_fsm = DCACHE_CC_CHECK; 2157 r_dcache_p0_valid = false; 2156 2158 } 2157 2159 … … 3281 3283 if ( r_tgt_dcache_req ) 3282 3284 { 3283 r_dcache_fsm = DCACHE_CC_CHECK;3284 r_dcache_fsm_ save = r_dcache_fsm;3285 r_dcache_fsm = DCACHE_CC_CHECK; 3286 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3285 3287 break; 3286 3288 } … … 3337 3339 if ( r_tgt_dcache_req.read() ) 3338 3340 { 3339 r_dcache_fsm = DCACHE_CC_CHECK;3340 r_dcache_fsm _save = DCACHE_XTN_SYNC;3341 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3342 r_dcache_fsm = DCACHE_CC_CHECK; 3341 3343 } 3342 3344 … … 3357 3359 if ( r_tgt_dcache_req ) 3358 3360 { 3359 r_dcache_fsm = DCACHE_CC_CHECK;3360 r_dcache_fsm _save = r_dcache_fsm;3361 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3362 r_dcache_fsm = DCACHE_CC_CHECK; 3361 3363 break; 3362 3364 } … … 3544 3546 r_dcache_tlb_inval_line = nline; 3545 3547 r_dcache_tlb_inval_count = 0; 3546 r_dcache_fsm_s ave= DCACHE_XTN_DC_INVAL_END;3548 r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; 3547 3549 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 3548 3550 r_dcache_in_tlb[way*m_dcache_sets+set] = false; … … 3649 3651 r_dcache_tlb_inval_count = 0; 3650 3652 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 3651 r_dcache_fsm_s ave= DCACHE_MISS_WAIT;3653 r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; 3652 3654 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 3653 3655 } … … 3672 3674 if ( r_tgt_dcache_req ) 3673 3675 { 3674 r_dcache_fsm = DCACHE_CC_CHECK;3675 r_dcache_fsm _save = r_dcache_fsm;3676 r_dcache_fsm_cc_save = r_dcache_fsm; 3677 r_dcache_fsm = DCACHE_CC_CHECK; 3676 3678 break; 3677 3679 } … … 3843 3845 if ( r_tgt_dcache_req.read() ) 3844 3846 { 3845 r_dcache_fsm = DCACHE_CC_CHECK;3846 r_dcache_fsm _save = r_dcache_fsm;3847 r_dcache_fsm_cc_save = r_dcache_fsm; 3848 r_dcache_fsm = DCACHE_CC_CHECK; 3847 3849 break; 3848 3850 } … … 3877 3879 if ( r_tgt_dcache_req.read() ) 3878 3880 { 3879 r_dcache_fsm = DCACHE_CC_CHECK;3880 r_dcache_fsm _save = r_dcache_fsm;3881 r_dcache_fsm_cc_save = r_dcache_fsm; 3882 r_dcache_fsm = DCACHE_CC_CHECK; 3881 3883 break; 3882 3884 } … … 3954 3956 if ( r_tgt_dcache_req ) 3955 3957 { 3956 r_dcache_fsm = DCACHE_CC_CHECK;3957 r_dcache_fsm _save = r_dcache_fsm;3958 r_dcache_fsm_cc_save = r_dcache_fsm; 3959 r_dcache_fsm = DCACHE_CC_CHECK; 3958 3960 break; 3959 3961 } … … 3980 3982 #endif 3981 3983 } 3982 else // invalidate the cache line and TLBs3984 else // invalidate the cache line and TLBs 3983 3985 { 3984 3986 paddr_t nline; … … 3999 4001 r_dcache_tlb_inval_line = nline; 4000 4002 r_dcache_tlb_inval_count = 0; 4001 r_dcache_fsm_s ave= DCACHE_IDLE;4003 r_dcache_fsm_scan_save = DCACHE_IDLE; 4002 4004 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4003 4005 r_dcache_in_tlb[way*m_dcache_sets+set] = false; … … 4027 4029 // If the updated (or invalidated) cache line has copies in TLBs 4028 4030 // these TLB copies are invalidated. 4029 // The return state is defined in r_dcache_fsm_ save4031 // The return state is defined in r_dcache_fsm_cc_save 4030 4032 { 4031 4033 paddr_t paddr = r_tgt_paddr.read(); … … 4033 4035 4034 4036 4035 if( (r_dcache_fsm_ save == DCACHE_MISS_WAIT) and4037 if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and 4036 4038 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss 4037 4039 { … … 4039 4041 r_tgt_dcache_req = false; // coherence request completed 4040 4042 r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update 4041 r_dcache_fsm = r_dcache_fsm_ save;4043 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4042 4044 4043 4045 #if DEBUG_DCACHE … … 4082 4084 r_tgt_dcache_req = false; 4083 4085 r_tgt_dcache_rsp = r_tgt_update.read(); 4084 r_dcache_fsm = r_dcache_fsm_ save.read();4086 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4085 4087 } 4086 4088 … … 4124 4126 r_dcache_tlb_inval_line = nline; 4125 4127 r_dcache_tlb_inval_count = 0; 4128 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4126 4129 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4127 4130 r_dcache_in_tlb[way*m_dcache_sets+set] = false; … … 4133 4136 r_tgt_dcache_rsp = true; 4134 4137 r_tgt_dcache_req = false; 4135 r_dcache_fsm = r_dcache_fsm_ save.read();4138 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4136 4139 } 4137 4140 else // no inval … … 4139 4142 r_tgt_dcache_rsp = true; 4140 4143 r_tgt_dcache_req = false; 4141 r_dcache_fsm = r_dcache_fsm_ save.read();4144 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4142 4145 } 4143 4146 … … 4179 4182 r_dcache_tlb_inval_line = nline; 4180 4183 r_dcache_tlb_inval_count = 0; 4184 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4181 4185 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4182 4186 r_dcache_in_tlb[way*m_dcache_sets+set] = false; … … 4188 4192 r_tgt_dcache_rsp = true; 4189 4193 r_tgt_dcache_req = false; 4190 r_dcache_fsm = r_dcache_fsm_ save.read();4194 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4191 4195 } 4192 4196 else // no inval … … 4194 4198 r_tgt_dcache_rsp = true; 4195 4199 r_tgt_dcache_req = false; 4196 r_dcache_fsm = r_dcache_fsm_ save.read();4200 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4197 4201 } 4198 4202 } … … 4226 4230 // - r_dcache_tlb_inval_line 4227 4231 // - r_dcache_tlb_inval_count 4228 // - r_dcache_fsm_ save4232 // - r_dcache_fsm_cc_save 4229 4233 { 4230 4234 paddr_t line = r_dcache_tlb_inval_line.read(); // nline … … 4263 4267 if ( r_dcache_tlb_inval_count.read() == (m_dtlb_sets*m_dtlb_ways-1) ) 4264 4268 { 4265 if ( r_tgt_dcache_req.read() ) // It's a coherence request 4266 { 4267 r_tgt_dcache_rsp = true; 4268 r_tgt_dcache_req = false; 4269 } 4270 r_dcache_fsm = r_dcache_fsm_save.read(); 4269 r_dcache_fsm = r_dcache_fsm_scan_save.read(); 4271 4270 } 4272 4271 r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1; … … 4356 4355 bool dcache_miss_req = r_dcache_vci_miss_req.read() 4357 4356 and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); 4357 4358 4358 bool icache_miss_req = r_icache_miss_req.read() 4359 4359 and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
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