Index: /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h =================================================================== --- /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h (revision 216) +++ /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h (revision 217) @@ -334,5 +334,6 @@ /////////////////////////////// sc_signal r_dcache_fsm; // state register - sc_signal r_dcache_fsm_save; // return state for coherence operation + sc_signal r_dcache_fsm_cc_save; // return state for coherence operation + sc_signal r_dcache_fsm_scan_save; // return state for tlb scan operation // registers written in P0 stage (used in P1 stage) sc_signal r_dcache_p0_valid; // P1 pipeline stage must be executed Index: /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp =================================================================== --- /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (revision 216) +++ /trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (revision 217) @@ -218,4 +218,5 @@ r_icache_fsm("r_icache_fsm"), r_icache_fsm_save("r_icache_fsm_save"), + r_icache_vci_paddr("r_icache_vci_paddr"), r_icache_vaddr_save("r_icache_vaddr_save"), @@ -242,5 +243,6 @@ r_dcache_fsm("r_dcache_fsm"), - r_dcache_fsm_save("r_dcache_fsm_save"), + r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"), + r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"), r_dcache_p0_valid("r_dcache_p0_valid"), @@ -1764,5 +1766,5 @@ if ( r_tgt_icache_req.read() ) { - r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm = ICACHE_CC_CHECK; r_icache_fsm_save = r_icache_fsm.read(); break; @@ -2144,14 +2146,14 @@ if ( tlb_inval_required ) { - r_dcache_fsm_save = DCACHE_IDLE; - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - r_dcache_p0_valid = false; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + r_dcache_p0_valid = false; } // external coherence request else if ( r_tgt_dcache_req.read() ) { - r_dcache_fsm_save = DCACHE_IDLE; - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_p0_valid = false; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_p0_valid = false; } @@ -3281,6 +3283,6 @@ if ( r_tgt_dcache_req ) { - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_fsm_save = r_dcache_fsm; + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); break; } @@ -3337,6 +3339,6 @@ if ( r_tgt_dcache_req.read() ) { - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_fsm_save = DCACHE_XTN_SYNC; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_CC_CHECK; } @@ -3357,6 +3359,6 @@ if ( r_tgt_dcache_req ) { - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_fsm_save = r_dcache_fsm; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_CC_CHECK; break; } @@ -3544,5 +3546,5 @@ r_dcache_tlb_inval_line = nline; r_dcache_tlb_inval_count = 0; - r_dcache_fsm_save = DCACHE_XTN_DC_INVAL_END; + r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; r_dcache_in_tlb[way*m_dcache_sets+set] = false; @@ -3649,5 +3651,5 @@ r_dcache_tlb_inval_count = 0; r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - r_dcache_fsm_save = DCACHE_MISS_WAIT; + r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; r_dcache_in_tlb[way*m_dcache_sets+set] = false; } @@ -3672,6 +3674,6 @@ if ( r_tgt_dcache_req ) { - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_fsm_save = r_dcache_fsm; + r_dcache_fsm_cc_save = r_dcache_fsm; + r_dcache_fsm = DCACHE_CC_CHECK; break; } @@ -3843,6 +3845,6 @@ if ( r_tgt_dcache_req.read() ) { - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_fsm_save = r_dcache_fsm; + r_dcache_fsm_cc_save = r_dcache_fsm; + r_dcache_fsm = DCACHE_CC_CHECK; break; } @@ -3877,6 +3879,6 @@ if ( r_tgt_dcache_req.read() ) { - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_fsm_save = r_dcache_fsm; + r_dcache_fsm_cc_save = r_dcache_fsm; + r_dcache_fsm = DCACHE_CC_CHECK; break; } @@ -3954,6 +3956,6 @@ if ( r_tgt_dcache_req ) { - r_dcache_fsm = DCACHE_CC_CHECK; - r_dcache_fsm_save = r_dcache_fsm; + r_dcache_fsm_cc_save = r_dcache_fsm; + r_dcache_fsm = DCACHE_CC_CHECK; break; } @@ -3980,5 +3982,5 @@ #endif } - else // invalidate the cache line and TLBs + else // invalidate the cache line and TLBs { paddr_t nline; @@ -3999,5 +4001,5 @@ r_dcache_tlb_inval_line = nline; r_dcache_tlb_inval_count = 0; - r_dcache_fsm_save = DCACHE_IDLE; + r_dcache_fsm_scan_save = DCACHE_IDLE; r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; r_dcache_in_tlb[way*m_dcache_sets+set] = false; @@ -4027,5 +4029,5 @@ // If the updated (or invalidated) cache line has copies in TLBs // these TLB copies are invalidated. - // The return state is defined in r_dcache_fsm_save + // The return state is defined in r_dcache_fsm_cc_save { paddr_t paddr = r_tgt_paddr.read(); @@ -4033,5 +4035,5 @@ - if( (r_dcache_fsm_save == DCACHE_MISS_WAIT) and + if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss { @@ -4039,5 +4041,5 @@ r_tgt_dcache_req = false; // coherence request completed r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update - r_dcache_fsm = r_dcache_fsm_save; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); #if DEBUG_DCACHE @@ -4082,5 +4084,5 @@ r_tgt_dcache_req = false; r_tgt_dcache_rsp = r_tgt_update.read(); - r_dcache_fsm = r_dcache_fsm_save.read(); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); } @@ -4124,4 +4126,5 @@ r_dcache_tlb_inval_line = nline; r_dcache_tlb_inval_count = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; r_dcache_in_tlb[way*m_dcache_sets+set] = false; @@ -4133,5 +4136,5 @@ r_tgt_dcache_rsp = true; r_tgt_dcache_req = false; - r_dcache_fsm = r_dcache_fsm_save.read(); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); } else // no inval @@ -4139,5 +4142,5 @@ r_tgt_dcache_rsp = true; r_tgt_dcache_req = false; - r_dcache_fsm = r_dcache_fsm_save.read(); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); } @@ -4179,4 +4182,5 @@ r_dcache_tlb_inval_line = nline; r_dcache_tlb_inval_count = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; r_dcache_in_tlb[way*m_dcache_sets+set] = false; @@ -4188,5 +4192,5 @@ r_tgt_dcache_rsp = true; r_tgt_dcache_req = false; - r_dcache_fsm = r_dcache_fsm_save.read(); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); } else // no inval @@ -4194,5 +4198,5 @@ r_tgt_dcache_rsp = true; r_tgt_dcache_req = false; - r_dcache_fsm = r_dcache_fsm_save.read(); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); } } @@ -4226,5 +4230,5 @@ // - r_dcache_tlb_inval_line // - r_dcache_tlb_inval_count - // - r_dcache_fsm_save + // - r_dcache_fsm_cc_save { paddr_t line = r_dcache_tlb_inval_line.read(); // nline @@ -4263,10 +4267,5 @@ if ( r_dcache_tlb_inval_count.read() == (m_dtlb_sets*m_dtlb_ways-1) ) { - if ( r_tgt_dcache_req.read() ) // It's a coherence request - { - r_tgt_dcache_rsp = true; - r_tgt_dcache_req = false; - } - r_dcache_fsm = r_dcache_fsm_save.read(); + r_dcache_fsm = r_dcache_fsm_scan_save.read(); } r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1; @@ -4356,4 +4355,5 @@ bool dcache_miss_req = r_dcache_vci_miss_req.read() and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); + bool icache_miss_req = r_icache_miss_req.read() and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );