Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 222) +++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 223) @@ -1733,14 +1733,5 @@ if( m_debug_write_fsm ) { - if( r_write_is_cnt.read() && r_write_count.read() ) - { - std::cout << " Read the cache to complete local buffer /" - << " coherence broadcast required" << std::endl; - } - else - { - std::cout << " Read the cache to complete local buffer" - << std::endl; - } + std::cout << " Read the cache to complete local buffer" << std::endl; } #endif @@ -1800,5 +1791,5 @@ } - if ( owner ) r_write_count = r_write_count.read() - 1; + if ( owner and not no_update ) r_write_count = r_write_count.read() - 1; if ( no_update ) // Write transaction completed @@ -1825,6 +1816,7 @@ std::cout << " Coherence update required:" << " is_cnt = " << r_write_is_cnt.read() - << " count = " << std::dec << r_write_count.read() - << std::endl; + << " nb_copies = " << std::dec << r_write_count.read() << std::endl; + if (owner) + std::cout << " ... but the first copy is the writer" << std::endl; } } @@ -1892,5 +1884,5 @@ break; } - ///////////////////// + ///////////////////////// case WRITE_UPT_HEAP_LOCK: // get access to heap { @@ -1909,6 +1901,6 @@ } ////////////////// - case WRITE_UPT_REQ: // prepare the request to INIT_CMD FSM - // and write the first srcid in the FIFO + case WRITE_UPT_REQ: // prepare the coherence ransaction for the INIT_CMD FSM + // and write the first copy in the FIFO // send the request if only one copy { @@ -1958,4 +1950,15 @@ r_write_to_dec = false; } + +#if DEBUG_MEMC_WRITE +if( m_debug_write_fsm ) +{ + std::cout << " Post first request to INIT_CMD FSM" + << " / srcid = " << r_write_copy.read() + << " / inst = " << r_write_copy_inst.read() << std::endl; + if ( r_write_count.read() == 1) + std::cout << " ... and this is the last" << std::endl; +} +#endif } break; @@ -1973,5 +1976,5 @@ HeapEntry entry = m_heap.read(r_write_ptr.read()); - bool dec_upt_counter; // = r_write_to_dec.read(); + bool dec_upt_counter; if( (entry.owner.srcid != r_write_srcid.read()) or @@ -1979,5 +1982,5 @@ (entry.owner.cache_id != r_write_pktid.read()) or #endif - entry.owner.inst) // put te next srcid in the fifo + entry.owner.inst) // put te next srcid in the fifo { dec_upt_counter = false; @@ -1988,8 +1991,32 @@ write_to_init_cmd_fifo_cache_id = entry.owner.cache_id; #endif + +#if DEBUG_MEMC_WRITE +if( m_debug_write_fsm ) +{ + std::cout << " Post another request to INIT_CMD FSM" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << r_write_copy.read() + << " / inst = " << r_write_copy_inst.read() << std::endl; + if( entry.next == r_write_ptr.read() ) + std::cout << " ... and this is the last" << std::endl; +} +#endif } - else // the UPT counter must be decremented + else // the UPT counter must be decremented { dec_upt_counter = true; + +#if DEBUG_MEMC_WRITE +if( m_debug_write_fsm ) +{ + std::cout << " Skip one entry in heap matching the writer" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << r_write_copy.read() + << " / inst = " << r_write_copy_inst.read() << std::endl; + if( entry.next == r_write_ptr.read() ) + std::cout << " ... and this is the last" << std::endl; +} +#endif } @@ -2000,5 +2027,5 @@ { std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl - << "The write_to_cmd_write_fifo should not be full" << std::endl + << "The write_to_init_cmd_fifo should not be full" << std::endl << "as the depth should be larger than the max number of copies" << std::endl; exit(0); @@ -3939,27 +3966,7 @@ } ////////////////////// - case SC_DIR_HIT_WRITE: // write data in the cache - // and test if a coherence request is required - { - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - - // cache update - m_cache_data[way][set][word] = r_sc_wdata.read(); - if(r_sc_cpt.read()==4) - m_cache_data[way][set][word+1] = m_cmd_sc_wdata_fifo.read(); - - // monitor - if ( m_monitor_ok ) - { - vci_addr_t address = m_cmd_sc_addr_fifo.read(); - char buf[80]; - snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); - check_monitor( buf, address, r_sc_wdata.read() ); - if ( r_sc_cpt.read()==4 ) - check_monitor( buf, address+4, m_cmd_sc_wdata_fifo.read() ); - } - + case SC_DIR_HIT_WRITE: // test if a CC transaction is required + // write data in cache if no CC request + { // test coherence request if(r_sc_count.read()) // replicated line @@ -3981,6 +3988,24 @@ else // no copies { + size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + + // cache update + m_cache_data[way][set][word] = r_sc_wdata.read(); + if(r_sc_cpt.read()==4) + m_cache_data[way][set][word+1] = m_cmd_sc_wdata_fifo.read(); + + // monitor + if ( m_monitor_ok ) + { + vci_addr_t address = m_cmd_sc_addr_fifo.read(); + char buf[80]; + snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); + check_monitor( buf, address, r_sc_wdata.read() ); + if ( r_sc_cpt.read()==4 ) + check_monitor( buf, address+4, m_cmd_sc_wdata_fifo.read() ); + } r_sc_fsm = SC_RSP_SUCCESS; - } #if DEBUG_MEMC_SC @@ -3995,8 +4020,11 @@ } #endif + } break; } ///////////////// - case SC_UPT_LOCK: // register the transaction in UPT + case SC_UPT_LOCK: // try to register the transaction in UPT + // and write data in cache if successful registration + // releases locks to retry later if UPT full { if ( r_alloc_upt_fsm.read() == ALLOC_UPT_SC ) @@ -4021,8 +4049,28 @@ if (wok) // coherence transaction registered in UPT { + // cache update + size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + + m_cache_data[way][set][word] = r_sc_wdata.read(); + if(r_sc_cpt.read()==4) + m_cache_data[way][set][word+1] = m_cmd_sc_wdata_fifo.read(); + + // monitor + if ( m_monitor_ok ) + { + vci_addr_t address = m_cmd_sc_addr_fifo.read(); + char buf[80]; + snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); + check_monitor( buf, address, r_sc_wdata.read() ); + if ( r_sc_cpt.read()==4 ) + check_monitor( buf, address+4, m_cmd_sc_wdata_fifo.read() ); + } + r_sc_upt_index = index; r_sc_fsm = SC_UPT_HEAP_LOCK; } - else // releases the locks protecting UPT and DIR if no entry + else // releases the locks protecting UPT and DIR UPT full { r_sc_fsm = SC_WAIT; @@ -4213,5 +4261,6 @@ } /////////////////// - case SC_BC_UPT_LOCK: // Register a broadcast inval transaction in UPT + case SC_BC_UPT_LOCK: // register a broadcast inval transaction in UPT + // write data in cache in case of successful registration { if ( r_alloc_upt_fsm.read() == ALLOC_UPT_SC ) @@ -4238,4 +4287,23 @@ if ( wok ) // UPT not full { + // cache update + size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + + m_cache_data[way][set][word] = r_sc_wdata.read(); + if(r_sc_cpt.read()==4) + m_cache_data[way][set][word+1] = m_cmd_sc_wdata_fifo.read(); + + // monitor + if ( m_monitor_ok ) + { + vci_addr_t address = m_cmd_sc_addr_fifo.read(); + char buf[80]; + snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); + check_monitor( buf, address, r_sc_wdata.read() ); + if ( r_sc_cpt.read()==4 ) + check_monitor( buf, address+4, m_cmd_sc_wdata_fifo.read() ); + } r_sc_upt_index = index; r_sc_fsm = SC_BC_DIR_INVAL;