Changeset 224 for trunk/modules/vci_mem_cache_v4/caba/source
- Timestamp:
- Mar 30, 2012, 3:58:32 PM (13 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r223 r224 799 799 if( m_debug_tgt_cmd_fsm ) 800 800 { 801 std::cout << " <MEMC.TGT_CMD_IDLE> Receive command from srcid " << p_vci_tgt.srcid.read()802 << " / for address " << p_vci_tgt.address.read() << std::endl;801 std::cout << " <MEMC.TGT_CMD_IDLE> Receive command from srcid " << std::dec << p_vci_tgt.srcid.read() 802 << " / for address " << std::hex << p_vci_tgt.address.read() << std::endl; 803 803 } 804 804 #endif … … 849 849 std::cout << " <MEMC.TGT_CMD_READ> Push into read_fifo:" 850 850 << " address = " << std::hex << p_vci_tgt.address.read() 851 << " srcid = " << p_vci_tgt.srcid.read()851 << " srcid = " << std::dec << p_vci_tgt.srcid.read() 852 852 << " trdid = " << p_vci_tgt.trdid.read() 853 << " plen = " << p_vci_tgt.plen.read() << std::endl;853 << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 854 854 } 855 855 #endif … … 871 871 std::cout << " <MEMC.TGT_CMD_WRITE> Push into write_fifo:" 872 872 << " address = " << std::hex << p_vci_tgt.address.read() 873 << " srcid = " << p_vci_tgt.srcid.read()873 << " srcid = " << std::dec << p_vci_tgt.srcid.read() 874 874 << " trdid = " << p_vci_tgt.trdid.read() 875 << " wdata = " << p_vci_tgt.wdata.read()875 << " wdata = " << std::hex << p_vci_tgt.wdata.read() 876 876 << " be = " << p_vci_tgt.be.read() 877 << " plen = " << p_vci_tgt.plen.read() << std::endl;877 << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 878 878 } 879 879 #endif … … 901 901 std::cout << " <MEMC.TGT_CMD_ATOMIC> Pushing command into cmd_sc_fifo:" 902 902 << " address = " << std::hex << p_vci_tgt.address.read() 903 << " srcid = " << p_vci_tgt.srcid.read()903 << " srcid = " << std::dec << p_vci_tgt.srcid.read() 904 904 << " trdid = " << p_vci_tgt.trdid.read() 905 << " wdata = " << p_vci_tgt.wdata.read()905 << " wdata = " << std::hex << p_vci_tgt.wdata.read() 906 906 << " be = " << p_vci_tgt.be.read() 907 << " plen = " << p_vci_tgt.plen.read() << std::endl;907 << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 908 908 } 909 909 #endif … … 956 956 << " INIT_RSP_IDLE state" << std::endl 957 957 << "index too large for UPT: " 958 << " / rtrdid = " << p_vci_ini.rtrdid.read()959 << " / UPT size = " << m_update_tab.size() << std::endl;958 << " / rtrdid = " << std::dec << p_vci_ini.rtrdid.read() 959 << " / UPT size = " << std::dec << m_update_tab.size() << std::endl; 960 960 exit(0); 961 961 } … … 1092 1092 { 1093 1093 std::cout << " <MEMC.READ_IDLE> Read request:" 1094 << " srcid = " << std:: hex<< m_cmd_read_srcid_fifo.read()1095 << " / address = " << m_cmd_read_addr_fifo.read()1094 << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1095 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 1096 1096 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1097 1097 } … … 1142 1142 std::cout << " <MEMC.READ_DIR_LOCK> Accessing directory: " 1143 1143 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1144 << " / hit = " << entry.valid1144 << " / hit = " << std::dec << entry.valid 1145 1145 << " / count = " <<std::dec << entry.count 1146 1146 << " / is_cnt = " << entry.is_cnt << std::endl; … … 1439 1439 { 1440 1440 std::cout << " <MEMC.READ_RSP> Request the TGT_RSP FSM to return data:" 1441 << " rsrcid = " << std:: hex<< m_cmd_read_srcid_fifo.read()1442 << " / address = " << m_cmd_read_addr_fifo.read()1441 << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1442 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 1443 1443 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1444 1444 } … … 1503 1503 { 1504 1504 std::cout << " <MEMC.READ_TRT_SET> Write in Transaction Table: " << std::hex 1505 << " address = " << m_cmd_read_addr_fifo.read() 1506 << " / srcid = " << m_cmd_read_srcid_fifo.read() << std::endl; 1505 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1506 << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1507 << std::endl; 1507 1508 } 1508 1509 #endif … … 1527 1528 { 1528 1529 std::cout << " <MEMC.READ_TRT_REQ> Request GET transaction for address " 1529 << m_cmd_read_addr_fifo.read() << std::endl;1530 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; 1530 1531 } 1531 1532 #endif … … 1607 1608 { 1608 1609 std::cout << " <MEMC.WRITE_IDLE> Write request " 1609 << " srcid = " << std:: hex<< m_cmd_write_srcid_fifo.read()1610 << " / address = " << m_cmd_write_addr_fifo.read()1610 << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() 1611 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 1611 1612 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 1612 1613 } … … 1696 1697 std::cout << " <MEMC.WRITE_DIR_LOCK> Check the directory: " 1697 1698 << " address = " << std::hex << r_write_address.read() 1698 << " hit = " << entry.valid1699 << " count = " << std::dec <<entry.count1699 << " hit = " << std::dec << entry.valid 1700 << " count = " << entry.count 1700 1701 << " is_cnt = " << entry.is_cnt << std::endl; 1701 1702 } … … 1955 1956 { 1956 1957 std::cout << " <MEMC.WRITE_UPT_REQ> Post first request to INIT_CMD FSM" 1957 << " / srcid = " << r_write_copy.read()1958 << " / inst = " << r_write_copy_inst.read() << std::endl;1958 << " / srcid = " << std::dec << r_write_copy.read() 1959 << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; 1959 1960 if ( r_write_count.read() == 1) 1960 1961 std::cout << " ... and this is the last" << std::endl; … … 1997 1998 std::cout << " <MEMC.WRITE_UPT_NEXT> Post another request to INIT_CMD FSM" 1998 1999 << " / heap_index = " << std::dec << r_write_ptr.read() 1999 << " / srcid = " << r_write_copy.read()2000 << " / inst = " << r_write_copy_inst.read() << std::endl;2000 << " / srcid = " << std::dec << r_write_copy.read() 2001 << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; 2001 2002 if( entry.next == r_write_ptr.read() ) 2002 2003 std::cout << " ... and this is the last" << std::endl; … … 2013 2014 std::cout << " <MEMC.WRITE_UPT_NEXT> Skip one entry in heap matching the writer" 2014 2015 << " / heap_index = " << std::dec << r_write_ptr.read() 2015 << " / srcid = " << r_write_copy.read()2016 << " / inst = " << r_write_copy_inst.read() << std::endl;2016 << " / srcid = " << std::dec << r_write_copy.read() 2017 << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; 2017 2018 if( entry.next == r_write_ptr.read() ) 2018 2019 std::cout << " ... and this is the last" << std::endl; … … 2111 2112 { 2112 2113 std::cout << " <MEMC.WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = " 2113 << std:: hex<< r_write_srcid.read() << std::endl;2114 << std::dec << r_write_srcid.read() << std::endl; 2114 2115 if ( m_cmd_write_addr_fifo.rok() ) 2115 2116 { 2116 2117 std::cout << " New Write request: " 2117 << " srcid = " << std:: hex<< m_cmd_write_srcid_fifo.read()2118 << " / address = " << m_cmd_write_addr_fifo.read()2118 << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() 2119 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 2119 2120 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 2120 2121 } … … 3044 3045 { 3045 3046 std::cout << " <MEMC.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:" 3046 << " rsrcid = " << std:: hex<< r_xram_rsp_trt_buf.srcid3047 << " / address = " << r_xram_rsp_trt_buf.nline*m_words*43047 << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid 3048 << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 3048 3049 << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; 3049 3050 } … … 3149 3150 { 3150 3151 std::cout << " <MEMC.XRAM_RSP_HEAP_ERASE> Erase the list of copies:" 3151 << " srcid = " << entry.owner.srcid3152 << " / inst = " << entry.owner.inst << std::endl;3152 << " srcid = " << std::dec << entry.owner.srcid 3153 << " / inst = " << std::dec << entry.owner.inst << std::endl; 3153 3154 } 3154 3155 #endif … … 3233 3234 { 3234 3235 std::cout << " <MEMC.XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:" 3235 << " srcid = " << r_xram_rsp_trt_buf.srcid << std::endl;3236 << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; 3236 3237 } 3237 3238 #endif … … 3774 3775 { 3775 3776 std::cout << " <MEMC.CLEANUP_WRITE_RSP> Send a response to a cleanup request:" 3776 << " rsrcid = " << r_cleanup_write_srcid.read()3777 << " / rtrdid = " << r_cleanup_write_trdid.read() << std::endl;3777 << " rsrcid = " << std::dec << r_cleanup_write_srcid.read() 3778 << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read() << std::endl; 3778 3779 } 3779 3780 #endif … … 3792 3793 { 3793 3794 std::cout << " <MEMC.CLEANUP_RSP> Send the response to a cleanup request:" 3794 << " rsrcid = " << r_cleanup_write_srcid.read()3795 << " rsrcid = " << std::dec << r_cleanup_write_srcid.read() 3795 3796 << " / rtrdid = " << r_cleanup_write_trdid.read() << std::endl; 3796 3797 } … … 3838 3839 { 3839 3840 std::cout << " <MEMC.SC_IDLE> SC command: " << std::hex 3840 << " srcid = " << m_cmd_sc_srcid_fifo.read()3841 << " addr = " << m_cmd_sc_addr_fifo.read()3841 << " srcid = " << std::dec << m_cmd_sc_srcid_fifo.read() 3842 << " addr = " << std::hex << m_cmd_sc_addr_fifo.read() 3842 3843 << " wdata = " << m_cmd_sc_wdata_fifo.read() 3843 << " eop = " << m_cmd_sc_eop_fifo.read()3844 << " eop = " << std::dec << m_cmd_sc_eop_fifo.read() 3844 3845 << " cpt = " << std::dec << r_sc_cpt.read() << std::endl; 3845 3846 } … … 3902 3903 { 3903 3904 std::cout << " <MEMC.SC_DIR_LOCK> Directory acces" 3904 << " / address = " << m_cmd_sc_addr_fifo.read()3905 << " / hit = " << entry.valid3905 << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() 3906 << " / hit = " << std::dec << entry.valid 3906 3907 << " / count = " << entry.count 3907 3908 << " / is_cnt = " << entry.is_cnt << std::endl; … … 4169 4170 << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() 4170 4171 << " / wdata = " << std::hex << r_sc_wdata.read() 4171 << " / srcid = " << std:: hex<< r_sc_copy.read()4172 << " / inst = " << r_sc_copy_inst.read() << std::endl;4172 << " / srcid = " << std::dec << r_sc_copy.read() 4173 << " / inst = " << std::dec << r_sc_copy_inst.read() << std::endl; 4173 4174 } 4174 4175 #endif … … 4209 4210 << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() 4210 4211 << " / wdata = " << std::hex << r_sc_wdata.read() 4211 << " / srcid = " << std:: hex<< entry.owner.srcid4212 << " / inst = " << entry.owner.inst << std::endl;4212 << " / srcid = " << std::dec << entry.owner.srcid 4213 << " / inst = " << std::dec << entry.owner.inst << std::endl; 4213 4214 } 4214 4215 #endif … … 5008 5009 { 5009 5010 std::cout << " <MEMC.TGT_RSP_READ> Read response" 5010 << " / rsrcid = " << std:: hex<< r_read_to_tgt_rsp_srcid.read()5011 << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read() 5011 5012 << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() 5012 << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()5013 << " / rdata = " << std::hex << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() 5013 5014 << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; 5014 5015 } … … 5036 5037 { 5037 5038 std::cout << " <MEMC.TGT_RSP_WRITE> Write response" 5038 << " / rsrcid = " << r_write_to_tgt_rsp_srcid.read()5039 << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read() 5039 5040 << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() << std::endl; 5040 5041 } … … 5055 5056 { 5056 5057 std::cout << " <MEMC.TGT_RSP_CLEANUP> Cleanup response" 5057 << " / rsrcid = " << r_cleanup_to_tgt_rsp_srcid.read()5058 << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read() 5058 5059 << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() << std::endl; 5059 5060 } … … 5074 5075 { 5075 5076 std::cout << " <MEMC.TGT_RSP_SC> SC response" 5076 << " / rsrcid = " << r_sc_to_tgt_rsp_srcid.read()5077 << " / rsrcid = " << std::dec << r_sc_to_tgt_rsp_srcid.read() 5077 5078 << " / rtrdid = " << r_sc_to_tgt_rsp_trdid.read() << std::endl; 5078 5079 } … … 5094 5095 { 5095 5096 std::cout << " <MEMC.TGT_RSP_XRAM> Response following XRAM access" 5096 << " / rsrcid = " << r_xram_rsp_to_tgt_rsp_srcid.read()5097 << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read() 5097 5098 << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() 5098 << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()5099 << " / cpt = " << r_tgt_rsp_cpt.read() << std::endl;5099 << " / rdata = " << std::hex << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() 5100 << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; 5100 5101 } 5101 5102 #endif … … 5124 5125 { 5125 5126 std::cout << " <MEMC.TGT_RSP_INIT> Write response after coherence transaction" 5126 << " / rsrcid = " << r_init_rsp_to_tgt_rsp_srcid.read()5127 << " / rsrcid = " << std::dec << r_init_rsp_to_tgt_rsp_srcid.read() 5127 5128 << " / rtrdid = " << r_init_rsp_to_tgt_rsp_trdid.read() << std::endl; 5128 5129 }
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