Index: /trunk/platforms/tsarv1_mono_ring/Makefile
===================================================================
--- /trunk/platforms/tsarv1_mono_ring/Makefile	(revision 226)
+++ /trunk/platforms/tsarv1_mono_ring/Makefile	(revision 226)
@@ -0,0 +1,8 @@
+
+simulator.x: tsarv1_mono_ring_top.cpp tsarv1_mono_ring_desc
+	soclib-cc -P -p tsarv1_mono_ring_desc -I. -o simulator.x
+
+clean:
+	soclib-cc -x -p tsarv1_mono_ring_desc -I.
+	rm -rf *.o *.x tty*
+
Index: /trunk/platforms/tsarv1_mono_ring/segmentation.h
===================================================================
--- /trunk/platforms/tsarv1_mono_ring/segmentation.h	(revision 226)
+++ /trunk/platforms/tsarv1_mono_ring/segmentation.h	(revision 226)
@@ -0,0 +1,44 @@
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//	Author: Cesar Fuguet
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	RESET and EXCEPTION segments
+//      Base addresses required by MIPS processor
+
+#define	KCODE_BASE	0x80000000
+#define	KCODE_SIZE	0x00004000
+
+#define	KDATA_BASE	0x80100000
+#define	KDATA_SIZE	0x00004000
+
+#define	KUNC_BASE	0x80200000
+#define	KUNC_SIZE	0x00004000
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00004000
+
+/////////////////////////////////////////////////////////////////
+//	CODE and DATA and STACK segments
+
+#define	CODE_BASE	0x00000000
+#define	CODE_SIZE	0x00004000
+
+#define DATA_BASE	0x00100000
+#define DATA_SIZE	0x00004000
+
+#define STAK_BASE	0x00800000
+#define STAK_SIZE	0x00004000
+
+#define HEAP_BASE	0x00300000
+#define HEAP_SIZE	0x00004000
+
+//////////////////////////////////////////////////////////
+//	System devices
+
+#define	TTY_BASE	0x00F10000
+#define	TTY_SIZE	0x00000010
+
+#define	XICU_BASE	0x00F00000	
+#define XICU_SIZE	0x00001000
Index: /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/metadata/tsar_cluster_v1.sd
===================================================================
--- /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/metadata/tsar_cluster_v1.sd	(revision 226)
+++ /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/metadata/tsar_cluster_v1.sd	(revision 226)
@@ -0,0 +1,74 @@
+
+# -*- python -*-
+
+Module('caba:tsar_cluster_v1',
+  classname = 'soclib::caba::TsarClusterV1',
+  
+  tmpl_parameters = [
+    parameter.Module('vci_param', default = 'caba:vci_param'),
+    parameter.Int('cmd_width'),
+    parameter.Int('rsp_width'),
+  ],
+
+  header_files = [
+    '../source/include/tsar_cluster_v1.h'
+  ],
+
+  implementation_files = [
+    '../source/src/tsar_cluster_v1.cpp'
+  ],
+ 
+  uses = [
+    Uses('caba:base_module'),
+    Uses('common:loader'),
+    Uses('common:elf_file_loader'),
+    Uses('common:mapping_table'),
+    Uses(
+      'caba:vci_cc_xcache_wrapper_v1',
+      iss_t = 'common:gdb_iss',
+      gdb_iss_t = 'common:mips32el'
+    ),
+    Uses('caba:vci_mem_cache_v1'),
+    Uses('caba:vci_multi_tty'),
+    Uses('caba:vci_xicu'),
+    Uses(
+      'caba:vci_simple_ring_fast',
+      ring_cmd_data_size = parameter.Reference('cmd_width'),
+      ring_rsp_data_size = parameter.Reference('rsp_width')
+    )
+  ],
+
+  instance_parameters = [
+    parameter.Int('cluster_idx'),
+    parameter.Int('infifo_depth'),
+    parameter.Int('outfifo_depth'),
+    parameter.Int('x_local'),
+    parameter.Int('y_local'),
+    parameter.Int('x_width'),
+    parameter.Int('y_width'),
+    parameter.Module('md', 'common:mapping_table'),
+    parameter.Module('mc', 'common:mapping_table'),
+    parameter.Module('mx', 'common:mapping_table'),
+    parameter.Int('nprocs'),
+    parameter.Int('max_nprocs'),
+    parameter.Int('iwords'),
+    parameter.Int('iways'),
+    parameter.Int('isets'),
+    parameter.Int('dwords'),
+    parameter.Int('dways'),
+    parameter.Int('dsets'),
+    parameter.Int('mcwords'),
+    parameter.Int('mcways'),
+    parameter.Int('mcsets'),
+    parameter.Int('is_io'),
+  ], 
+
+  ports = [
+    Port('caba:clock_in'    , 'p_clk'           , auto = 'clock'  ),
+    Port('caba:bit_in'      , 'p_resetn'        , auto = 'resetn' ),
+
+    Port('caba:vci_initiator', 'p_vci_ixr')
+  ]
+)
+
+# vim: filetype=python : tabstop=2 : shiftwidth=2 : expandtab
Index: /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/include/tsar_cluster_v1.h
===================================================================
--- /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/include/tsar_cluster_v1.h	(revision 226)
+++ /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/include/tsar_cluster_v1.h	(revision 226)
@@ -0,0 +1,129 @@
+#ifndef TSAR_CLUSTER_V1_H
+#define TSAR_CLUSTER_V1_H
+
+#include <systemc.h>
+#include <iostream>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_multi_tty.h"
+#include "vci_mem_cache_v1.h"
+#include "vci_cc_xcache_wrapper_v1.h"
+#include "vci_xicu.h"
+#include "vci_simple_ring_fast.h"
+#include "gdbserver.h"
+#include "vci_initiator.h"
+
+///////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For processors, the local SRCID is between 0 & nprocs-1
+
+#define MEMC_TGTID	  0
+#define XICU_TGTID	  1
+#define MTTY_TGTID	  2
+
+#define PROC_SRCID    0
+
+namespace soclib { 
+  namespace caba {
+
+    template <typename vci_param, size_t cmd_width, size_t rsp_width>
+    class TsarClusterV1 : public soclib::caba::BaseModule {
+      public:
+        TsarClusterV1(
+          sc_module_name nm,
+
+          // Cluster Index
+          int cluster_idx,
+
+          // Dspin Routers parameters
+          int infifo_depth,
+          int outfifo_depth,
+          int x_local,
+          int y_local,
+
+          // Bits for global routing
+          size_t x_width,
+          size_t y_width,
+
+          // Mapping tables
+          const MappingTable & md,
+          const MappingTable & mc,
+          const MappingTable & mx,
+
+          // Processor Number
+          size_t nprocs,
+          size_t max_nprocs,
+         
+          // Cache L1 sizes
+          size_t iways,
+          size_t isets,
+          size_t iwords,
+          size_t dways,
+          size_t dsets,
+          size_t dwords,
+
+          // MemCache sizes
+          size_t mcways,
+          size_t mcsets,
+          size_t mcwords,
+
+          int    is_io,
+
+          Loader & loader
+        );
+
+        void print_trace();
+
+        ~TsarClusterV1();
+
+      private:
+        typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+
+        ///////////////////////////////////////////////////////////
+        // Components
+
+        VciSimpleRingFast<vci_param,cmd_width,rsp_width> * ringd;
+        VciSimpleRingFast<vci_param,cmd_width,rsp_width> * ringc;
+
+        VciCcXCacheWrapperV1<vci_param, proc_iss> ** procs;
+        VciMemCacheV1<vci_param>                  *  memc;
+        VciXicu<vci_param>                        *  xicu;
+        VciMultiTty<vci_param>                    *  mtty;
+
+        ////////////////////////////////////////////////////////////
+        // Signals
+
+        // Direct VCI Signals
+        VciSignals<vci_param> * signal_vci_ini_d;
+        VciSignals<vci_param> * signal_vci_tgt_d;
+
+        // Coherence VCI Signals
+        VciSignals<vci_param> * signal_vci_ini_c;
+        VciSignals<vci_param> * signal_vci_tgt_c;
+
+        // Interruptions
+        sc_signal<bool> * signal_proc_irq;
+        sc_signal<bool>   signal_mtty_irq;
+
+        sc_signal<bool>   signal_false;
+
+        size_t m_nprocs;
+
+      public:
+
+        ////////////////////////////////////////////////////////////
+        // Ports
+
+        sc_in<bool> p_clk;
+        sc_in<bool> p_resetn;
+
+        soclib::caba::VciInitiator<vci_param>   p_vci_ixr;
+    };
+  }
+}
+
+#endif
+
+// vim: tabstop=2 : shiftwidth=2 : expandtab
Index: /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/src/tsar_cluster_v1.cpp
===================================================================
--- /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/src/tsar_cluster_v1.cpp	(revision 226)
+++ /trunk/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/src/tsar_cluster_v1.cpp	(revision 226)
@@ -0,0 +1,265 @@
+#include "tsar_cluster_v1.h"
+
+#define DIRECT_TRACE
+#define COHERENCE_TRACE
+
+namespace soclib {
+  namespace caba {
+
+    template<typename vci_param, size_t cmd_width, size_t rsp_width>
+    TsarClusterV1<vci_param, cmd_width, rsp_width>::TsarClusterV1(
+      sc_module_name nm,
+
+      // Cluster Index
+      int cluster_idx,
+
+      // Dspin Routers parameters
+      int infifo_depth,
+      int outfifo_depth,
+      int x_local,
+      int y_local,
+
+      // Bits for global routing
+      size_t x_width,
+      size_t y_width,
+
+      // Mapping tables
+      const MappingTable & md,
+      const MappingTable & mc,
+      const MappingTable & mx,
+
+      // Processor Number
+      size_t nprocs,
+      size_t max_nprocs,
+     
+      // Cache L1 sizes
+      size_t iways,
+      size_t isets,
+      size_t iwords,
+      size_t dways,
+      size_t dsets,
+      size_t dwords,
+
+      // MemCache sizes
+      size_t mcways,
+      size_t mcsets,
+      size_t mcwords,
+
+      int    is_io,
+
+      Loader & loader
+    ) : soclib::caba::BaseModule(nm),
+        m_nprocs(nprocs)
+    {
+      std::ostringstream sd;
+      sd << "ringd_" << x_local << "_" << y_local;
+      ringd = new VciSimpleRingFast<vci_param, cmd_width, rsp_width> (
+        sd.str().c_str(),
+        md,                               // Direct Mapping Table
+        IntTab(),                         // Cluster index
+        2,                                // Wrapper fifo depth
+        nprocs,                           // Number of initiators
+        2 + is_io                         // Number of targets
+      );
+
+#ifdef DEBUG_TSAR_CLUSTER_V1
+      std::cout << ringd->name() << " instantiated" << std::endl;
+#endif
+
+      std::ostringstream sc;
+      sc << "ringc_" << x_local << "_" << y_local;
+      ringc = new VciSimpleRingFast<vci_param, cmd_width, rsp_width> (
+        sc.str().c_str(),
+        mc,                               // Direct Mapping Table
+        IntTab(),                         // Cluster index
+        2,                                // Wrapper fifo depth
+        nprocs + 1,                       // Number of initiators
+        max_nprocs + 1                    // Number of targets
+      );
+
+#ifdef DEBUG_TSAR_CLUSTER_V1
+      std::cout << ringc->name() << " instantiated" << std::endl;
+#endif
+
+      proc_iss::set_loader(loader);
+      procs = new VciCcXCacheWrapperV1<vci_param, proc_iss> * [nprocs];
+      for(size_t p=0; p < nprocs; p++) {
+        std::ostringstream sp;
+        sp << "proc_" << x_local << "_" << y_local << "_" << p;
+
+        procs[p] = new VciCcXCacheWrapperV1<vci_param, proc_iss> (
+          sp.str().c_str(),
+          p + nprocs*cluster_idx,         // Processor Id
+          md, mc,                         // Mapping Tables
+          IntTab(p),                      // SRCID_D
+          IntTab(p),                      // SRCID_C
+          IntTab(p),                      // TGTID_C
+          iways, isets, iwords,           // ICache Size
+          dways, dsets, dwords,           // DCache Size
+          x_width, y_width, max_nprocs    // Coherence Parameters
+        );
+    
+#ifdef DEBUG_TSAR_CLUSTER_V1
+        std::cout << procs[p]->name() << " instantiated" << std::endl;
+#endif
+      }
+
+      std::ostringstream sm;
+      sm << "memc_" << x_local << "_" << y_local;
+      memc = new VciMemCacheV1<vci_param> (
+        sm.str().c_str(),
+        md, mc, mx,                       // Mapping Tables
+        IntTab(0),                        // SRCID_X
+        IntTab(max_nprocs),               // SRCID_C
+        IntTab(0),                        // TGTID_D
+        IntTab(max_nprocs),               // TGTID_C
+        mcways, mcsets, mcwords           // MemCache Size  
+      );
+      
+#ifdef DEBUG_TSAR_CLUSTER_V1
+      std::cout << memc->name() << " instantiated" << std::endl;
+#endif
+
+      std::ostringstream sx;
+      sx << "xicu_" << x_local << "_" << y_local;
+      xicu = new VciXicu<vci_param> (
+        sx.str().c_str(),
+        md,
+        IntTab(1),                        // TGTID_D
+        nprocs,                           // number of TIMERS
+        is_io,                            // number of hard IRQs
+        nprocs,                           // number of soft IRQs
+        nprocs                            // number of output IRQ lines
+      );
+      
+#ifdef DEBUG_TSAR_CLUSTER_V1
+      std::cout << xicu->name() << " instantiated" << std::endl;
+#endif
+
+      std::ostringstream stty;
+      mtty = NULL;
+      if (is_io == 1) {
+        stty << "mtty_" << x_local << "_" << y_local;
+
+        mtty = new VciMultiTty<vci_param> (
+          stty.str().c_str(),
+          IntTab(2),
+          md,
+          "tty0", NULL
+        );
+
+#ifdef DEBUG_TSAR_CLUSTER_V1
+        std::cout << mtty->name() << " instantiated" << std::endl;
+#endif
+      }
+
+      //////////////////////////////////////////////////////////////
+      // Netlist
+
+      signal_vci_ini_d = alloc_elems<VciSignals<vci_param> >("s_vci_ini_d", nprocs);
+      signal_vci_tgt_d = alloc_elems<VciSignals<vci_param> >("s_vci_tgt_d", 2 + is_io);
+      signal_vci_ini_c = alloc_elems<VciSignals<vci_param> >("s_vci_ini_c", nprocs + 1);
+      signal_vci_tgt_c = alloc_elems<VciSignals<vci_param> >("s_vci_tgt_c", nprocs + 1);
+
+      signal_proc_irq  = new sc_signal<bool>[nprocs];
+
+      memc->p_clk               (p_clk);
+      memc->p_resetn            (p_resetn);
+      memc->p_vci_tgt           (signal_vci_tgt_d[0]);
+      memc->p_vci_ini           (signal_vci_ini_c[nprocs]);
+      memc->p_vci_tgt_cleanup   (signal_vci_tgt_c[max_nprocs]);
+      memc->p_vci_ixr           (p_vci_ixr);
+
+      for ( size_t p = 0 ; p < nprocs ; p++ ) {
+        procs[p]->p_clk        (p_clk);  
+        procs[p]->p_resetn     (p_resetn);  
+        procs[p]->p_vci_ini_rw (signal_vci_ini_d[p]);
+        procs[p]->p_vci_ini_c  (signal_vci_ini_c[p]);
+        procs[p]->p_vci_tgt    (signal_vci_tgt_c[p]);
+        procs[p]->p_irq[0]     (signal_proc_irq[p]);
+
+        for ( size_t j = 1 ; j < 6 ; j++ ) {
+          procs[p]->p_irq[j]   (signal_false); 
+        }
+      }
+
+      // XICU
+      xicu->p_clk       (p_clk);
+      xicu->p_resetn    (p_resetn);
+      xicu->p_vci       (signal_vci_tgt_d[1]);
+
+      if(is_io == 1) {
+        xicu->p_hwi[0]  (signal_mtty_irq);
+
+        mtty->p_clk     (p_clk);
+        mtty->p_resetn  (p_resetn);
+        mtty->p_vci     (signal_vci_tgt_d[2]);
+        mtty->p_irq[0]  (signal_mtty_irq);
+      }
+
+      for ( size_t p = 0 ; p < nprocs ; p++ ) {
+        xicu->p_irq[p]  (signal_proc_irq[p]);
+      }
+
+      // Direct ring
+      ringd->p_clk                    (p_clk);
+      ringd->p_resetn                 (p_resetn);
+
+      for ( size_t p = 0 ; p < nprocs ; p++ ) {
+        ringd->p_to_initiator[p]      (signal_vci_ini_d[p]);
+      }
+
+      for ( int t = 0 ; t < (2 + is_io) ; t++ ) {
+        ringd->p_to_target[t]         (signal_vci_tgt_d[t]);
+      }
+
+      // Coherence ring
+      ringc->p_clk                    (p_clk);
+      ringc->p_resetn                 (p_resetn);
+
+      for ( size_t i = 0 ; i < (nprocs + 1) ; i++ ) {
+        ringc->p_to_initiator[i]      (signal_vci_ini_c[i]);
+      }
+
+      for ( size_t t = 0 ; t < (max_nprocs + 1) ; t++ ) {
+        ringc->p_to_target[t]         (signal_vci_tgt_c[t]);
+      }
+    } // End TsarClusterV1
+
+    template<typename vci_param, size_t cmd_width, size_t rsp_width>
+    void TsarClusterV1<vci_param, cmd_width, rsp_width>::print_trace() {
+      #ifdef DIRECT_TRACE
+      ringd->print_trace();
+      #endif
+      #ifdef COHERENCE_TRACE
+      ringc->print_trace();
+      #endif
+    }
+
+    template<typename vci_param, size_t cmd_width, size_t rsp_width>
+    TsarClusterV1<vci_param, cmd_width, rsp_width>::~TsarClusterV1() {
+      for(size_t p=0; p < m_nprocs; p++) {
+        delete procs[p];
+      }
+      delete [] procs;
+      delete ringd;
+      delete ringc;
+      delete memc;
+      delete xicu;
+
+      if(mtty) {
+        delete mtty;
+        dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_d, 3);
+      } else {
+        dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_d, 2);
+      }
+
+      dealloc_elems<VciSignals<vci_param> >(signal_vci_ini_d, m_nprocs);
+      dealloc_elems<VciSignals<vci_param> >(signal_vci_ini_c, m_nprocs + 1);
+      dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_c, m_nprocs + 1);
+      delete [] signal_proc_irq;
+    }
+  }
+}
+
+// vim: tabstop=2 : shiftwidth=2 : expandtab
Index: /trunk/platforms/tsarv1_mono_ring/tsarv1_mono_ring_desc
===================================================================
--- /trunk/platforms/tsarv1_mono_ring/tsarv1_mono_ring_desc	(revision 226)
+++ /trunk/platforms/tsarv1_mono_ring/tsarv1_mono_ring_desc	(revision 226)
@@ -0,0 +1,24 @@
+
+# -*- python -*-
+
+todo = Platform(
+  'caba', 'tsarv1_mono_ring_top.cpp',
+  uses = [
+      Uses('caba:tsar_cluster_v1', cmd_width = 40, rsp_width = 33),
+      Uses('caba:vci_simple_ram'),
+      Uses('common:elf_file_loader'),
+  ],
+
+  cell_size = 4,
+  plen_size = 8,
+  addr_size = 32,
+  rerror_size = 1,
+  clen_size = 1,
+  rflag_size = 1,
+  srcid_size = 5,
+  pktid_size = 4,
+  trdid_size = 4,
+  wrplen_size = 1,
+)
+
+# vim: tabstop=2 : shiftwidth=2 : expandtab
Index: /trunk/platforms/tsarv1_mono_ring/tsarv1_mono_ring_top.cpp
===================================================================
--- /trunk/platforms/tsarv1_mono_ring/tsarv1_mono_ring_top.cpp	(revision 226)
+++ /trunk/platforms/tsarv1_mono_ring/tsarv1_mono_ring_top.cpp	(revision 226)
@@ -0,0 +1,421 @@
+/////////////////////////////////////////////////////////////////////////
+// File:      tsarv1_mono_ring_top.cpp
+// Author:    Cesar Fuguet / Abdelmalek Simerabe
+// Copyright: UPMC/LIP6
+// Date :     2012
+//
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "tsar_cluster_v1.h"
+#include "mapping_table.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_simple_ram.h"
+#include "segmentation.h"
+
+///////////////////////////////////
+// flit widths for the ring network
+
+#define cmd_width	    40
+#define rsp_width	    33
+
+//////////////////
+// VCI format
+
+#define cell_width	  4
+#define address_width	32
+#define plen_width	  8
+#define error_width	  1
+#define clen_width	  1
+#define rflag_width	  1
+#define srcid_width	  5
+#define pktid_width	  4
+#define trdid_width	  4
+#define wrplen_width  1
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+
+    char    soft_name[128]  = "undefined_binary_file";  // pathname to binary code
+    size_t  ncycles         = 200000;           	      // simulated cycles
+    size_t  xmax            = 1;         		            // number of clusters in a row
+    size_t  ymax            = 1;                	      // number of clusters in a column
+    size_t  nprocs          = 1;         		            // number of processors per cluster
+    bool    debug_ok        = false;            	      // debug activated
+    size_t  from_cycle      = 0;                      	// debug start cycle
+    size_t  to_cycle        = 200000;           	      // debug end cycle
+
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( (nprocs <= 8) 
+                    && "The number of processors per cluster cannot be larger than 8");
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+            {
+                debug_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) )
+            {
+                to_cycle = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) ";
+                std::cout << "couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT elf_file_name" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+                std::cout << "     -TOCYCLE debug_end_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    std::cout << std::endl << "***********  TSAR ARCHITECTURE  **************" << std::endl
+              << " - Interconnect = DSPIN & RING" << std::endl
+              << " - Number of clusters = " << xmax << " * " << ymax << std::endl
+              << " - Number of processors per cluster = " << nprocs << std::endl
+              << "**********************************************" << std::endl
+              << std::endl;
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    size_t x_width = 0;
+    size_t y_width = 0;
+
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(16 - x_width - y_width), 
+                         IntTab(srcid_width - x_width - y_width), 
+                         0x00FF0000);
+
+    maptabd.add(
+        Segment("d_seg_xicu", 
+          XICU_BASE,
+          XICU_SIZE, 
+          IntTab(XICU_TGTID), 
+          false
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_stak",
+          STAK_BASE,
+          STAK_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_mtty",
+          TTY_BASE,
+          TTY_SIZE,
+          IntTab(MTTY_TGTID),
+          false
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_reset",
+          RESET_BASE,
+          RESET_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_kcode",
+          KCODE_BASE,
+          KCODE_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_kdata",
+          KDATA_BASE,
+          KDATA_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_kunc",
+          KUNC_BASE,
+          KUNC_SIZE,
+          IntTab(MEMC_TGTID),
+          false
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_code",
+          CODE_BASE,
+          CODE_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_data",
+          DATA_BASE,
+          DATA_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    MappingTable maptabc(address_width,
+        IntTab(srcid_width - x_width - y_width),
+        IntTab(srcid_width - x_width - y_width),
+        0xFF000000);
+
+    std::ostringstream sm;
+    sm << "c_seg_memc_" << 0 << "_" << 0;
+    maptabc.add(
+        Segment(sm.str(),
+          (nprocs << (address_width - srcid_width)),
+          0xC,
+          IntTab(nprocs),
+          false
+          )
+        );
+
+    for ( size_t p = 0 ; p < nprocs ; p++)
+    {
+      std::ostringstream sp;
+      sp << "c_seg_proc_" << 0 << "_" << 0 << "_" << p;
+      maptabc.add(
+          Segment(sp.str(),
+            (p << (address_width - srcid_width)),
+            0xC,
+            IntTab(p),
+            false
+            )
+          );
+    }
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(
+      address_width,
+      IntTab(x_width + y_width),
+      IntTab(x_width + y_width),
+      0x00FF0000
+    );
+
+    maptabx.add(
+      Segment("x_seg_kcode",
+        KCODE_BASE,
+        KCODE_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_kdata",
+        KDATA_BASE,
+        KDATA_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_kunc",
+        KUNC_BASE,
+        KUNC_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_code",
+        CODE_BASE,
+        CODE_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_reset",
+        RESET_BASE,
+        RESET_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_data",
+        DATA_BASE,
+        DATA_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+    
+    maptabx.add(
+        Segment("x_seg_stak",
+          STAK_BASE,
+          STAK_SIZE,
+          IntTab(0),
+          false
+          )
+        );
+    std::cout << maptabx << std::endl;
+
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock		    signal_clk("clk");
+    sc_signal<bool> signal_resetn("resetn");
+
+    // Xternal network VCI signals
+    VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram");
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+    soclib::common::Loader loader(soft_name);
+
+    cout << loader << endl;
+
+    // TSAR Clusters
+    TsarClusterV1<vci_param, cmd_width, rsp_width> * cluster;
+    std::ostringstream scluster;
+    scluster << "cluster_" << 0 << "_" << 0;
+
+    cluster = new TsarClusterV1<vci_param, cmd_width, rsp_width> (
+        scluster.str().c_str(),
+        0,                          // Cluster index
+        4,4,                        // Router fifo's depth
+        0,0,                        // X, Y coordinates
+        x_width, y_width,           // Global routing bits
+        maptabd, maptabc, maptabx,  // Mapping Tables
+        nprocs,                     // Number of processors in the cluster
+        nprocs,                     // Maximum number of processors per cluster
+        4,32,16,/**/4,32,16,  		  // Icache and Dcache sizes
+        4,32,16,				            // MemCache size
+        1,                          // Is IO cluster
+        loader                      // Program Loader
+        ); 
+
+    // External RAM
+    VciSimpleRam<vci_param> xram(
+        "xram", 
+        IntTab(0), 
+        maptabx, 
+        loader);
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // External Ram (one instance)
+    xram.p_clk						(signal_clk);
+    xram.p_resetn					(signal_resetn);
+    xram.p_vci						(signal_vci_tgt_x_xram);	
+
+    // Connection with the external network
+    cluster->p_vci_ixr(signal_vci_tgt_x_xram);
+
+    // Clock and Reset
+    cluster->p_clk(signal_clk);
+    cluster->p_resetn(signal_resetn);
+
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+
+    for(size_t i=1 ; i<ncycles ; i++)
+    {
+        sc_start(sc_core::sc_time(1, SC_NS));
+
+        if(debug_ok) {
+          cluster->print_trace();
+        }
+    }
+
+    std::cout << "Hit ENTER to end simulation" << std::endl;
+    char buf[1];
+    std::cin.getline(buf,1);
+
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
+
+// vim: tabstop=2 shiftwidth=2 expandtab softtabstop=2