Index: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 229)
+++ trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 230)
@@ -689,5 +689,5 @@
         r_mmu_mode = 0x3;
 
-	// No request from ICACHE FSM to CMD FSM
+	    // No request from ICACHE FSM to CMD FSM
         r_icache_miss_req          = false;
         r_icache_unc_req           = false;
@@ -712,5 +712,5 @@
 
         // No LL reservation
-	r_dcache_ll_valid          = false;
+	    r_dcache_ll_valid          = false;
 
         // No processor XTN request pending
@@ -1964,12 +1964,12 @@
     {
     case DCACHE_IDLE:	// There is 8 conditions to exit the IDLE state :
-    			// 1) Dirty bit update (processor)	=> DCACHE_DIRTY_GET_PTE
-    			// 2) Coherence request (TGT FSM) 	=> DCACHE_CC_CHECK 
-    			// 3) ITLB miss request (ICACHE FSM) 	=> DCACHE_TLB_MISS
-    			// 4) XTN request (processor)		=> DCACHE_XTN_*
-    			// 5) DTLB miss (processor) 		=> DCACHE_TLB_MISS
-    			// 6) Cacheable read miss (processor)  	=> DCACHE_MISS_VICTIM
-    			// 7) Uncacheable read (processor) 	=> DCACHE_UNC_WAIT 
-    			// 8) SC access (processor)		=> DCACHE_SC_WAIT
+						// 1) Dirty bit update (processor)	=> DCACHE_DIRTY_GET_PTE
+						// 2) Coherence request (TGT FSM) 	=> DCACHE_CC_CHECK 
+						// 3) ITLB miss request (ICACHE FSM) 	=> DCACHE_TLB_MISS
+						// 4) XTN request (processor)		=> DCACHE_XTN_*
+						// 5) DTLB miss (processor) 		=> DCACHE_TLB_MISS
+						// 6) Cacheable read miss (processor)  	=> DCACHE_MISS_VICTIM
+						// 7) Uncacheable read (processor) 	=> DCACHE_UNC_WAIT 
+						// 8) SC access (processor)		=> DCACHE_SC_WAIT
                         //
                         // The dtlb is unconditionally accessed to translate the
@@ -2532,4 +2532,6 @@
                     // If dcache miss, we go to DCACHE_MISS_VICTIM state.
                     // If uncacheable, we go to DCACHE_UNC_WAIT state.
+                    // In case of LL, the LL registration is done when the data is returned:
+                    // in DCACHE_IDLE if cacheable / in DCACHE_UNC_WAIT if uncacheable 
                     if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL)) 
                         and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
@@ -2570,4 +2572,12 @@
                                 m_drsp.valid   = true;
                                 m_drsp.rdata   = cache_rdata;
+
+                                // makes reservation in case of LL
+                                if ( m_dreq.type == iss_t::DATA_LL )
+                                {
+                                    r_dcache_ll_valid = true;
+                                    r_dcache_ll_vaddr = m_dreq.addr;
+                                    r_dcache_ll_data  = cache_rdata;
+                                }
 #if DEBUG_DCACHE
 if ( m_debug_dcache_fsm )
@@ -2586,11 +2596,4 @@
                         }
 
-                        // makes reservation in case of LL
-                        if ( m_dreq.type == iss_t::DATA_LL )
-                        {
-                            r_dcache_ll_valid = true;
-                            r_dcache_ll_data  = cache_rdata;
-                            r_dcache_ll_vaddr = m_dreq.addr;
-                        }
                         r_dcache_p0_valid = false;
                     } // end READ or LL
@@ -2666,5 +2669,5 @@
                             {
                                 // The PTE physical address is obtained from the nline value (dtlb),
-                                // and the word index (proper bits of the virtual address)
+                                // and the word index (virtual address)
                                 if ( tlb_flags.b )	// PTE1
                                 {
@@ -3867,15 +3870,25 @@
             break;
         }
-	else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
-	{
+	    else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
+	    {
+            // consume data 
             vci_rsp_fifo_dcache_get = true;     
             r_dcache_fsm            = DCACHE_IDLE;
-            // we acknowledge the processor request if it has not been modified
+
+            // acknowledge the processor request if it has not been modified
             if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
             {
-	        m_drsp.valid          = true;
-	        m_drsp.rdata          = r_vci_rsp_fifo_dcache.read();
-            }
-	}	
+	            m_drsp.valid          = true;
+	            m_drsp.rdata          = r_vci_rsp_fifo_dcache.read();
+
+                // makes reservation in case of LL
+                if ( m_dreq.type == iss_t::DATA_LL )
+                {
+                    r_dcache_ll_valid = true;
+                    r_dcache_ll_data  = r_vci_rsp_fifo_dcache.read();
+                    r_dcache_ll_vaddr = m_dreq.addr;
+                }
+            }
+	    }	
         break;
     }