Index: /trunk/softs/tests_ccvcache_v4/Makefile.inc
===================================================================
--- /trunk/softs/tests_ccvcache_v4/Makefile.inc	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/Makefile.inc	(revision 232)
@@ -0,0 +1,27 @@
+all: test.elf
+
+COMMON= ../common
+LDSCRIPT?= ../common/ldscript
+
+CC= mipsel-unknown-elf-gcc
+LD= mipsel-unknown-elf-ld
+DU= mipsel-unknown-elf-objdump
+
+CFLAGS= -mips32 -nostdinc -I. -I${COMMON} -mno-abicalls
+### LDFLAGS=-mips32 -nostdlib -Wl,-T${LDSCRIPT} -Ttext=0xbfc00000
+
+#### object files generation
+test.o: test.S 
+	${CC} ${CFLAGS} -c -o $@ $<
+	${DU} -D $@ > $@.txt
+
+subr.o: ${COMMON}/subr.S
+	${CC} ${CFLAGS} -c -o $@ $<
+	${DU} -D $@ > $@.txt
+
+### linking : test.o has to be the first object 
+test.elf: test.o subr.o ${EXTRA_OBJ}
+	${LD} -o $@ -T ${LDSCRIPT} -Ttext 0xbfc00000 $^
+	${DU} -D $@ > $@.txt
+clean:
+	rm -f *.o test.elf *.txt run.out temp
Index: /trunk/softs/tests_ccvcache_v4/README
===================================================================
--- /trunk/softs/tests_ccvcache_v4/README	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/README	(revision 232)
@@ -0,0 +1,49 @@
+This is a very basic framework for running regression tests against
+a mips32+vcache2 platform. Here's the layout of this directory:
+
+plaform/
+	contains the soclib platform description and simulation executable.
+	It should be compiled before starting tests.
+	It includes a very simple component "vci_exit". It has a single
+	write-only 32bit register. When a value is written, the
+	caba code does a "exit(data)", using the value written to
+	the register. This allows to stop the simulator from software
+	and pass an exit value to the calling shell. The framework uses
+	this (with other things, see below) to determine if a test
+	is successfull. The simulator will exit with a non-0 exit status
+	after 100000 cycles (and a message to stderr), so the tests are
+	expected to be simple.
+	The platform has a tty, which is redirected to a file along with
+	the simlulator's output. The test framework may search for specific
+	strings in this file to determine if a test was successfull.
+common/
+	Some common functions, ldscripts, etc ... used by the tests.
+	It has a subr.S which holds usefull subroutines, such as
+	print() and printx().
+Makefile.inc
+	included from the test's Makefiles. Basic stuff to compile a
+	mips32 ELF executable for a test. It expects a test.S,
+	add the subr.S from common and eventually additionnal object
+	files.
+test_*/
+	these directories holds the test themselves. They have a run
+	script which does what is needed to compile and run a test,
+	print "test failed" or "test passed" on stdout, and clean the
+	directory if it's successfull. A sample script will call
+	make, then run the simulator with srdout/stderr redirected
+	to a file. If the simulator exists with a 0 status, this
+	script search for some strings in the output (that the
+	test program would have printed). This is an additionnal way
+	to check that all worked properly.
+	Tests are written in assembly; as we're testing for very specific
+	conditions (such as an instruction in a branch's delay slot on
+	a page boundary), we don't want the compiler to optimise things
+	or otherwise reorder instructions.
+	If the test was successfull, the 'run' script cleanups the
+	directory. Otherwise the 'run.out' file is available to
+	start looking at what's wrong.
+run_tests
+	runs all the test_*/run scripts - the goal being that
+	all of them print "test passsed" :). Directories are explicitely
+	listed in the run_tests script (order does matter to have a readable
+	output)
Index: /trunk/softs/tests_ccvcache_v4/bilan
===================================================================
--- /trunk/softs/tests_ccvcache_v4/bilan	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/bilan	(revision 232)
@@ -0,0 +1,106 @@
+-n test_sanity: 
+test passsed
+-n test_exceptions: 
+test passsed
+-n test_mmu_basic: 
+test passsed
+-n test_excep_ls: 
+test passsed
+-n test_excep_ls_delayslot: 
+test passsed
+-n test_excep_ls_llsc: 
+test passsed
+-n test_excep_if: 
+test passsed
+-n test_excep_if_delayslot: 
+test passsed
+-n test_excep_if_llsc: 
+test passsed
+-n test_exception_epc_modify: 
+test passsed
+-n test_dtlb_inval: 
+test passsed
+-n test_dtlb_inval2: 
+test passsed
+-n test_dtlb_inval3: 
+test passsed
+-n test_itlb_inval: 
+test passsed
+-n test_itlb_inval2: 
+test passsed
+-n test_idtlb_inval: 
+test passsed
+-n test_idtlb_inval2: 
+test passsed
+-n test_idtlb_inval3: 
+test passsed
+-n test_idtlb_inval4: 
+test passsed
+-n test_dtlb_ptprinval: 
+test passsed
+-n test_itlb_ptprinval: 
+test passsed
+-n test_idtlb_ptprinval: 
+test passsed
+-n test_sync: 
+test passsed
+-n test_sc_update_cache: 
+test passsed
+-n test_pte_llsc: 
+test passsed
+-n test_interrupt: 
+test passsed
+-n test_interrupt_epc_modify: 
+test passsed
+-n test_xicu_timer: 
+test passsed
+-n test_interrupt_delayslot: 
+test FAILED
+-n test_interrupt_mask: 
+test passsed
+-n test_interrupt_external_mask: 
+test passsed
+-n test_excep_cop: 
+test passsed
+-n test_excep_cop_delayslot: 
+test passsed
+-n test_excep_cop1: 
+test passsed
+-n test_syscall: 
+test passsed
+-n test_syscall_delayslot: 
+test passsed
+-n test_breakpoint: 
+test passsed
+-n test_breakpoint_delayslot: 
+test passsed
+-n test_ri: 
+test passsed
+-n test_ri_delayslot: 
+test passsed
+-n test_ao: 
+test passsed
+-n test_ao_delayslot: 
+test passsed
+-n test_trap: 
+test passsed
+-n test_trap_delayslot: 
+test passsed
+-n test_fpediv: 
+test FAILED
+-n test_fpe_delayslot: 
+test FAILED
+-n test_dcache_inval_pa: 
+test passsed
+-n test_icache_inval_pa: 
+test passsed
+-n test_pte2i_ref: 
+test passsed
+-n test_pte2lw_ref: 
+test passsed
+-n test_pte2ll_ref: 
+test passsed
+-n test_pte2sw_dirty: 
+test passsed
+-n test_pte2sc_dirty: 
+test passsed
Index: /trunk/softs/tests_ccvcache_v4/common/common.sh
===================================================================
--- /trunk/softs/tests_ccvcache_v4/common/common.sh	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/common/common.sh	(revision 232)
@@ -0,0 +1,3 @@
+SIMUL=../../../platforms/tsarv4_mono_mmu/simul.x
+
+#SIMUL=../../../../soclib-svn-june-2009/soclib/soclib/platform/topcells/caba_vgsb_almo_mmu/simul.x
Index: /trunk/softs/tests_ccvcache_v4/common/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/common/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/common/ldscript	(revision 232)
@@ -0,0 +1,65 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/common/misc.h
===================================================================
--- /trunk/softs/tests_ccvcache_v4/common/misc.h	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/common/misc.h	(revision 232)
@@ -0,0 +1,49 @@
+/* multi-tty definitions */
+#define TTY_BASE 0xd0200000
+#define TTY_WRITE  0
+#define TTY_STATUS 1
+#define TTY_READ 2
+
+/* vci_exit definitions */
+#define EXIT_BASE 0xe0000000
+
+#define BOOT_ADDRESS 0xbfc00000
+#define EXCEP_ADDRESS 0xbfc00380
+
+/* vci dma */
+#define DMA_BASE 	0xe8000000
+#define DMA_SRC  	0
+#define DMA_DST  	4
+#define DMA_LEN  	8
+#define DMA_RESET	12
+
+/* cop0 definitions */
+#define COP_0_BADVADDR	$8
+#define COP0_STATUS	$12
+#define COP0_CAUSE	$13
+#define COP0_EXPC	$14
+
+/* easy print macros */
+#define PRINT(str) \
+        la      a0, str;\
+	jal     print; \
+	nop
+
+#define PRINTX \
+	jal     printx;\
+	nop
+
+#define PUTCHAR(c) li a0, c; sb a0, 0(k0)
+
+#define EXIT(a) \
+	li a0, a; \
+	sw a0, 4(k1); \
+	1:      j 1b; \
+	nop
+
+/* some magic numers to test */
+#define MAGIC1	0xdead
+#define MAGIC2	0xbeef
+#define MAGIC3	0x900d
+#define MAGIC4	0xf00d
+
Index: /trunk/softs/tests_ccvcache_v4/common/registers.h
===================================================================
--- /trunk/softs/tests_ccvcache_v4/common/registers.h	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/common/registers.h	(revision 232)
@@ -0,0 +1,32 @@
+#define zero	$0
+#define at	$at
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26
+#define k1	$27
+#define gp	$28
+#define sp	$29
+#define fp	$30
+#define ra	$31
Index: /trunk/softs/tests_ccvcache_v4/common/subr.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/common/subr.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/common/subr.S	(revision 232)
@@ -0,0 +1,56 @@
+#include <registers.h>
+/* test common subroutines
+
+	.text
+/*
+ * void print(char *): print a string to the multitty.
+ * assumes k0 points to the tty base.
+ */
+	.globl print
+print:
+	.set noreorder
+	move	t0, a0
+1:
+	lb	t1, 0(t0);
+	beq	t1, zero, end
+	nop
+	sb	t1, 0(k0)
+	addiu	t0, t0, 1
+	j	1b
+	nop
+end:
+	jr	ra
+	nop
+
+/*
+ * void printx(uint32_t): print a number in hex to the multitty
+ * assumes points to the tty base.
+ */
+	.globl printx
+printx:
+	.set noreorder
+	move	t0, a0
+	li	t1, '0'
+	sb	t1, 0(k0)
+	li	t1, 'x'
+	sb	t1, 0(k0)
+	li	t1, 8
+1:
+	lui	t2, 0xf000;
+	and	t2, t0, t2
+	srl	t2, t2, 28
+	slti	t3, t2, 0xa
+	beq	t3, zero, 2f /* in range A-F */
+	nop
+	addi	t2, t2, '0'
+	j	3f
+	nop
+2:
+	addi    t2, t2, 'A' - 0xa
+3:
+	sb      t2, 0(k0)
+	addi	t1, t1, -1
+	bgtz	t1, 1b
+	sll	t0, t0, 4
+	jr	ra
+	nop
Index: /trunk/softs/tests_ccvcache_v4/common/vcache.h
===================================================================
--- /trunk/softs/tests_ccvcache_v4/common/vcache.h	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/common/vcache.h	(revision 232)
@@ -0,0 +1,66 @@
+/* cop2/vcache definitions */
+#define VC_PTPR			$0 		/* set Page Table Pointer Register */
+#define VC_TLB_EN		$1 		/* set Data & Inst TLBs Mode Register */
+#define	  VC_TLB_EN_ITLB		0x8 	/* enable instruction TLB */
+#define	  VC_TLB_EN_DTLB		0x4 	/* enable data TLB */
+#define	  VC_TLB_EN_ICACHE		0x2 	/* enable instruction cache */
+#define	  VC_TLB_EN_DCACHE		0x1 	/* enable data cache */
+#define VC_ICACHE_FLUSH 	$2 		/* Instruction Cache flush */
+#define VC_DCACHE_FLUSH 	$3 		/* Data Cache flush */
+#define VC_ITLB_INVAL		$4 		/* Instruction TLB line invalidate */
+#define VC_DTLB_INVAL		$5 		/* Data TLB line invalidate */
+#define VC_ICACHE_INVAL 	$6 		/* Instruction Cache line invalidate */
+#define VC_DCACHE_INVAL 	$7 		/* Data Cache line invalidate */
+#define VC_ICACHE_PREFETCH 	$8 		/* Instruction Cache line prefetch */
+#define VC_DCACHE_PREFETCH 	$9 		/* Data Cache line prefetch */
+#define VC_SYNC			$10 		/* Complete pending writes */
+#define VC_IERR_TYPE		$11 		/* Instruction Exception type Register */
+#define VC_DERR_TYPE		$12 		/* Data Exception type Register */
+#define VC_DATA_LO		$17 		/* misc register low */
+#define VC_DATA_HI		$18 		/* misc register hight */
+#define VC_ICACHE_INVAL_PA 	$19 		/* misc register hight */
+#define VC_DCACHE_INVAL_PA 	$20 		/* misc register hight */
+#define	  VC_ERR_PT1_UNMAPPED		0x001 	/* Page fault on Table1 (invalid PTE) */
+#define	  VC_ERR_PT2_UNMAPPED		0x002 	/* Page fault on Table 2 (invalid PTE) */
+#define	  VC_ERR_PRIVILEGE_VIOLATION	0x004 	/* Protected access in user mode */
+#define	  VC_ERR_WRITE_VIOLATION	0x008 	/* Write access to a non write page */
+#define	  VC_ERR_EXEC_VIOLATION		0x010 	/* Exec access to a non exec page */
+#define	  VC_ERR_UNDEFINED_XTN		0x020 	/* Undefined external access address */
+#define	  VC_ERR_PT1_ILLEGAL_ACCESS	0x040 	/* Bus Error in Table1 access */
+#define	  VC_ERR_PT2_ILLEGAL_ACCESS	0x080 	/* Bus Error in Table2 access */
+#define	  VC_ERR_CACHE_ILLEGAL_ACCESS	0x100 	/* Bus Error during the cache access */
+#define VC_I_BAD_VADDR		$13 		/* Instruction Bad Virtual Address Register */
+#define VC_D_BAD_VADDR		$14 		/* Data Bad Virtual Address Register */
+#define VC_DATA_L		$17 		/* cache parameters */
+#define VC_DATA_H		$18 		/* cache parameters */
+#define VC_ICACHE_INVAL_PA	$19 		/* icache inval per physical address */
+#define VC_DCACHE_INVAL_PA	$20 		/* dcache inval per physical address */
+
+/* vcache page level 1 format */
+#define PTE1_V  (1 << 31)       		/* entry valid */
+#define PTE1_T  (1 << 30)       		/* 0 == entry is a PTE1 (maps a 2M page) */
+#define PTE1_L  (1 << 29)       		/* accessed by local CPU */
+#define PTE1_R  (1 << 28)       		/* accessed by remote CPU */
+#define PTE1_C  (1 << 27)       		/* cachable */
+#define PTE1_W  (1 << 26)       		/* writable */
+#define PTE1_X  (1 << 25)       		/* executable */
+#define PTE1_U  (1 << 24)       		/* user-accessible */
+#define PTE1_G  (1 << 23)       		/* global */
+#define PTE1_D  (1 << 22)       		/* dirty */
+
+/* vcache page level 2 format: same as level 1, PTE1_T  */
+#define PTE2_V  (1 << 31)       		/* entry valid */
+						/* reserved, 0 */
+#define PTE2_L  (1 << 29)       		/* accessed by local CPU */
+#define PTE2_R  (1 << 28)       		/* accessed by remote CPU */
+#define PTE2_C  (1 << 27)       		/* cachable */
+#define PTE2_W  (1 << 26)       		/* writable */
+#define PTE2_X  (1 << 25)       		/* executable */
+#define PTE2_U  (1 << 24)       		/* user-accessible */
+#define PTE2_G  (1 << 23)       		/* global */
+#define PTE2_D  (1 << 22)       		/* dirty */
+#define PTE2_os 0xff				/* OS-reserved bits */
+
+#define PTE2_SHIFT 	12
+#define PTE2_MASK 	0x0001ff000
+#define VADDR_TO_PTE2I(va) (((va) & PTE2_MASK) >> PTE2_SHIFT)
Index: /trunk/softs/tests_ccvcache_v4/common/xicu.h
===================================================================
--- /trunk/softs/tests_ccvcache_v4/common/xicu.h	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/common/xicu.h	(revision 232)
@@ -0,0 +1,96 @@
+#define XICU_BASE 0xd8200000
+#define __XICU_FUNC_SHIFT 7
+#define __XICU_IDX_SHIFT 2
+#define __XICU_RIDX(func, idx) \
+    ((((func) & 0x1f) << __XICU_FUNC_SHIFT) + \
+     (((idx) & 0x1f) << __XICU_IDX_SHIFT))
+
+/* triggers the wtiidx interrupt. R/W */
+#define XICU_WTI_REG_FUNC 0x00
+#define XICU_WTI_REG(wtiidx) __XICU_RIDX(XICU_WTI_REG_FUNC, wtiidx)
+
+/* Timer period R/W */
+#define XICU_PTI_PER_FUNC 0x01
+#define XICU_PTI_PER(ptiidx) __XICU_RIDX(XICU_PTI_PER_FUNC, ptiidx)
+
+/* timer value R/W */
+#define XICU_PTI_VAL_FUNC 0x02
+#define XICU_PTI_VAL(ptiidx) __XICU_RIDX(XICU_PTI_VAL_FUNC, ptiidx)
+
+/* Timer interrupt acknowledge. R */
+#define XICU_PTI_ACK_FUNC 0x03
+#define XICU_PTI_ACK(ptiidx) __XICU_RIDX(XICU_PTI_ACK_FUNC, ptiidx)
+
+/*
+ * remaining registers define the way interrupt sources are mutiplexed to
+ * the output lines. Indexed by output line number.
+ */
+/*
+ * Multiplex timers to output lines:
+ * XICU_MSK_PTI mask register for outidx line (bit to 1 enable interrupt)
+ * XICU_MSK_PTI_E atomically add a set of bits to XICU_MSK_PTI
+ * XICU_MSK_PTI_D atomically clear a set of bits from XICU_MSK_PTI
+ * XICU_PTI_ACT get active PTI lines for this output line
+ */
+#define XICU_MSK_PTI_FUNC 0x04 /* R/W */
+#define XICU_MSK_PTI(outidx) __XICU_RIDX(XICU_MSK_PTI_FUNC, outidx)
+
+#define XICU_MSK_PTI_E_FUNC 0x05 /* W */
+#define XICU_MSK_PTI_E(outidx) __XICU_RIDX(XICU_MSK_PTI_E_FUNC, outidx)
+
+#define XICU_MSK_PTI_D_FUNC 0x06 /* W */
+#define XICU_MSK_PTI_D(outidx) __XICU_RIDX(XICU_MSK_PTI_D_FUNC, outidx)
+
+#define XICU_PTI_ACT_FUNC 0x06 /* R */
+#define XICU_PTI_ACT(outidx) __XICU_RIDX(XICU_PTI_ACT_FUNC, outidx)
+
+/*
+ * Multiplex hardware input lines to output lines:
+ * XICU_MSK_HWI mask register for outidx line (bit to 1 enable interrupt)
+ * XICU_MSK_HWI_E atomically add a set of bits to XICU_MSK_HWI
+ * XICU_MSK_HWI_D atomically clear a set of bits from XICU_MSK_HWI
+ * XICU_HWI_ACT get active HWI lines for this output line
+ */
+#define XICU_MSK_HWI_FUNC 0x08 /* R/W */
+#define XICU_MSK_HWI(outidx) __XICU_RIDX(XICU_MSK_HWI_FUNC, outidx)
+
+#define XICU_MSK_HWI_E_FUNC 0x09 /* W */
+#define XICU_MSK_HWI_E(outidx) __XICU_RIDX(XICU_MSK_HWI_E_FUNC, outidx)
+
+#define XICU_MSK_HWI_D_FUNC 0x0a /* W */
+#define XICU_MSK_HWI_D(outidx) __XICU_RIDX(XICU_MSK_HWI_D_FUNC, outidx)
+
+#define XICU_HWI_ACT_FUNC 0x0a /* R */
+#define XICU_HWI_ACT(outidx) __XICU_RIDX(XICU_HWI_ACT_FUNC, outidx)
+
+/*
+ * Multiplex hardware input lines to output lines:
+ * XICU_MSK_WTI mask register for outidx line (bit to 1 enable interrupt)
+ * XICU_MSK_WTI_E atomically add a set of bits to XICU_MSK_WTI
+ * XICU_MSK_WTI_D atomically clear a set of bits from XICU_MSK_WTI
+ * XICU_WTI_ACT get active WTI lines for this output line
+ */
+#define XICU_MSK_WTI_FUNC 0x0c /* R/W */
+#define XICU_MSK_WTI(outidx) __XICU_RIDX(XICU_MSK_WTI_FUNC, outidx)
+
+#define XICU_MSK_WTI_E_FUNC 0x0d /* W */
+#define XICU_MSK_WTI_E(outidx) __XICU_RIDX(XICU_MSK_WTI_E_FUNC, outidx)
+
+#define XICU_MSK_WTI_D_FUNC 0x0e /* W */
+#define XICU_MSK_WTI_D(outidx) __XICU_RIDX(XICU_MSK_WTI_D_FUNC, outidx)
+
+#define XICU_WTI_ACT_FUNC 0x0e /* R */
+#define XICU_WTI_ACT(outidx) __XICU_RIDX(XICU_WTI_ACT_FUNC, outidx)
+
+/* source priority encoder for outpout lines */
+#define XICU_PRIO_FUNC 0x0f
+#define XICU_PRIO(outidx) __XICU_RIDX(XICU_PRIO_FUNC, outidx)
+
+#define XICU_PRIO_PTI 0x00000001 /* Timer interrrupt pending */
+#define XICU_PRIO_PTII(val) ((val) >> 8 & 0x1f) /* first PTI pending */
+#define XICU_PRIO_HWI 0x00000002 /* Hardware interrrupt pending */
+#define XICU_PRIO_HWII(val) ((val) >> 16 & 0x1f) /* first HWI pending */
+#define XICU_PRIO_WTI 0x00000004 /* write-triggered interrrupt pending */
+#define XICU_PRIO_WTII(val) ((val) >> 24 & 0x1f) /* first WTI pending */
+
+#define XICU_PRIO_PENDING (XICU_PRIO_PTI|XICU_PRIO_HWI|XICU_PRIO_WTI)
Index: /trunk/softs/tests_ccvcache_v4/run_tests
===================================================================
--- /trunk/softs/tests_ccvcache_v4/run_tests	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/run_tests	(revision 232)
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+PATH=${PATH}:/dsk/l1/misc/bouyer/tmp/tsarmips/obj/netbsd-5/tooldir/bin
+export PATH
+SOCLIB_TTY=TERM
+export SOCLIB_TTY
+
+for dir in test_sanity test_exceptions test_mmu_basic \
+   test_excep_ls test_excep_ls_delayslot test_excep_ls_llsc \
+   test_excep_if test_excep_if_delayslot test_excep_if_llsc \
+   test_exception_epc_modify	\
+   test_dtlb_inval test_dtlb_inval2 test_dtlb_inval3 \
+   test_itlb_inval test_itlb_inval2 \
+   test_idtlb_inval test_idtlb_inval2 test_idtlb_inval3 test_idtlb_inval4 \
+   test_dtlb_ptprinval test_itlb_ptprinval test_idtlb_ptprinval \
+   test_sync \
+   test_sc_update_cache test_pte_llsc \
+   test_interrupt \
+   test_interrupt_epc_modify \
+   test_xicu_timer \
+   test_interrupt_delayslot \
+   test_interrupt_mask \
+   test_interrupt_external_mask \
+   test_excep_cop test_excep_cop_delayslot test_excep_cop1 \
+   test_syscall test_syscall_delayslot \
+   test_breakpoint test_breakpoint_delayslot \
+   test_ri test_ri_delayslot \
+   test_ao test_ao_delayslot \
+   test_trap test_trap_delayslot \
+   test_dcache_inval_pa test_icache_inval_pa \
+   test_pte2i_ref test_pte2lw_ref test_pte2ll_ref test_pte2sw_dirty test_pte2sc_dirty \
+   test_dma_basic test_dma_unaligned \
+   ; do
+	echo -n ${dir}": "
+	(cd $dir && ./run)
+done
Index: /trunk/softs/tests_ccvcache_v4/test_ao/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ao/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ao/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_ao/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ao/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ao/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hstart
+status 0x00400002 cause 0x00000030 pc 0xBFC00034 badva 0x00000000
Index: /trunk/softs/tests_ccvcache_v4/test_ao/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ao/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ao/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000030 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_ao/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ao/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ao/test.S	(revision 232)
@@ -0,0 +1,63 @@
+/*
+ * arithmetic overflow test: check that a add can generates an exception
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	la	a0, 0x7fffffff
+	li	a1, 0x02
+	add	a0, a0, a1
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000030 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ao_delayslot/test.S	(revision 232)
@@ -0,0 +1,84 @@
+/*
+ * arithmetic overflow test: check that a overflow in a delay slot is
+ * properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	la	a0, 0x7fffffff
+	li	a1, 0x02
+	j	exit
+	add	a0, a0, a1
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_breakpoint/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_breakpoint/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_breakpoint/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_breakpoint/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_breakpoint/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_breakpoint/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000024 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_breakpoint/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_breakpoint/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_breakpoint/test.S	(revision 232)
@@ -0,0 +1,86 @@
+/*
+ * breakpoint test: check that a breakpoint generates an exception, and we can
+ * return 
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	break
+	bne a3, zero, exit
+	nop
+	/* we should not get there, a3 is not 0 */
+	EXIT(2)
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	mfc0	a0, COP0_EXPC
+	addiu	a0, a0, 4
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000024 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_breakpoint_delayslot/test.S	(revision 232)
@@ -0,0 +1,85 @@
+/*
+ * breakpoint test: check that a breakpoint in a delay slot is properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	j	exit
+	break
+	nop
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/mtty0	(revision 232)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started before DMA 0x0000BEEF
+mmu started after DMA 0x0000F00D
+mmu started after FLUSH 0x0000F00D
Index: /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/run	(revision 232)
@@ -0,0 +1,38 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started before DMA 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started after DMA 0x0000F00D$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started after FLUSH 0x0000F00D$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 3 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dcache_inval_pa/test.S	(revision 232)
@@ -0,0 +1,136 @@
+/*
+ * cache inval test: check that VC_DCACHE_INVAL_PA does the job
+ * on a cc_vcache, the cache invalidation/update should be done by hardware
+ * and VC_DCACHE_INVAL_PA should not be needed.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_a)
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, DMA_BASE
+	la	a0, testval2
+	sw	a0, DMA_SRC(a1)
+	la	a0, testval
+	sw	a0, DMA_DST(a1)
+	li	a0, 4
+	sw	a0, DMA_LEN(a1) /* start DMA */
+loop:
+	lw	a0, DMA_LEN(a1)
+	bne	a0, zero, loop;
+	nop
+
+	PRINT(mmustr_b)
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+
+	la      a0, testval
+	mtc2	a0, VC_DATA_LO
+	mtc2	zero, VC_DATA_HI
+	mtc2	zero, VC_DCACHE_INVAL_PA
+	nop
+
+	PRINT(mmustr_c)
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started before DMA \0"
+mmustr_b: .ascii "mmu started after DMA \0"
+mmustr_c: .ascii "mmu started after FLUSH \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+data_b:
+	.word MAGIC3
+testval2:
+	.word MAGIC4
+	.globl pte2_a
+
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + (DMA_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */
Index: /trunk/softs/tests_ccvcache_v4/test_dma_basic/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dma_basic/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dma_basic/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_dma_basic/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dma_basic/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dma_basic/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hbefore DMA 0x0000BEEF 0x0000F00D
+after DMA 0x0000F00D 0x0000F00D 0x0000BEEF 0x0000DEAD 0x0000DEAD
Index: /trunk/softs/tests_ccvcache_v4/test_dma_basic/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dma_basic/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dma_basic/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^after DMA 0x0000F00D 0x0000F00D 0x0000BEEF 0x0000DEAD 0x0000DEAD$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_dma_basic/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dma_basic/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dma_basic/test.S	(revision 232)
@@ -0,0 +1,135 @@
+/*
+ * basic DMA check: check that the DMA engine works and and doens't
+ * clobbers memory
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(mmustr_a)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval2
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+	la	t0, testval
+	la	t1, testval3
+	lw 	a0, 0(t0);
+	sw	a0, 0(t1)
+
+	la	a1, DMA_BASE
+	la	a0, tstsrc
+	sw	a0, DMA_SRC(a1)
+	la	a0, tstdst
+	sw	a0, DMA_DST(a1)
+	la	a0, 0x18
+	sw	a0, DMA_LEN(a1) /* start DMA */
+loop:
+	lw	a0, DMA_LEN(a1)
+	bne	a0, zero, loop;
+	nop
+	sw	a0, DMA_RESET(a1) /* reset DMA */
+
+	la	a0, testval2
+	sw	a0, DMA_SRC(a1)
+	la	a0, testval 
+	sw	a0, DMA_DST(a1)
+	la	a0, 0x4
+	sw	a0, DMA_LEN(a1) /* start DMA */
+loop2:
+	lw	a0, DMA_LEN(a1)
+	bne	a0, zero, loop2;
+	nop
+	sw	a0, DMA_RESET(a1) /* reset DMA */
+
+	PRINT(mmustr_b)
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval2
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval3
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, tstsrc
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, tstdst
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "before DMA \0"
+mmustr_b: .ascii "after DMA \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+testval:
+	.word MAGIC2
+testval2:
+	.word MAGIC4
+testval3:
+	.word MAGIC4
+tstdst:
+	.word 0
+	.org 0x1000
+	.word 0
+tstsrc:
+	.word MAGIC1
+
Index: /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^after DMA this is the test string unaligned and more than 64 chars long abcdefghijklmnopqrstuvwxyz ABCDEFGHIJKLMNOPQRSTUVWXYZ 123456789      abcdefghijklmnopqrstuvwxyz$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dma_unaligned/test.S	(revision 232)
@@ -0,0 +1,96 @@
+/*
+ * basic DMA check: check that the DMA engine works and and doens't
+ * clobbers memory
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(mmustr_a)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	t0, tstdst
+	sw 	zero, 0(t0);
+	PRINT(tstdst)
+	PUTCHAR('E')
+	PUTCHAR('\n')
+
+	la	a1, DMA_BASE
+	la	a0, tstsrc
+	sw	a0, DMA_SRC(a1)
+	la	a0, tstdst
+	sw	a0, DMA_DST(a1)
+	la	a0, 160 #strlen(tstsrc)
+	sw	a0, DMA_LEN(a1) /* start DMA */
+loop:
+	lw	a0, DMA_LEN(a1)
+	bne	a0, zero, loop;
+	nop
+
+	PRINT(mmustr_b)
+	PRINT(tstdst)
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "before DMA \0"
+mmustr_b: .ascii "after DMA \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+testval:
+	.word MAGIC2
+testval2:
+	.word MAGIC4
+testval3:
+	.word MAGIC4
+tstdst:
+	.word 0
+	.org 0x1000
+testval4:
+	.word MAGIC1
+tstsrc:
+	.ascii "this is the test string unaligned and more than 64 chars long abcdefghijklmnopqrstuvwxyz ABCDEFGHIJKLMNOPQRSTUVWXYZ 123456789      abcdefghijklmnopqrstuvwxyz\n\0"
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x0000BEEF status 0x00400002 cause 0x0000001C pc 0xBFC00080 badva 0x00200004
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+.  ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF status 0x00400002 cause 0x0000001C pc 0xBFC00080 badva 0x00200004$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval/test.S	(revision 232)
@@ -0,0 +1,117 @@
+/*
+ * dtlb inval: a write to VC_DTLB_INVAL should invalidate the corresponding
+ * dtlb entry. On a ccvcache, VC_DTLB_INVAL should not be needed, and
+ * the first access after clearing pte2_a should fail
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la 	a0, pte2_a
+	sw	zero, 0(a0) /* invalidate PTE2 entry */
+	sync
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0); /* TLB entry not invalidated yet, we can do this */
+	PRINTX
+	PUTCHAR('\n')
+	la	t0, testval + 0x00200000
+	mtc2	t0, VC_DTLB_INVAL /* invalidate VA */
+	lw 	a0, 0(t0); /* now this should fail */
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval2/test.S	(revision 232)
@@ -0,0 +1,121 @@
+/*
+ * dtlb inval: a write to a PTE2 should invalidate the corresponding
+ * dtlb entry. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la 	t0, pte2_a
+	la	a0, 0x1000 >> 12 
+	sw	a0, 4(t0) /* swap PTE2 entry */
+1:
+	ll	a0, 0(t0)
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 0(t0)
+	beqz	a0, 1b
+	nop
+
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0); /* should get MAGIC1 */
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.align 12
+	.word MAGIC2
+	.word MAGIC1
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we switch an entry in the PTP and
+ * check that the dtlb is invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "mmu started 0x0000BEEF 0xAC400000 0x0000900D status 0x00400002 cause 0x0000001C pc 0xBFC000D4 badva 0x00200004" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_inval3/test.S	(revision 232)
@@ -0,0 +1,128 @@
+/*
+ * dtlb inval: a write to a PTE2 should invalidate the corresponding
+ * dtlb entry. Check that this is true is we change only the write flag
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval + 0x00200000
+	la	a0, MAGIC3
+	sw	a0, 0(t0)
+	la 	t0, pte2_a
+1:
+	ll	a0, 0(t0)
+	la	a1, ~PTE2_W
+	and	a1, a0, a1
+	sc	a1, 0(t0)
+	beqz	a1, 1b
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0); /* should get MAGIC3 */
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval + 0x00200000
+	la	a0, MAGIC1
+	sw	a0, 0(t0)
+
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.align 12
+	.word MAGIC2
+	.word MAGIC1
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we switch an entry in the PTP and
+ * check that the dtlb is invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_W
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started ptpr_b 0x0000F00D$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started ptpr_a 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_dtlb_ptprinval/test.S	(revision 232)
@@ -0,0 +1,145 @@
+/*
+ * dtlb inval on PTPR write: check that no stale entry exists in the dtlb
+ * after MMU context swicth
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_b
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR	# PTPR <= pte1_b
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_b)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX			# print MAGIC3
+	PUTCHAR('\n')
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR	# PTPR <= pte1_a
+	nop
+	PRINT(mmustr_a)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX			# print MAGIC1
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started ptpr_a \0"
+mmustr_b: .ascii "mmu started ptpr_b \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.org data_a + 0x1000
+data_b:
+	.word MAGIC3
+	.word MAGIC4
+
+/*
+ * two PD with two different PTE2 for code: check that dtlb points to
+ * the right one by loading 2 different data at the same virtual address
+ */
+	.globl pte2_a
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+pte2_b:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x1000 >> 12 /* check real value of data_b */
+
+	.org pte2_b + 4092
+	.word 0
+
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
+	.globl pte1_b
+pte1_b:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x3000 >> 12) /* map PA 0x1000 at VA 0x00200000 via pte2_b */
+	.org pte1_b + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_b + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_b + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_b + 8188
+	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x1000002C pc 0xBFC0002C badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop/test.S	(revision 232)
@@ -0,0 +1,71 @@
+/*
+ * coproc unusable exception test: we take an exception on COP1 use
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	li	t3, MAGIC1
+	mtc1    t3,$f2
+	mfc1	a0,$f2
+	PRINTX
+	PUTCHAR('\n')
+	nop
+	nop
+	nop
+	nop
+
+1:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop1/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop1/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop1/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop1/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop1/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop1/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x1000002C pc 0xBFC00030 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop1/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop1/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop1/test.S	(revision 232)
@@ -0,0 +1,71 @@
+/*
+ * trap test: check that we get a trap on FPU access though [ls][dw]c1
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV), enable cop1 */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, div1;
+	lwc1	$f0, 0(a0)
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl div1
+div1:
+	.float	10.0
+	.globl div2
+div2:
+	.float	0.0
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x9000002C pc 0xBFC00028 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_cop_delayslot/test.S	(revision 232)
@@ -0,0 +1,65 @@
+/*
+ * coproc unusable exception test: 0x80000000 bit is set in cause register
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	j	1f
+	mtc1    t3,$f2
+	nop
+
+1:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if/mtty0	(revision 232)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started
+status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000
+0x00000004: 0x0000BEEF
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if/test.S	(revision 232)
@@ -0,0 +1,135 @@
+/*
+ * ifetch bus fault exception test: we can restart the faulting instruction
+ * We use the MMU to cause fault.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00200000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	move	a1, zero
+	la	s0, testval
+	jal	doload
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* don't clobber a0 and ra */
+	addiu   sp, sp, -8
+	sw      a0, 4(sp)
+	sw      ra, 8(sp)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0xbfc01000 at PA 0xbfc01000 */
+	la	t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8
+	la	a0, (0xbfc01000 >> PTE2_SHIFT)
+	sw	a0, 4(t0)
+	la	a0, (PTE2_V | PTE2_C | PTE2_X)
+	sw	a0, 0(t0)
+	/* la	a0, 0xbfc01000
+	mtc2	a0, VC_ITLB_INVAL */
+
+	lw      a0, 4(sp)
+	lw      ra, 8(sp)
+	addiu   sp, sp, 8
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	/*
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	lw      a1, 0(s0) /* this should trigger the exception */
+
+	/* we should not get there */
+	nop
+	nop
+	EXIT(1)
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2
+pte2:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.org pte2 + 4092
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000) - 4;
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x80000018 pc 0xBFC00FFC badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if_delayslot/test.S	(revision 232)
@@ -0,0 +1,135 @@
+/*
+ * ifetch bus fault exception test: we can restart the faulting instruction
+ * when the fault occurs in the branch delay slot.
+ * We use the MMU to cause fault.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00200000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	move	a1, zero
+	la	s0, testval
+	jal	doload
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* don't clobber a0 and ra */
+	addiu   sp, sp, -8
+	sw      a0, 4(sp)
+	sw      ra, 8(sp)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0xbfc01000 at PA 0xbfc01000 */
+	la	t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8
+	la	a0, (0xbfc01000 >> PTE2_SHIFT)
+	sw	a0, 4(t0)
+	la	a0, (PTE2_V | PTE2_C | PTE2_X)
+	sw	a0, 0(t0)
+	/* la	a0, 0xbfc01000
+	mtc2	a0, VC_ITLB_INVAL */
+
+	lw      a0, 4(sp)
+	lw      ra, 8(sp)
+	addiu   sp, sp, 8
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	/*
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	lw      a1, 0(s0) /* this should trigger the exception */
+
+	/* we should not get there */
+	nop
+	nop
+	EXIT(1)
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2
+pte2:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.org pte2 + 4092
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_if_llsc/test.S	(revision 232)
@@ -0,0 +1,136 @@
+/*
+ * ifetch bus fault exception test: we can restart the faulting instruction
+ * We use the MMU to cause fault.
+ * Match what NetBSD does for page table update: sw for ppn, ll/sc for flags
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00200000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	move	a1, zero
+	la	s0, testval
+	jal	doload
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* don't clobber a0 and ra */
+	addiu   sp, sp, -8
+	sw      a0, 4(sp)
+	sw      ra, 8(sp)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0xbfc01000 at PA 0xbfc01000 */
+	la	t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8
+	la	a0, (0xbfc01000 >> PTE2_SHIFT)
+	sw	a0, 4(t0)
+1:
+	ll	a0, 0(t0)
+	la	a0, (PTE2_V | PTE2_C | PTE2_X)
+	sc	a0, 0(t0)
+	beqz	a0, 1b
+
+	lw      a0, 4(sp)
+	lw      ra, 8(sp)
+	addiu   sp, sp, 8
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	/*
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	lw      a1, 0(s0) /* this should trigger the exception */
+	/* we should not get there */
+	nop
+	nop
+	EXIT(1)
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2
+pte2:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.org pte2 + 4092
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_excep_intr/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_intr/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_intr/Makefile	(revision 232)
@@ -0,0 +1,3 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
+CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY}
Index: /trunk/softs/tests_ccvcache_v4/test_excep_intr/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_intr/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_intr/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_excep_intr/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_intr/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_intr/mtty0	(revision 232)
@@ -0,0 +1,4 @@
+[20hstart
+status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000001
+status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001
+end 0x0000BEEF 0x00000001
Index: /trunk/softs/tests_ccvcache_v4/test_excep_intr/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_intr/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_intr/run	(revision 232)
@@ -0,0 +1,44 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^end 0x0000BEEF 0x00000001$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 3 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+echo 
+i=1180
+while true; do
+	echo -n "    DELAY=$i: "
+	make INTERRUPT_DELAY=$i --quiet || exit 1
+	${SIMUL} > run.out 2>&1 
+	if [ $? -eq 0 ]; then
+		if check_output; then
+			echo "test passsed";
+			make --quiet clean
+		else
+			echo "test FAILED"
+			exit 1
+		fi
+	else 
+		echo "test FAILED"
+		exit 1
+	fi
+	i=$((i+1))
+done
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_intr/run.out
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_intr/run.out	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_intr/run.out	(revision 232)
@@ -0,0 +1,25 @@
+
+             SystemC 2.2.0 --- Apr 14 2011 18:52:40
+        Copyright (c) 1996-2006 by all Contributors
+                    ALL RIGHTS RESERVED
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+start
+status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000001
+status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001
+end 0x0000BEEF 0x00000001
+vci_exit terminate simulation, status 0d0
+couldn't find string 2 in output - mtty not working ?
Index: /trunk/softs/tests_ccvcache_v4/test_excep_intr/subr.o.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_intr/subr.o.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_intr/subr.o.txt	(revision 232)
@@ -0,0 +1,49 @@
+
+subr.o:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+00000000 <print>:
+   0:	00804021 	move	t0,a0
+   4:	81090000 	lb	t1,0(t0)
+   8:	11200005 	beqz	t1,20 <end>
+   c:	00000000 	nop
+  10:	a3490000 	sb	t1,0(k0)
+  14:	25080001 	addiu	t0,t0,1
+  18:	08000001 	j	4 <print+0x4>
+  1c:	00000000 	nop
+
+00000020 <end>:
+  20:	03e00008 	jr	ra
+  24:	00000000 	nop
+
+00000028 <printx>:
+  28:	00804021 	move	t0,a0
+  2c:	24090030 	li	t1,48
+  30:	a3490000 	sb	t1,0(k0)
+  34:	24090078 	li	t1,120
+  38:	a3490000 	sb	t1,0(k0)
+  3c:	24090008 	li	t1,8
+  40:	3c0af000 	lui	t2,0xf000
+  44:	010a5024 	and	t2,t0,t2
+  48:	000a5702 	srl	t2,t2,0x1c
+  4c:	294b000a 	slti	t3,t2,10
+  50:	11600004 	beqz	t3,64 <printx+0x3c>
+  54:	00000000 	nop
+  58:	214a0030 	addi	t2,t2,48
+  5c:	0800001a 	j	68 <printx+0x40>
+  60:	00000000 	nop
+  64:	214a0037 	addi	t2,t2,55
+  68:	a34a0000 	sb	t2,0(k0)
+  6c:	2129ffff 	addi	t1,t1,-1
+  70:	1d20fff3 	bgtz	t1,40 <printx+0x18>
+  74:	00084100 	sll	t0,t0,0x4
+  78:	03e00008 	jr	ra
+  7c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	84000f10 	lh	zero,3856(zero)
+	...
Index: /trunk/softs/tests_ccvcache_v4/test_excep_intr/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_intr/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_intr/test.S	(revision 232)
@@ -0,0 +1,201 @@
+/*
+ * Check interrupt while in trap handler.
+ * Cache is enabled so we have one instruction/cycle
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+#include <xicu.h>
+
+#define DOLOAD_ADDR 0x80000000
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00200000 - 16
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 */
+	li	a0, INTERRUPT_DELAY
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	nop
+	move	a1, zero
+	la	s0, DOLOAD_ADDR
+	jalr	s0
+	nop
+	j	end
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+end:
+	PRINT(endstr)
+	move	a0, a1
+	PRINTX
+	PUTCHAR(' ')
+	la	a0, myvar
+	lw	a0, 0(a0)
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+        /* don't clobber a0 and ra */
+	addiu   sp, sp, -8
+	sw      a0, 4(sp)
+	sw      ra, 8(sp)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	move	s0, a0
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+	PUTCHAR('\n')
+	/* map VA DOLOAD_ADDR at PA 0xbfc01000 */
+	la	t0, pte22 + VADDR_TO_PTE2I(DOLOAD_ADDR) * 8
+	la	a0, (0xbfc01000 >> PTE2_SHIFT)
+	sw	a0, 4(t0)
+	la	a0, (PTE2_V | PTE2_C | PTE2_X)
+	sw	a0, 0(t0)
+	mtc2	zero, VC_DCACHE_FLUSH /* flush the whole data cache */
+
+	andi	a0, s0, 0xff00
+	beq	a0, zero, notintr
+	nop
+
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+notintr:
+	la	a1, myvar
+	la	a0, 0(a1)
+	beq	a0, zero, noex
+	nop
+	EXIT(2)
+noex:
+	li	a0, 1
+	sw	a0, 0(a1)
+	lw	a0, 4(sp)
+	lw	ra, 8(sp)
+	addiu	sp, sp, 8
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	/*
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	la	s0, testval
+	jr	ra
+	lw	a1, 0(s0) /* this should trigger the exception */
+	/* we should not get there */
+	EXIT(1)
+	nop
+	.data
+myvar:	.word 0
+testval:
+	.word MAGIC2
+	.globl pte2
+pte2:
+        .align 12
+        .word PTE2_V | PTE2_C | PTE2_X
+        .word BOOT_ADDRESS >> 12
+        .org pte2 + 4092
+	.globl pte22
+pte22:
+        .align 12
+        .word 0
+        .word 0
+        .org pte22 + 4092
+        .globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (DOLOAD_ADDR >> 21) * 4
+        .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map VA DOLOAD_ADDR with 4k page: check real address of PTE22 !!! */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+        .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (XICU_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_intr/test.elf.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_intr/test.elf.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_intr/test.elf.txt	(revision 232)
@@ -0,0 +1,273 @@
+
+test.elf:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+bfc00000 <_start>:
+bfc00000:	3c1ad020 	lui	k0,0xd020
+bfc00004:	3c1be000 	lui	k1,0xe000
+bfc00008:	3c1d001f 	lui	sp,0x1f
+bfc0000c:	37bdfff0 	ori	sp,sp,0xfff0
+bfc00010:	40806800 	mtc0	zero,c0_cause
+bfc00014:	3c040000 	lui	a0,0x0
+bfc00018:	24844000 	addiu	a0,a0,16384
+bfc0001c:	00042342 	srl	a0,a0,0xd
+bfc00020:	48840000 	mtc2	a0,$0
+	...
+bfc0002c:	2404000f 	li	a0,15
+bfc00030:	48840800 	mtc2	a0,$1
+bfc00034:	3c04bfc0 	lui	a0,0xbfc0
+bfc00038:	2484024c 	addiu	a0,a0,588
+bfc0003c:	0ff000e4 	jal	bfc00390 <print>
+bfc00040:	00000000 	nop
+bfc00044:	3c08d820 	lui	t0,0xd820
+bfc00048:	8d040180 	lw	a0,384(t0)
+bfc0004c:	24040001 	li	a0,1
+bfc00050:	ad040280 	sw	a0,640(t0)
+bfc00054:	3410beef 	li	s0,0xbeef
+bfc00058:	2404049c 	li	a0,1180
+bfc0005c:	ad040080 	sw	a0,128(t0)
+bfc00060:	8d040180 	lw	a0,384(t0)
+bfc00064:	3c040040 	lui	a0,0x40
+bfc00068:	24840401 	addiu	a0,a0,1025
+bfc0006c:	40846000 	mtc0	a0,c0_status
+	...
+bfc00088:	00002821 	move	a1,zero
+bfc0008c:	3c108000 	lui	s0,0x8000
+bfc00090:	0200f809 	jalr	s0
+bfc00094:	00000000 	nop
+bfc00098:	0bf0002c 	j	bfc000b0 <end>
+bfc0009c:	00000000 	nop
+bfc000a0:	24040001 	li	a0,1
+bfc000a4:	af640000 	sw	a0,0(k1)
+bfc000a8:	0bf0002a 	j	bfc000a8 <_start+0xa8>
+bfc000ac:	00000000 	nop
+
+bfc000b0 <end>:
+bfc000b0:	3c04bfc0 	lui	a0,0xbfc0
+bfc000b4:	24840253 	addiu	a0,a0,595
+bfc000b8:	0ff000e4 	jal	bfc00390 <print>
+bfc000bc:	00000000 	nop
+bfc000c0:	00a02021 	move	a0,a1
+bfc000c4:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000c8:	00000000 	nop
+bfc000cc:	24040020 	li	a0,32
+bfc000d0:	a3440000 	sb	a0,0(k0)
+bfc000d4:	3c040000 	lui	a0,0x0
+bfc000d8:	24840000 	addiu	a0,a0,0
+bfc000dc:	8c840000 	lw	a0,0(a0)
+bfc000e0:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000e4:	00000000 	nop
+bfc000e8:	2404000a 	li	a0,10
+bfc000ec:	a3440000 	sb	a0,0(k0)
+bfc000f0:	24040000 	li	a0,0
+bfc000f4:	af640000 	sw	a0,0(k1)
+bfc000f8:	0bf0003e 	j	bfc000f8 <end+0x48>
+bfc000fc:	00000000 	nop
+
+bfc00100 <excep>:
+bfc00100:	27bdfff8 	addiu	sp,sp,-8
+bfc00104:	afa40004 	sw	a0,4(sp)
+bfc00108:	afbf0008 	sw	ra,8(sp)
+bfc0010c:	3c04bfc0 	lui	a0,0xbfc0
+bfc00110:	24840228 	addiu	a0,a0,552
+bfc00114:	0ff000e4 	jal	bfc00390 <print>
+bfc00118:	00000000 	nop
+bfc0011c:	40046000 	mfc0	a0,c0_status
+bfc00120:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00124:	00000000 	nop
+bfc00128:	3c04bfc0 	lui	a0,0xbfc0
+bfc0012c:	24840230 	addiu	a0,a0,560
+bfc00130:	0ff000e4 	jal	bfc00390 <print>
+bfc00134:	00000000 	nop
+bfc00138:	40046800 	mfc0	a0,c0_cause
+bfc0013c:	00808021 	move	s0,a0
+bfc00140:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00144:	00000000 	nop
+bfc00148:	3c04bfc0 	lui	a0,0xbfc0
+bfc0014c:	24840238 	addiu	a0,a0,568
+bfc00150:	0ff000e4 	jal	bfc00390 <print>
+bfc00154:	00000000 	nop
+bfc00158:	40047000 	mfc0	a0,c0_epc
+bfc0015c:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00160:	00000000 	nop
+bfc00164:	3c04bfc0 	lui	a0,0xbfc0
+bfc00168:	2484023d 	addiu	a0,a0,573
+bfc0016c:	0ff000e4 	jal	bfc00390 <print>
+bfc00170:	00000000 	nop
+bfc00174:	40044000 	mfc0	a0,c0_badvaddr
+bfc00178:	0ff000ee 	jal	bfc003b8 <printx>
+bfc0017c:	00000000 	nop
+bfc00180:	3c04bfc0 	lui	a0,0xbfc0
+bfc00184:	24840245 	addiu	a0,a0,581
+bfc00188:	0ff000e4 	jal	bfc00390 <print>
+bfc0018c:	00000000 	nop
+bfc00190:	3c08d820 	lui	t0,0xd820
+bfc00194:	8d040780 	lw	a0,1920(t0)
+bfc00198:	0ff000ee 	jal	bfc003b8 <printx>
+bfc0019c:	00000000 	nop
+bfc001a0:	2404000a 	li	a0,10
+bfc001a4:	a3440000 	sb	a0,0(k0)
+bfc001a8:	3c080000 	lui	t0,0x0
+bfc001ac:	25082000 	addiu	t0,t0,8192
+bfc001b0:	3c04000b 	lui	a0,0xb
+bfc001b4:	3484fc01 	ori	a0,a0,0xfc01
+bfc001b8:	ad040004 	sw	a0,4(t0)
+bfc001bc:	3c048a00 	lui	a0,0x8a00
+bfc001c0:	ad040000 	sw	a0,0(t0)
+bfc001c4:	48801800 	mtc2	zero,$3
+bfc001c8:	3204ff00 	andi	a0,s0,0xff00
+bfc001cc:	10800003 	beqz	a0,bfc001dc <notintr>
+bfc001d0:	00000000 	nop
+bfc001d4:	3c08d820 	lui	t0,0xd820
+bfc001d8:	ad000080 	sw	zero,128(t0)
+
+bfc001dc <notintr>:
+bfc001dc:	3c050000 	lui	a1,0x0
+bfc001e0:	24a50000 	addiu	a1,a1,0
+bfc001e4:	24a40000 	addiu	a0,a1,0
+bfc001e8:	10800005 	beqz	a0,bfc00200 <noex>
+bfc001ec:	00000000 	nop
+bfc001f0:	24040002 	li	a0,2
+bfc001f4:	af640000 	sw	a0,0(k1)
+bfc001f8:	0bf0007e 	j	bfc001f8 <notintr+0x1c>
+bfc001fc:	00000000 	nop
+
+bfc00200 <noex>:
+bfc00200:	24040001 	li	a0,1
+bfc00204:	aca40000 	sw	a0,0(a1)
+bfc00208:	8fa40004 	lw	a0,4(sp)
+bfc0020c:	8fbf0008 	lw	ra,8(sp)
+bfc00210:	27bd0008 	addiu	sp,sp,8
+bfc00214:	42000018 	eret
+bfc00218:	24040001 	li	a0,1
+bfc0021c:	af640000 	sw	a0,0(k1)
+bfc00220:	0bf00088 	j	bfc00220 <noex+0x20>
+bfc00224:	00000000 	nop
+
+bfc00228 <statusstr>:
+bfc00228:	74617473 	jalx	b185d1cc <_stack+0xb145d1dc>
+bfc0022c:	00207375 	0x207375
+
+bfc00230 <causestr>:
+bfc00230:	75616320 	jalx	b5858c80 <_stack+0xb5458c90>
+bfc00234:	00206573 	tltu	at,zero,0x195
+
+bfc00238 <pcstr>:
+bfc00238:	20637020 	addi	v1,v1,28704
+	...
+
+bfc0023d <badvastr>:
+bfc0023d:	6220      	sw	ra,128(sp)
+bfc0023f:	6461      	restore	8,ra,s0
+bfc00241:	6176      	btnez	bfc0032f <endstr+0xdc>
+bfc00243:	0020      	addiu	s0,sp,128
+
+bfc00245 <xicustr>:
+bfc00245:	7820      	sd	s1,0(s0)
+bfc00247:	6369      	addiu	sp,840
+bfc00249:	2075      	beqz	s0,bfc00335 <endstr+0xe2>
+	...
+
+bfc0024c <startstr>:
+bfc0024c:	72617473 	0x72617473
+bfc00250:	65000a74 	0x65000a74
+
+bfc00253 <endstr>:
+bfc00253:	6e65      	li	a2,101
+bfc00255:	2064      	beqz	s0,bfc0031f <endstr+0xcc>
+	...
+
+bfc00380 <evect>:
+bfc00380:	0bf00040 	j	bfc00100 <excep>
+bfc00384:	00000000 	nop
+	...
+
+bfc00390 <print>:
+bfc00390:	00804021 	move	t0,a0
+bfc00394:	81090000 	lb	t1,0(t0)
+bfc00398:	11200005 	beqz	t1,bfc003b0 <end>
+bfc0039c:	00000000 	nop
+bfc003a0:	a3490000 	sb	t1,0(k0)
+bfc003a4:	25080001 	addiu	t0,t0,1
+bfc003a8:	0bf000e5 	j	bfc00394 <print+0x4>
+bfc003ac:	00000000 	nop
+
+bfc003b0 <end>:
+bfc003b0:	03e00008 	jr	ra
+bfc003b4:	00000000 	nop
+
+bfc003b8 <printx>:
+bfc003b8:	00804021 	move	t0,a0
+bfc003bc:	24090030 	li	t1,48
+bfc003c0:	a3490000 	sb	t1,0(k0)
+bfc003c4:	24090078 	li	t1,120
+bfc003c8:	a3490000 	sb	t1,0(k0)
+bfc003cc:	24090008 	li	t1,8
+bfc003d0:	3c0af000 	lui	t2,0xf000
+bfc003d4:	010a5024 	and	t2,t0,t2
+bfc003d8:	000a5702 	srl	t2,t2,0x1c
+bfc003dc:	294b000a 	slti	t3,t2,10
+bfc003e0:	11600004 	beqz	t3,bfc003f4 <printx+0x3c>
+bfc003e4:	00000000 	nop
+bfc003e8:	214a0030 	addi	t2,t2,48
+bfc003ec:	0bf000fe 	j	bfc003f8 <printx+0x40>
+bfc003f0:	00000000 	nop
+bfc003f4:	214a0037 	addi	t2,t2,55
+bfc003f8:	a34a0000 	sb	t2,0(k0)
+bfc003fc:	2129ffff 	addi	t1,t1,-1
+bfc00400:	1d20fff3 	bgtz	t1,bfc003d0 <printx+0x18>
+bfc00404:	00084100 	sll	t0,t0,0x4
+bfc00408:	03e00008 	jr	ra
+bfc0040c:	00000000 	nop
+	...
+
+bfc01000 <doload>:
+bfc01000:	3c100000 	lui	s0,0x0
+bfc01004:	26100004 	addiu	s0,s0,4
+bfc01008:	03e00008 	jr	ra
+bfc0100c:	8e050000 	lw	a1,0(s0)
+bfc01010:	24040001 	li	a0,1
+bfc01014:	af640000 	sw	a0,0(k1)
+bfc01018:	0bf00406 	j	bfc01018 <doload+0x18>
+bfc0101c:	00000000 	nop
+bfc01020:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+bfc01024 <.reginfo>:
+bfc01024:	bc010130 	cache	0x1,304(zero)
+	...
+bfc01038:	00008000 	sll	s0,zero,0x0
+
+Disassembly of section .data:
+
+00000000 <myvar>:
+       0:	00000000 	nop
+
+00000004 <testval>:
+       4:	0000beef 	0xbeef
+	...
+
+00001000 <pte2>:
+    1000:	8a000000 	lwl	zero,0(s0)
+    1004:	000bfc00 	sll	ra,t3,0x10
+	...
+
+00002000 <pte22>:
+	...
+
+00004000 <pte1>:
+    4000:	8c000000 	lw	zero,0(zero)
+	...
+    5000:	c0000002 	ll	zero,2(zero)
+	...
+    57f8:	c0000001 	ll	zero,1(zero)
+	...
+    5a04:	84000681 	lh	zero,1665(zero)
+	...
+    5b04:	840006c1 	lh	zero,1729(zero)
+	...
+    5c00:	84000700 	lh	zero,1792(zero)
+	...
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls/mtty0	(revision 232)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started
+status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004
+0x00000004: 0x0000BEEF
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls/test.S	(revision 232)
@@ -0,0 +1,103 @@
+/*
+ * load/store bus fault exception test: we can restart the faulting instruction
+ * We use the MMU to cause fault
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/* 0x00000000 not mapped yet: we fault, load the MMU and retry */
+	move	a1, zero
+	la	s0, testval
+	lw	a1, 0(s0) /* this should trigger the exception */
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0 at PA 0: just copy entry for 0x00200000 */
+	la	t0, pte1 + 0x00200000
+	lw	a0, 4(t0)
+	sw	a0, 0(t0)
+	/* mtc2	zero, VC_DTLB_INVAL */
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte1
+pte1:
+	.align 13
+	.word 0x0                            /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x8000001C pc 0xBFC000AC badva 0x00000004$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls_delayslot/test.S	(revision 232)
@@ -0,0 +1,123 @@
+/*
+ * load/store bus fault exception test: we can restart the jump when the
+ * instruction in the delay slot takes a fault.
+ * We use the MMU to cause fault
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/* 0x00000000 not mapped yet: we fault, load the MMU and retry */
+	move	a1, zero
+	la	s0, testval
+	jal	doload
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl doload
+doload:
+	nop
+	nop
+	jr 	ra
+	lw	a1, 0(s0) /* this should trigger the exception */
+
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* don't clobber a0 and ra */
+	addiu	sp, sp, -8
+	sw	a0, 4(sp)
+	sw	ra, 8(sp)
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0 at PA 0: just copy entry for 0x00200000 */
+	la	t0, pte1 + 0x00200000
+	lw	a0, 4(t0)
+	sw	a0, 0(t0)
+	/* mtc2	zero, VC_DTLB_INVAL */
+	lw	a0, 4(sp)
+	lw	ra, 8(sp)
+	addiu	sp, sp, 8
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte1
+pte1:
+	.align 13
+	.word 0x0                            /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_excep_ls_llsc/test.S	(revision 232)
@@ -0,0 +1,107 @@
+/*
+ * load/store bus fault exception test: we can restart the faulting instruction
+ * We use the MMU to cause fault
+ * Match what NetBSD does for page table update: sw for ppn, ll/sc for flags
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/* 0x00000000 not mapped yet: we fault, load the MMU and retry */
+	move	a1, zero
+	la	s0, testval
+	lw	a1, 0(s0) /* this should trigger the exception */
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0 at PA 0: just copy entry for 0x00200000 */
+	la	t0, pte1 + 0x00200000
+1:
+	ll	a0, 0(t0)
+	lw	a0, 4(t0)
+	sc	a0, 0(t0)
+	beqz	a0, 1b
+	/* mtc2	zero, VC_DTLB_INVAL */
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte1
+pte1:
+	.align 13
+	.word 0x0                            /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^eret$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_exception_epc_modify/test.S	(revision 232)
@@ -0,0 +1,71 @@
+/*
+ * Check that on return from exception the modified EPC is handled.
+ * We use a load to an unaligned address to trigger the exception.
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	li	a0, 1
+	lw	a0, 0(a0) /* fault */
+
+	/* we shouldn't get there */
+	EXIT(1)
+
+	.globl exret
+
+exret:
+	PRINT(eretstr)
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	la	a0, exret
+	mtc0	a0, COP0_EXPC
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_exceptions/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_exceptions/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_exceptions/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_exceptions/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_exceptions/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_exceptions/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400006 cause 0x00000010 pc 0xBFC0001C badva 0x00000001$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_exceptions/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_exceptions/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_exceptions/test.S	(revision 232)
@@ -0,0 +1,60 @@
+/*
+ * Check that the exeption vector is called on exception.
+ * We use a load to an unaligned address to trigger the exception.
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	li	a0, 1
+	lw	a0, 0(a0) /* fault */
+
+	/* we shouldn't get there */
+        EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	li	a0, '\n'
+	sb	a0, 0(k0)
+
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hstart
+0x00000000 0x00000000
Index: /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/run.out
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/run.out	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/run.out	(revision 232)
@@ -0,0 +1,23 @@
+
+             SystemC 2.2.0 --- Apr 14 2011 18:52:40
+        Copyright (c) 1996-2006 by all Contributors
+                    ALL RIGHTS RESERVED
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+start
+0x00000000 0x00000000
+vci_exit terminate simulation, status 0d0
+couldn't find string 1 in output - mtty not working ?
Index: /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/subr.o.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/subr.o.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/subr.o.txt	(revision 232)
@@ -0,0 +1,49 @@
+
+subr.o:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+00000000 <print>:
+   0:	00804021 	move	t0,a0
+   4:	81090000 	lb	t1,0(t0)
+   8:	11200005 	beqz	t1,20 <end>
+   c:	00000000 	nop
+  10:	a3490000 	sb	t1,0(k0)
+  14:	25080001 	addiu	t0,t0,1
+  18:	08000001 	j	4 <print+0x4>
+  1c:	00000000 	nop
+
+00000020 <end>:
+  20:	03e00008 	jr	ra
+  24:	00000000 	nop
+
+00000028 <printx>:
+  28:	00804021 	move	t0,a0
+  2c:	24090030 	li	t1,48
+  30:	a3490000 	sb	t1,0(k0)
+  34:	24090078 	li	t1,120
+  38:	a3490000 	sb	t1,0(k0)
+  3c:	24090008 	li	t1,8
+  40:	3c0af000 	lui	t2,0xf000
+  44:	010a5024 	and	t2,t0,t2
+  48:	000a5702 	srl	t2,t2,0x1c
+  4c:	294b000a 	slti	t3,t2,10
+  50:	11600004 	beqz	t3,64 <printx+0x3c>
+  54:	00000000 	nop
+  58:	214a0030 	addi	t2,t2,48
+  5c:	0800001a 	j	68 <printx+0x40>
+  60:	00000000 	nop
+  64:	214a0037 	addi	t2,t2,55
+  68:	a34a0000 	sb	t2,0(k0)
+  6c:	2129ffff 	addi	t1,t1,-1
+  70:	1d20fff3 	bgtz	t1,40 <printx+0x18>
+  74:	00084100 	sll	t0,t0,0x4
+  78:	03e00008 	jr	ra
+  7c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	84000f10 	lh	zero,3856(zero)
+	...
Index: /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/temp
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/temp	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/temp	(revision 232)
@@ -0,0 +1,8775 @@
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+****************** cycle 1 ************************************************
+PROC proc
+  <InsReq  invalid mode MODE_HYPER @ 0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 2 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 3 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 4 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 5 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 6 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 7 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 8 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 9 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 10 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 11 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 12 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 13 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1be000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 14 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 15 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 16 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x037bdfff0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 17 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 18 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840155 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 19 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 20 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 21 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c042040 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 22 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040846000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 23 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 24 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 25 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4820000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 26 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 27 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 28 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4800000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 29 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 30 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 31 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp    valid no error ins 0x3c1ad020>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 32 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00004>
+  <InsRsp    valid no error ins 0x3c1be000>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 33 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00008>
+  <InsRsp    valid no error ins 0x3c1d003f>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 34 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0000c>
+  <InsRsp    valid no error ins 0x37bdfff0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 35 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00010>
+  <InsRsp    valid no error ins 0x3c04bfc0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 36 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00014>
+  <InsRsp    valid no error ins 0x24840155>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 37 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00018>
+  <InsRsp    valid no error ins 0xff000e4>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 38 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0001c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 39 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 40 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00380  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 41 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 42 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 43 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 44 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 45 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 46 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 47 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 48 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 49 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 50 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 51 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 52 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 53 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 54 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x081090000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 55 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011200005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 56 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 57 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 58 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x025080001 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 59 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000e5 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 60 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 61 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 62 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 63 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 64 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 65 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 66 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 67 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 68 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 69 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 70 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0x5 / valid = 0 / line = 0x000000005
+****************** cycle 71 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00140  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 72 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 73 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 74 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 75 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 76 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 77 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 78 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+****************** cycle 79 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+****************** cycle 80 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000206573 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+****************** cycle 81 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x75616320 / way = 0 / set = 0x5 / word = 0
+****************** cycle 82 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x206573 / way = 0 / set = 0x5 / word = 0x1
+****************** cycle 83 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061622000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x20637020 / way = 0 / set = 0x5 / word = 0x2
+****************** cycle 84 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020617664 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x61622000 / way = 0 / set = 0x5 / word = 0x3
+****************** cycle 85 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061747300 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x20617664 / way = 0 / set = 0x5 / word = 0x4
+****************** cycle 86 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a7472 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x61747300 / way = 0 / set = 0x5 / word = 0x5
+****************** cycle 87 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x06d727375 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0xa7472 / way = 0 / set = 0x5 / word = 0x6
+****************** cycle 88 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00a65646f | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x6d727375 / way = 0 / set = 0x5 / word = 0x7
+****************** cycle 89 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0xa65646f / way = 0 / set = 0x5 / word = 0x8
+****************** cycle 90 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0x9
+****************** cycle 91 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xa
+****************** cycle 92 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xb
+****************** cycle 93 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xc
+****************** cycle 94 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xd
+****************** cycle 95 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xe
+****************** cycle 96 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xf
+****************** cycle 97 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 98 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 99 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 100 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 101 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 102 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 103 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 104 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000073  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 105 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 106 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 107 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 108 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 109 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 110 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 111 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 112 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 113 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 114 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 115 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 116 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 117 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 118 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 119 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 120 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 121 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 122 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 123 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 124 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 125 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 126 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000061  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 127 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 128 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 129 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 130 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 131 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 132 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 133 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 134 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 135 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 136 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 137 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000072  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 138 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 139 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 140 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 141 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 142 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 143 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 144 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 145 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 146 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 147 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 148 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 149 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 150 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 151 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 152 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 153 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 154 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 155 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 156 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 157 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 158 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 159 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 160 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 161 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 162 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b0>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 163 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 164 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00020>
+  <InsRsp    valid no error ins 0x3c042040>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 165 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00024>
+  <InsRsp    valid no error ins 0x40846000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 166 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00028>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 167 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0002c>
+  <InsRsp    valid no error ins 0x24840008>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 168 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00030>
+  <InsRsp    valid no error ins 0xc4820000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 169 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 170 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0 / valid = 0 / line = 0x000000000
+****************** cycle 171 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 172 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 173 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 174 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0
+  <MEMC.TGT_CMD_IDLE> Receive command from srcid 0x0000 / for address 0x000000000
+****************** cycle 175 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_READ | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+  <MEMC.TGT_CMD_READ> Push into read_fifo: address = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040
+****************** cycle 176 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_IDLE> Read request: srcid = 0 / address = 0 / nwords = 16
+****************** cycle 177 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_DIR_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_DIR_LOCK> Accessing directory:  address = 0 / hit = 0 / count = 0 / is_cnt = 0
+****************** cycle 178 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_LOCK> Check TRT: hit_read = 0 / hit_write = 0 / full = 0
+****************** cycle 179 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_SET | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_SET> Write in Transaction Table:  address = 0 / srcid = 0
+****************** cycle 180 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_REQ | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_REQ> Request GET transaction for address 0
+****************** cycle 181 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 182 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram
+****************** cycle 183 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_IDLE> Response from XRAM to a get transaction
+****************** cycle 184 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+****************** cycle 185 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 0 / data = 0xdead
+****************** cycle 186 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 1 / data = 0xbeef
+****************** cycle 187 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 2 / data = 0x41200000
+****************** cycle 188 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 3 / data = 0
+****************** cycle 189 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 4 / data = 0
+****************** cycle 190 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 5 / data = 0
+****************** cycle 191 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 6 / data = 0
+****************** cycle 192 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 7 / data = 0
+****************** cycle 193 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 8 / data = 0
+****************** cycle 194 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 9 / data = 0
+****************** cycle 195 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 10 / data = 0
+****************** cycle 196 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 11 / data = 0
+****************** cycle 197 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 12 / data = 0
+****************** cycle 198 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 13 / data = 0
+****************** cycle 199 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 14 / data = 0
+****************** cycle 200 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 15 / data = 0
+****************** cycle 201 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.XRAM_RSP_IDLE> Available cache line in TRT: index = 0
+****************** cycle 202 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
+****************** cycle 203 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
+  <MEMC.XRAM_RSP_DIR_LOCK> Get access to directory
+****************** cycle 204 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
+****************** cycle 205 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
+  <MEMC.XRAM_RSP_TRT_COPY> Select a slot:  way = 0 / set = 0 / inval_required = 0
+****************** cycle 206 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
+****************** cycle 207 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
+  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT
+****************** cycle 208 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT
+  <MEMC.XRAM_RSP_DIR_UPDT> Directory update:  way = 0 / set = 0 / count = 1 / is_cnt = 0
+****************** cycle 209 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP
+  <MEMC.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0 / nwords = 16
+****************** cycle 210 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 211 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xdead / cpt = 0
+****************** cycle 212 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xbeef / cpt = 0x1
+****************** cycle 213 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0x41200000 / cpt = 0x2
+****************** cycle 214 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x3
+****************** cycle 215 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x4
+****************** cycle 216 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x5
+****************** cycle 217 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xdead / way = 0 / set = 0 / word = 0
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x6
+****************** cycle 218 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xbeef / way = 0 / set = 0 / word = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x7
+****************** cycle 219 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0x41200000 / way = 0 / set = 0 / word = 0x2
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x8
+****************** cycle 220 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x3
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x9
+****************** cycle 221 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x4
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xa
+****************** cycle 222 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x5
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xb
+****************** cycle 223 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x6
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xc
+****************** cycle 224 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x7
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xd
+****************** cycle 225 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x8
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xe
+****************** cycle 226 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x9
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xf
+****************** cycle 227 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xa
+****************** cycle 228 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xb
+****************** cycle 229 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xc
+****************** cycle 230 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xd
+****************** cycle 231 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xe
+****************** cycle 232 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xf
+****************** cycle 233 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 234 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0x41200000>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 235 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00038>
+  <InsRsp    valid no error ins 0x2484000c>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 236 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0xc4800000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 237 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 238 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00040  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 239 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 240 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 241 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 242 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 243 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 244 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 245 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00016 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 246 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00016 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 247 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046020003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 248 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 249 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 250 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 251 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00014 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 252 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 253 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000402021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 254 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 255 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 256 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 257 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 258 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000602021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 259 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 260 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 261 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02404000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 262 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 263 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 264 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 265 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp    valid no error ins 0xbf00016>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 266 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00044>
+  <InsRsp    valid no error ins 0x46020003>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 267 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00058>
+  <InsRsp    valid no error ins 0x402021>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 268 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0005c>
+  <InsRsp    valid no error ins 0xff000ee>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 269 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00060>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 270 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b8>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 271 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003bc>
+  <InsRsp    valid no error ins 0x24090030>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 272 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 273 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc003c0  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 274 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 275 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 276 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 277 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 278 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 279 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 280 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 281 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 282 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090078 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 283 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 284 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 285 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 286 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c0af000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 287 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0010a5024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 288 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a5702 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 289 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0294b000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 290 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011600004 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 291 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 292 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 293 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000fe | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 294 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 295 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0037 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 296 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a34a0000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 297 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02129ffff | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 298 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 299 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 300 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 301 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c4>
+  <InsRsp    valid no error ins 0x24090078>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 302 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c8>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 303 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 304 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 305 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 306 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 307 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 308 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 309 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 310 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 311 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 312 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 313 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 314 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000078  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 315 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 316 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00400  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 317 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 318 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 319 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 320 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 321 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 322 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 323 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 324 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 325 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 326 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000084100 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 327 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 328 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 329 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 330 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0bc00009c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 331 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 332 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 333 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 334 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 335 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 336 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 337 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 338 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 339 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 340 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 341 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 342 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 343 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 344 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 345 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 346 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 347 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 348 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 349 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 350 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 351 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 352 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 353 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 354 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 355 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 356 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 357 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 358 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 359 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 360 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 361 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 362 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 363 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 364 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 365 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 366 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 367 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 368 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 369 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 370 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 371 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 372 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 373 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 374 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 375 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 376 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 377 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 378 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 379 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 380 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 381 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 382 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 383 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 384 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 385 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 386 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 387 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 388 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 389 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 390 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 391 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 392 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 393 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 394 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 395 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 396 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 397 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 398 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 399 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 400 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 401 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 402 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 403 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 404 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 405 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 406 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 407 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 408 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 409 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 410 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 411 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 412 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 413 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 414 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 415 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 416 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 417 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 418 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 419 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 420 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 421 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 422 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 423 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 424 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 425 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 426 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 427 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 428 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 429 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 430 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 431 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 432 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 433 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 434 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 435 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 436 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 437 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00408>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 438 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0040c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 439 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00064>
+  <InsRsp    valid no error ins 0x24040020>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 440 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xa3440000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 441 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0x602021>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 442 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00070>
+  <InsRsp    valid no error ins 0xff000ee>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 443 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00074>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 444 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b8>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 445 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003bc>
+  <InsRsp    valid no error ins 0x24090030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 446 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 447 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c4>
+  <InsRsp    valid no error ins 0x24090078>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000020  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 448 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c8>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 449 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 450 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 451 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 452 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 453 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 454 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 455 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 456 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 457 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 458 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 459 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 460 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 461 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 462 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 463 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 464 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 465 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 466 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 467 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 468 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 469 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000078  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 470 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 471 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 472 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 473 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 474 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 475 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 476 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 477 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 478 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 479 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 480 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 481 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 482 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 483 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 484 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 485 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 486 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 487 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 488 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 489 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 490 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 491 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 492 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 493 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 494 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 495 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 496 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 497 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 498 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 499 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 500 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 501 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 502 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 503 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 504 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 505 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 506 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 507 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 508 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 509 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 510 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 511 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 512 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 513 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 514 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 515 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 516 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 517 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 518 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 519 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 520 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 521 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 522 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 523 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 524 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 525 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 526 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 527 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 528 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 529 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 530 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 531 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 532 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 533 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 534 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 535 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 536 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 537 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 538 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 539 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 540 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 541 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 542 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 543 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 544 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 545 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 546 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 547 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 548 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 549 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 550 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 551 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 552 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 553 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 554 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 555 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 556 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 557 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 558 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 559 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 560 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 561 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 562 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00408>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 563 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0040c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 564 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00078>
+  <InsRsp    valid no error ins 0x2404000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 565 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0007c>
+  <InsRsp    valid no error ins 0xa3440000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 566 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 567 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00080  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 568 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 569 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 570 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 571 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 572 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 573 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 574 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 575 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 576 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 577 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00022 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 578 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00022 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 579 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 580 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 581 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840138 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 582 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 583 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 584 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040046000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 585 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 586 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 587 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 588 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840140 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 589 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 590 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 591 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040046800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 592 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 593 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 594 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp    valid no error ins 0x24040000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 595 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00084>
+  <InsRsp    valid no error ins 0xaf640000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 596 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
+  <InsRsp    valid no error ins 0xbf00022>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 597 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 598 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
+  <InsRsp    valid no error ins 0xbf00022>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0e0000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 599 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 600 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
+  <InsRsp    valid no error ins 0xbf00022>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 601 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+vci_exit terminate simulation, status 0x000000000
Index: /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/test.S	(revision 232)
@@ -0,0 +1,92 @@
+/*
+ * trap test: check that a trap in a delay slot is
+ * properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV), enable cop1 */
+	lui	a0, 0x2040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, div1
+	lwc1	$f2, 0(a0)
+	la	a0, div2
+	lwc1	$f0, 0(a0)
+	j exit
+	div.s	$f0, $f0, $f2
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+div1:
+	.float	10.0
+	.globl div2
+div2:
+	.float	0.0
Index: /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/test.elf.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/test.elf.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpe_delayslot/test.elf.txt	(revision 232)
@@ -0,0 +1,185 @@
+
+test.elf:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+bfc00000 <_start>:
+bfc00000:	3c1ad020 	lui	k0,0xd020
+bfc00004:	3c1be000 	lui	k1,0xe000
+bfc00008:	3c1d003f 	lui	sp,0x3f
+bfc0000c:	37bdfff0 	ori	sp,sp,0xfff0
+bfc00010:	3c04bfc0 	lui	a0,0xbfc0
+bfc00014:	24840155 	addiu	a0,a0,341
+bfc00018:	0ff000e4 	jal	bfc00390 <print>
+bfc0001c:	00000000 	nop
+bfc00020:	3c042040 	lui	a0,0x2040
+bfc00024:	40846000 	mtc0	a0,c0_status
+bfc00028:	3c040000 	lui	a0,0x0
+bfc0002c:	24840008 	addiu	a0,a0,8
+bfc00030:	c4820000 	lwc1	$f2,0(a0)
+bfc00034:	3c040000 	lui	a0,0x0
+bfc00038:	2484000c 	addiu	a0,a0,12
+bfc0003c:	c4800000 	lwc1	$f0,0(a0)
+bfc00040:	0bf00016 	j	bfc00058 <exit>
+bfc00044:	46020003 	div.s	$f0,$f0,$f2
+bfc00048:	24040002 	li	a0,2
+bfc0004c:	af640000 	sw	a0,0(k1)
+bfc00050:	0bf00014 	j	bfc00050 <_start+0x50>
+bfc00054:	00000000 	nop
+
+bfc00058 <exit>:
+bfc00058:	00402021 	move	a0,v0
+bfc0005c:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00060:	00000000 	nop
+bfc00064:	24040020 	li	a0,32
+bfc00068:	a3440000 	sb	a0,0(k0)
+bfc0006c:	00602021 	move	a0,v1
+bfc00070:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00074:	00000000 	nop
+bfc00078:	2404000a 	li	a0,10
+bfc0007c:	a3440000 	sb	a0,0(k0)
+bfc00080:	24040000 	li	a0,0
+bfc00084:	af640000 	sw	a0,0(k1)
+bfc00088:	0bf00022 	j	bfc00088 <exit+0x30>
+bfc0008c:	00000000 	nop
+
+bfc00090 <excep>:
+bfc00090:	3c04bfc0 	lui	a0,0xbfc0
+bfc00094:	24840138 	addiu	a0,a0,312
+bfc00098:	0ff000e4 	jal	bfc00390 <print>
+bfc0009c:	00000000 	nop
+bfc000a0:	40046000 	mfc0	a0,c0_status
+bfc000a4:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000a8:	00000000 	nop
+bfc000ac:	3c04bfc0 	lui	a0,0xbfc0
+bfc000b0:	24840140 	addiu	a0,a0,320
+bfc000b4:	0ff000e4 	jal	bfc00390 <print>
+bfc000b8:	00000000 	nop
+bfc000bc:	40046800 	mfc0	a0,c0_cause
+bfc000c0:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000c4:	00000000 	nop
+bfc000c8:	3c04bfc0 	lui	a0,0xbfc0
+bfc000cc:	24840148 	addiu	a0,a0,328
+bfc000d0:	0ff000e4 	jal	bfc00390 <print>
+bfc000d4:	00000000 	nop
+bfc000d8:	40047000 	mfc0	a0,c0_epc
+bfc000dc:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000e0:	00000000 	nop
+bfc000e4:	3c04bfc0 	lui	a0,0xbfc0
+bfc000e8:	2484014d 	addiu	a0,a0,333
+bfc000ec:	0ff000e4 	jal	bfc00390 <print>
+bfc000f0:	00000000 	nop
+bfc000f4:	40044000 	mfc0	a0,c0_badvaddr
+bfc000f8:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000fc:	00000000 	nop
+bfc00100:	2404000a 	li	a0,10
+bfc00104:	a3440000 	sb	a0,0(k0)
+bfc00108:	3c04bfc0 	lui	a0,0xbfc0
+bfc0010c:	24840058 	addiu	a0,a0,88
+bfc00110:	40847000 	mtc0	a0,c0_epc
+bfc00114:	3402dead 	li	v0,0xdead
+bfc00118:	3403beef 	li	v1,0xbeef
+bfc0011c:	24070001 	li	a3,1
+bfc00120:	42000018 	eret
+bfc00124:	00000000 	nop
+bfc00128:	24040001 	li	a0,1
+bfc0012c:	af640000 	sw	a0,0(k1)
+bfc00130:	0bf0004c 	j	bfc00130 <excep+0xa0>
+bfc00134:	00000000 	nop
+
+bfc00138 <statusstr>:
+bfc00138:	74617473 	jalx	b185d1cc <_stack+0xb145d1dc>
+bfc0013c:	00207375 	0x207375
+
+bfc00140 <causestr>:
+bfc00140:	75616320 	jalx	b5858c80 <_stack+0xb5458c90>
+bfc00144:	00206573 	tltu	at,zero,0x195
+
+bfc00148 <pcstr>:
+bfc00148:	20637020 	addi	v1,v1,28704
+	...
+
+bfc0014d <badvastr>:
+bfc0014d:	6220      	sw	ra,128(sp)
+bfc0014f:	6461      	restore	8,ra,s0
+bfc00151:	6176      	btnez	bfc0023f <usrstr+0xe3>
+bfc00153:	0020      	addiu	s0,sp,128
+
+bfc00155 <startstr>:
+bfc00155:	7473      	cmpi	a0,115
+bfc00157:	7261      	cmpi	v0,97
+bfc00159:	0a74      	la	v0,bfc00328 <usrstr+0x1cc>
+	...
+
+bfc0015c <usrstr>:
+bfc0015c:	6d727375 	0x6d727375
+bfc00160:	0a65646f 	j	b99591bc <_stack+0xb95591cc>
+bfc00164:	00000000 	nop
+	...
+
+bfc00380 <evect>:
+bfc00380:	0bf00024 	j	bfc00090 <excep>
+bfc00384:	00000000 	nop
+	...
+
+bfc00390 <print>:
+bfc00390:	00804021 	move	t0,a0
+bfc00394:	81090000 	lb	t1,0(t0)
+bfc00398:	11200005 	beqz	t1,bfc003b0 <end>
+bfc0039c:	00000000 	nop
+bfc003a0:	a3490000 	sb	t1,0(k0)
+bfc003a4:	25080001 	addiu	t0,t0,1
+bfc003a8:	0bf000e5 	j	bfc00394 <print+0x4>
+bfc003ac:	00000000 	nop
+
+bfc003b0 <end>:
+bfc003b0:	03e00008 	jr	ra
+bfc003b4:	00000000 	nop
+
+bfc003b8 <printx>:
+bfc003b8:	00804021 	move	t0,a0
+bfc003bc:	24090030 	li	t1,48
+bfc003c0:	a3490000 	sb	t1,0(k0)
+bfc003c4:	24090078 	li	t1,120
+bfc003c8:	a3490000 	sb	t1,0(k0)
+bfc003cc:	24090008 	li	t1,8
+bfc003d0:	3c0af000 	lui	t2,0xf000
+bfc003d4:	010a5024 	and	t2,t0,t2
+bfc003d8:	000a5702 	srl	t2,t2,0x1c
+bfc003dc:	294b000a 	slti	t3,t2,10
+bfc003e0:	11600004 	beqz	t3,bfc003f4 <printx+0x3c>
+bfc003e4:	00000000 	nop
+bfc003e8:	214a0030 	addi	t2,t2,48
+bfc003ec:	0bf000fe 	j	bfc003f8 <printx+0x40>
+bfc003f0:	00000000 	nop
+bfc003f4:	214a0037 	addi	t2,t2,55
+bfc003f8:	a34a0000 	sb	t2,0(k0)
+bfc003fc:	2129ffff 	addi	t1,t1,-1
+bfc00400:	1d20fff3 	bgtz	t1,bfc003d0 <printx+0x18>
+bfc00404:	00084100 	sll	t0,t0,0x4
+bfc00408:	03e00008 	jr	ra
+bfc0040c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+bfc00410 <.reginfo>:
+bfc00410:	bc00009c 	cache	0x0,156(zero)
+bfc00414:	00000000 	nop
+bfc00418:	00000005 	0x5
+	...
+bfc00424:	00000010 	mfhi	zero
+
+Disassembly of section .data:
+
+00000000 <testval-0x4>:
+   0:	0000dead 	0xdead
+
+00000004 <testval>:
+   4:	0000beef 	0xbeef
+
+00000008 <div1>:
+   8:	41200000 	0x41200000
+
+0000000c <div2>:
+   c:	00000000 	nop
Index: /trunk/softs/tests_ccvcache_v4/test_fpediv/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpediv/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpediv/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_fpediv/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpediv/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpediv/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hstart
+0x00008F80
Index: /trunk/softs/tests_ccvcache_v4/test_fpediv/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpediv/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpediv/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000038 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_fpediv/run.out
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpediv/run.out	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpediv/run.out	(revision 232)
@@ -0,0 +1,22 @@
+
+             SystemC 2.2.0 --- Apr 14 2011 18:52:40
+        Copyright (c) 1996-2006 by all Contributors
+                    ALL RIGHTS RESERVED
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+start
+0x00008F80
+vci_exit terminate simulation, status 0d2
Index: /trunk/softs/tests_ccvcache_v4/test_fpediv/subr.o.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpediv/subr.o.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpediv/subr.o.txt	(revision 232)
@@ -0,0 +1,49 @@
+
+subr.o:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+00000000 <print>:
+   0:	00804021 	move	t0,a0
+   4:	81090000 	lb	t1,0(t0)
+   8:	11200005 	beqz	t1,20 <end>
+   c:	00000000 	nop
+  10:	a3490000 	sb	t1,0(k0)
+  14:	25080001 	addiu	t0,t0,1
+  18:	08000001 	j	4 <print+0x4>
+  1c:	00000000 	nop
+
+00000020 <end>:
+  20:	03e00008 	jr	ra
+  24:	00000000 	nop
+
+00000028 <printx>:
+  28:	00804021 	move	t0,a0
+  2c:	24090030 	li	t1,48
+  30:	a3490000 	sb	t1,0(k0)
+  34:	24090078 	li	t1,120
+  38:	a3490000 	sb	t1,0(k0)
+  3c:	24090008 	li	t1,8
+  40:	3c0af000 	lui	t2,0xf000
+  44:	010a5024 	and	t2,t0,t2
+  48:	000a5702 	srl	t2,t2,0x1c
+  4c:	294b000a 	slti	t3,t2,10
+  50:	11600004 	beqz	t3,64 <printx+0x3c>
+  54:	00000000 	nop
+  58:	214a0030 	addi	t2,t2,48
+  5c:	0800001a 	j	68 <printx+0x40>
+  60:	00000000 	nop
+  64:	214a0037 	addi	t2,t2,55
+  68:	a34a0000 	sb	t2,0(k0)
+  6c:	2129ffff 	addi	t1,t1,-1
+  70:	1d20fff3 	bgtz	t1,40 <printx+0x18>
+  74:	00084100 	sll	t0,t0,0x4
+  78:	03e00008 	jr	ra
+  7c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	84000f10 	lh	zero,3856(zero)
+	...
Index: /trunk/softs/tests_ccvcache_v4/test_fpediv/temp
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpediv/temp	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpediv/temp	(revision 232)
@@ -0,0 +1,4909 @@
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+****************** cycle 1 ************************************************
+PROC proc
+  <InsReq  invalid mode MODE_HYPER @ 0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 2 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 3 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 4 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 5 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 6 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 7 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 8 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 9 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 10 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 11 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 12 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 13 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1be000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 14 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 15 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 16 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x037bdfff0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 17 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 18 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840115 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 19 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 20 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 21 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c042040 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 22 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040846000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 23 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040f80 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 24 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x044c4f800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 25 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 26 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 27 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4820000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 28 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 29 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 30 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 31 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp    valid no error ins 0x3c1ad020>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 32 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00004>
+  <InsRsp    valid no error ins 0x3c1be000>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 33 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00008>
+  <InsRsp    valid no error ins 0x3c1d003f>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 34 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0000c>
+  <InsRsp    valid no error ins 0x37bdfff0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 35 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00010>
+  <InsRsp    valid no error ins 0x3c04bfc0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 36 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00014>
+  <InsRsp    valid no error ins 0x24840115>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 37 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00018>
+  <InsRsp    valid no error ins 0xff000e4>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 38 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0001c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 39 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 40 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00380  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 41 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 42 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 43 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 44 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 45 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 46 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 47 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 48 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 49 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 50 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 51 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 52 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 53 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 54 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x081090000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 55 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011200005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 56 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 57 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 58 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x025080001 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 59 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000e5 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 60 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 61 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 62 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 63 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 64 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 65 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 66 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 67 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 68 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 69 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 70 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0x4 / valid = 0 / line = 0x000000004
+****************** cycle 71 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00100  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 72 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 73 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 74 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 75 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 76 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 77 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 78 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+****************** cycle 79 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+****************** cycle 80 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000206573 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+****************** cycle 81 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x75616320 / way = 0 / set = 0x4 / word = 0
+****************** cycle 82 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x206573 / way = 0 / set = 0x4 / word = 0x1
+****************** cycle 83 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061622000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x20637020 / way = 0 / set = 0x4 / word = 0x2
+****************** cycle 84 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020617664 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x61622000 / way = 0 / set = 0x4 / word = 0x3
+****************** cycle 85 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061747300 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x20617664 / way = 0 / set = 0x4 / word = 0x4
+****************** cycle 86 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a7472 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x61747300 / way = 0 / set = 0x4 / word = 0x5
+****************** cycle 87 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x06d727375 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0xa7472 / way = 0 / set = 0x4 / word = 0x6
+****************** cycle 88 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00a65646f | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x6d727375 / way = 0 / set = 0x4 / word = 0x7
+****************** cycle 89 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0xa65646f / way = 0 / set = 0x4 / word = 0x8
+****************** cycle 90 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0x9
+****************** cycle 91 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xa
+****************** cycle 92 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xb
+****************** cycle 93 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xc
+****************** cycle 94 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xd
+****************** cycle 95 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xe
+****************** cycle 96 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xf
+****************** cycle 97 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 98 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 99 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 100 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 101 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 102 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 103 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 104 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000073  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 105 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 106 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 107 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 108 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 109 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 110 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 111 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 112 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 113 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 114 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 115 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 116 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 117 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 118 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 119 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 120 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 121 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 122 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 123 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 124 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 125 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 126 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000061  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 127 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 128 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 129 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 130 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 131 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 132 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 133 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 134 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 135 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 136 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 137 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000072  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 138 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 139 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 140 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 141 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 142 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 143 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 144 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 145 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 146 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 147 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 148 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 149 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 150 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 151 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 152 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 153 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 154 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 155 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 156 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 157 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 158 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 159 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 160 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 161 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 162 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b0>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 163 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 164 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00020>
+  <InsRsp    valid no error ins 0x3c042040>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 165 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00024>
+  <InsRsp    valid no error ins 0x40846000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 166 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00028>
+  <InsRsp    valid no error ins 0x24040f80>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 167 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0002c>
+  <InsRsp    valid no error ins 0x44c4f800>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 168 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00030>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 169 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x24840008>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 170 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00038>
+  <InsRsp    valid no error ins 0xc4820000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 171 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 172 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0 / valid = 0 / line = 0x000000000
+****************** cycle 173 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 174 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 175 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 176 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0
+  <MEMC.TGT_CMD_IDLE> Receive command from srcid 0x0000 / for address 0x000000000
+****************** cycle 177 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_READ | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+  <MEMC.TGT_CMD_READ> Push into read_fifo: address = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040
+****************** cycle 178 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_IDLE> Read request: srcid = 0 / address = 0 / nwords = 16
+****************** cycle 179 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_DIR_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_DIR_LOCK> Accessing directory:  address = 0 / hit = 0 / count = 0 / is_cnt = 0
+****************** cycle 180 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_LOCK> Check TRT: hit_read = 0 / hit_write = 0 / full = 0
+****************** cycle 181 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_SET | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_SET> Write in Transaction Table:  address = 0 / srcid = 0
+****************** cycle 182 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_REQ | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_REQ> Request GET transaction for address 0
+****************** cycle 183 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 184 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram
+****************** cycle 185 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_IDLE> Response from XRAM to a get transaction
+****************** cycle 186 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+****************** cycle 187 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 0 / data = 0xdead
+****************** cycle 188 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 1 / data = 0xbeef
+****************** cycle 189 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 2 / data = 0x41200000
+****************** cycle 190 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 3 / data = 0
+****************** cycle 191 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 4 / data = 0
+****************** cycle 192 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 5 / data = 0
+****************** cycle 193 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 6 / data = 0
+****************** cycle 194 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 7 / data = 0
+****************** cycle 195 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 8 / data = 0
+****************** cycle 196 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 9 / data = 0
+****************** cycle 197 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 10 / data = 0
+****************** cycle 198 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 11 / data = 0
+****************** cycle 199 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 12 / data = 0
+****************** cycle 200 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 13 / data = 0
+****************** cycle 201 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 14 / data = 0
+****************** cycle 202 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 15 / data = 0
+****************** cycle 203 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.XRAM_RSP_IDLE> Available cache line in TRT: index = 0
+****************** cycle 204 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
+****************** cycle 205 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
+  <MEMC.XRAM_RSP_DIR_LOCK> Get access to directory
+****************** cycle 206 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
+****************** cycle 207 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
+  <MEMC.XRAM_RSP_TRT_COPY> Select a slot:  way = 0 / set = 0 / inval_required = 0
+****************** cycle 208 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
+****************** cycle 209 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
+  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT
+****************** cycle 210 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT
+  <MEMC.XRAM_RSP_DIR_UPDT> Directory update:  way = 0 / set = 0 / count = 1 / is_cnt = 0
+****************** cycle 211 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP
+  <MEMC.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0 / nwords = 16
+****************** cycle 212 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 213 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xdead / cpt = 0
+****************** cycle 214 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xbeef / cpt = 0x1
+****************** cycle 215 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0x41200000 / cpt = 0x2
+****************** cycle 216 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x3
+****************** cycle 217 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x4
+****************** cycle 218 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x5
+****************** cycle 219 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xdead / way = 0 / set = 0 / word = 0
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x6
+****************** cycle 220 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xbeef / way = 0 / set = 0 / word = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x7
+****************** cycle 221 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0x41200000 / way = 0 / set = 0 / word = 0x2
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x8
+****************** cycle 222 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x3
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x9
+****************** cycle 223 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x4
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xa
+****************** cycle 224 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x5
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xb
+****************** cycle 225 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x6
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xc
+****************** cycle 226 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x7
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xd
+****************** cycle 227 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x8
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xe
+****************** cycle 228 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x9
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xf
+****************** cycle 229 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xa
+****************** cycle 230 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xb
+****************** cycle 231 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xc
+****************** cycle 232 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xd
+****************** cycle 233 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xe
+****************** cycle 234 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xf
+****************** cycle 235 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 236 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0x41200000>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 237 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 238 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00040  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 239 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 240 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 241 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 242 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 243 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 244 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 245 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 246 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 247 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4800000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 248 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046001003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 249 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046001003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 250 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x04444f800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 251 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 252 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 253 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02404000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 254 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 255 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 256 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 257 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 258 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 259 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 260 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0248400f8 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 261 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 262 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 263 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 264 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 265 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp    valid no error ins 0x2484000c>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 266 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00044>
+  <InsRsp    valid no error ins 0xc4800000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 267 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00048>
+  <InsRsp    valid no error ins 0x46001003>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 268 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0004c>
+  <InsRsp    valid no error ins 0x4444f800>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 269 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00050>
+  <InsRsp    valid no error ins 0xff000ee>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 270 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00054>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 271 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b8>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 272 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003bc>
+  <InsRsp    valid no error ins 0x24090030>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 273 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 274 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc003c0  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 275 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 276 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 277 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 278 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 279 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 280 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 281 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 282 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 283 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090078 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 284 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 285 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 286 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 287 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c0af000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 288 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0010a5024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 289 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a5702 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 290 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0294b000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 291 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011600004 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 292 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 293 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 294 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000fe | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 295 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 296 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0037 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 297 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a34a0000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 298 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02129ffff | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 299 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 300 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 301 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 302 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c4>
+  <InsRsp    valid no error ins 0x24090078>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 303 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c8>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 304 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 305 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 306 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 307 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 308 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 309 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 310 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 311 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 312 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 313 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 314 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 315 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000078  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 316 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 317 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00400  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 318 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 319 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 320 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 321 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 322 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 323 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 324 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 325 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 326 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 327 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000084100 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 328 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 329 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 330 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 331 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0bc000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 332 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 333 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 334 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 335 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 336 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 337 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 338 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 339 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 340 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 341 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 342 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 343 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 344 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 345 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 346 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 347 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 348 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 349 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 350 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 351 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 352 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 353 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 354 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 355 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 356 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 357 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 358 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 359 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 360 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 361 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 362 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 363 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 364 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 365 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 366 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 367 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 368 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 369 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 370 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 371 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 372 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 373 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 374 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 375 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 376 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 377 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 378 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 379 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 380 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 381 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 382 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 383 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 384 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 385 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 386 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 387 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 388 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 389 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 390 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 391 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 392 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 393 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 394 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 395 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 396 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 397 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 398 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000038  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 399 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 400 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 401 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 402 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 403 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 404 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 405 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f4>
+  <InsRsp    valid no error ins 0x214a0037>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 406 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 407 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 408 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 409 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000046  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 410 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 411 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 412 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 413 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 414 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 415 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 416 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 417 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 418 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 419 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 420 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 421 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 422 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000038  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 423 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 424 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 425 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 426 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 427 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 428 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 429 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 430 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 431 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 432 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 433 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 434 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 435 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 436 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00408>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 437 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0040c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 438 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00058>
+  <InsRsp    valid no error ins 0x2404000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 439 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0005c>
+  <InsRsp    valid no error ins 0xa3440000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 440 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00060>
+  <InsRsp    valid no error ins 0x24040002>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 441 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00064>
+  <InsRsp    valid no error ins 0xaf640000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 442 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 443 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 444 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 445 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 446 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 447 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 448 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 449 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 450 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 451 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 452 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 453 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 454 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 455 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 456 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 457 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0e0000000  wdata = 0x000000002  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 458 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 459 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 460 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+vci_exit terminate simulation, status 0x000000002
Index: /trunk/softs/tests_ccvcache_v4/test_fpediv/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpediv/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpediv/test.S	(revision 232)
@@ -0,0 +1,81 @@
+/*
+ * trap test: check that a we can generate a trap from FPE instruction
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV), enable cop1 */
+	lui	a0, 0x2040;
+	mtc0	a0, COP0_STATUS
+	/* enable COP1 exceptions */
+	li	a0, 0x0f80
+	ctc1	a0, $31
+#if 0
+	li	a0, 0xf000
+	ctc1	a0, $26
+#endif
+	la	a0, div1
+	lwc1	$f2, 0(a0)
+	la	a0, div2
+	lwc1	$f0, 0(a0)
+	div.s	$f0, $f2, $f0
+	cfc1	a0, $31
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl div1
+div1:
+	.float	10.0
+	.globl div2
+div2:
+	.float	0.0
Index: /trunk/softs/tests_ccvcache_v4/test_fpediv/test.elf.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_fpediv/test.elf.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_fpediv/test.elf.txt	(revision 232)
@@ -0,0 +1,167 @@
+
+test.elf:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+bfc00000 <_start>:
+bfc00000:	3c1ad020 	lui	k0,0xd020
+bfc00004:	3c1be000 	lui	k1,0xe000
+bfc00008:	3c1d003f 	lui	sp,0x3f
+bfc0000c:	37bdfff0 	ori	sp,sp,0xfff0
+bfc00010:	3c04bfc0 	lui	a0,0xbfc0
+bfc00014:	24840115 	addiu	a0,a0,277
+bfc00018:	0ff000e4 	jal	bfc00390 <print>
+bfc0001c:	00000000 	nop
+bfc00020:	3c042040 	lui	a0,0x2040
+bfc00024:	40846000 	mtc0	a0,c0_status
+bfc00028:	24040f80 	li	a0,3968
+bfc0002c:	44c4f800 	ctc1	a0,$31
+bfc00030:	3c040000 	lui	a0,0x0
+bfc00034:	24840008 	addiu	a0,a0,8
+bfc00038:	c4820000 	lwc1	$f2,0(a0)
+bfc0003c:	3c040000 	lui	a0,0x0
+bfc00040:	2484000c 	addiu	a0,a0,12
+bfc00044:	c4800000 	lwc1	$f0,0(a0)
+bfc00048:	46001003 	div.s	$f0,$f2,$f0
+bfc0004c:	4444f800 	cfc1	a0,$31
+bfc00050:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00054:	00000000 	nop
+bfc00058:	2404000a 	li	a0,10
+bfc0005c:	a3440000 	sb	a0,0(k0)
+bfc00060:	24040002 	li	a0,2
+bfc00064:	af640000 	sw	a0,0(k1)
+bfc00068:	0bf0001a 	j	bfc00068 <_start+0x68>
+bfc0006c:	00000000 	nop
+
+bfc00070 <excep>:
+bfc00070:	3c04bfc0 	lui	a0,0xbfc0
+bfc00074:	248400f8 	addiu	a0,a0,248
+bfc00078:	0ff000e4 	jal	bfc00390 <print>
+bfc0007c:	00000000 	nop
+bfc00080:	40046000 	mfc0	a0,c0_status
+bfc00084:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00088:	00000000 	nop
+bfc0008c:	3c04bfc0 	lui	a0,0xbfc0
+bfc00090:	24840100 	addiu	a0,a0,256
+bfc00094:	0ff000e4 	jal	bfc00390 <print>
+bfc00098:	00000000 	nop
+bfc0009c:	40046800 	mfc0	a0,c0_cause
+bfc000a0:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000a4:	00000000 	nop
+bfc000a8:	3c04bfc0 	lui	a0,0xbfc0
+bfc000ac:	24840108 	addiu	a0,a0,264
+bfc000b0:	0ff000e4 	jal	bfc00390 <print>
+bfc000b4:	00000000 	nop
+bfc000b8:	40047000 	mfc0	a0,c0_epc
+bfc000bc:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000c0:	00000000 	nop
+bfc000c4:	3c04bfc0 	lui	a0,0xbfc0
+bfc000c8:	2484010d 	addiu	a0,a0,269
+bfc000cc:	0ff000e4 	jal	bfc00390 <print>
+bfc000d0:	00000000 	nop
+bfc000d4:	40044000 	mfc0	a0,c0_badvaddr
+bfc000d8:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000dc:	00000000 	nop
+bfc000e0:	2404000a 	li	a0,10
+bfc000e4:	a3440000 	sb	a0,0(k0)
+bfc000e8:	24040000 	li	a0,0
+bfc000ec:	af640000 	sw	a0,0(k1)
+bfc000f0:	0bf0003c 	j	bfc000f0 <excep+0x80>
+bfc000f4:	00000000 	nop
+
+bfc000f8 <statusstr>:
+bfc000f8:	74617473 	jalx	b185d1cc <_stack+0xb145d1dc>
+bfc000fc:	00207375 	0x207375
+
+bfc00100 <causestr>:
+bfc00100:	75616320 	jalx	b5858c80 <_stack+0xb5458c90>
+bfc00104:	00206573 	tltu	at,zero,0x195
+
+bfc00108 <pcstr>:
+bfc00108:	20637020 	addi	v1,v1,28704
+	...
+
+bfc0010d <badvastr>:
+bfc0010d:	6220      	sw	ra,128(sp)
+bfc0010f:	6461      	restore	8,ra,s0
+bfc00111:	6176      	btnez	bfc001ff <usrstr+0xe3>
+bfc00113:	0020      	addiu	s0,sp,128
+
+bfc00115 <startstr>:
+bfc00115:	7473      	cmpi	a0,115
+bfc00117:	7261      	cmpi	v0,97
+bfc00119:	0a74      	la	v0,bfc002e8 <usrstr+0x1cc>
+	...
+
+bfc0011c <usrstr>:
+bfc0011c:	6d727375 	0x6d727375
+bfc00120:	0a65646f 	j	b99591bc <_stack+0xb95591cc>
+bfc00124:	00000000 	nop
+	...
+
+bfc00380 <evect>:
+bfc00380:	0bf0001c 	j	bfc00070 <excep>
+bfc00384:	00000000 	nop
+	...
+
+bfc00390 <print>:
+bfc00390:	00804021 	move	t0,a0
+bfc00394:	81090000 	lb	t1,0(t0)
+bfc00398:	11200005 	beqz	t1,bfc003b0 <end>
+bfc0039c:	00000000 	nop
+bfc003a0:	a3490000 	sb	t1,0(k0)
+bfc003a4:	25080001 	addiu	t0,t0,1
+bfc003a8:	0bf000e5 	j	bfc00394 <print+0x4>
+bfc003ac:	00000000 	nop
+
+bfc003b0 <end>:
+bfc003b0:	03e00008 	jr	ra
+bfc003b4:	00000000 	nop
+
+bfc003b8 <printx>:
+bfc003b8:	00804021 	move	t0,a0
+bfc003bc:	24090030 	li	t1,48
+bfc003c0:	a3490000 	sb	t1,0(k0)
+bfc003c4:	24090078 	li	t1,120
+bfc003c8:	a3490000 	sb	t1,0(k0)
+bfc003cc:	24090008 	li	t1,8
+bfc003d0:	3c0af000 	lui	t2,0xf000
+bfc003d4:	010a5024 	and	t2,t0,t2
+bfc003d8:	000a5702 	srl	t2,t2,0x1c
+bfc003dc:	294b000a 	slti	t3,t2,10
+bfc003e0:	11600004 	beqz	t3,bfc003f4 <printx+0x3c>
+bfc003e4:	00000000 	nop
+bfc003e8:	214a0030 	addi	t2,t2,48
+bfc003ec:	0bf000fe 	j	bfc003f8 <printx+0x40>
+bfc003f0:	00000000 	nop
+bfc003f4:	214a0037 	addi	t2,t2,55
+bfc003f8:	a34a0000 	sb	t2,0(k0)
+bfc003fc:	2129ffff 	addi	t1,t1,-1
+bfc00400:	1d20fff3 	bgtz	t1,bfc003d0 <printx+0x18>
+bfc00404:	00084100 	sll	t0,t0,0x4
+bfc00408:	03e00008 	jr	ra
+bfc0040c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+bfc00410 <.reginfo>:
+bfc00410:	bc000010 	cache	0x0,16(zero)
+bfc00414:	00000000 	nop
+bfc00418:	00000005 	0x5
+	...
+bfc00424:	00000010 	mfhi	zero
+
+Disassembly of section .data:
+
+00000000 <testval-0x4>:
+   0:	0000dead 	0xdead
+
+00000004 <testval>:
+   4:	0000beef 	0xbeef
+
+00000008 <div1>:
+   8:	41200000 	0x41200000
+
+0000000c <div2>:
+   c:	00000000 	nop
Index: /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/mtty0	(revision 232)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started before DMA 0x0000DEAD
+mmu started after DMA 0x0000BEEF
+mmu started after FLUSH 0x0000BEEF
Index: /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/run	(revision 232)
@@ -0,0 +1,38 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started before DMA 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started after DMA 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started after FLUSH 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 3 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_icache_inval_pa/test.S	(revision 232)
@@ -0,0 +1,167 @@
+/*
+ * cache inval test: check that VC_ICACHE_INVAL_PA does the job
+ * on a cc_vcache, the cache invalidation/update should be done by hardware
+ * and VC_ICACHE_INVAL_PA should not be needed.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+#define TEST_ADDRESS 0x200000
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_a)
+	#copy 'doload' to TEST_ADDRESS 
+	la	a1, DMA_BASE
+	la	a0, doload 
+	sw      a0, DMA_SRC(a1)
+	la	a0, TEST_ADDRESS
+	sw      a0, DMA_DST(a1)
+        li      a0, 8
+	sw      a0, DMA_LEN(a1) /* start DMA */
+loop1:
+	lw      a0, DMA_LEN(a1)
+	bne     a0, zero, loop1;
+	nop
+	sw	zero, DMA_RESET(a1)
+
+	la	a0, TEST_ADDRESS
+	jalr	a0
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	#copy 'doload2' to TEST_ADDRESS 
+	la	a1, DMA_BASE
+	la	a0, doload2
+	sw      a0, DMA_SRC(a1)
+	la	a0, TEST_ADDRESS
+	sw      a0, DMA_DST(a1)
+        li      a0, 8
+	sw      a0, DMA_LEN(a1) /* start DMA */
+loop2:
+	lw      a0, DMA_LEN(a1)
+	bne     a0, zero, loop2;
+	nop
+	sw	zero, DMA_RESET(a1)
+
+	PRINT(mmustr_b)
+	la	a0, TEST_ADDRESS
+	jalr	a0
+	nop
+	PRINTX
+	PUTCHAR('\n')
+
+        la      a0, TEST_ADDRESS
+	mtc2    a0, VC_DATA_LO
+	mtc2    zero, VC_DATA_HI
+	mtc2    zero, VC_ICACHE_INVAL_PA
+	addi	a0, a0, 4
+	mtc2    a0, VC_DATA_LO
+	mtc2    zero, VC_DATA_HI
+	mtc2    zero, VC_ICACHE_INVAL_PA
+	nop
+
+	PRINT(mmustr_c)
+	la	a0, TEST_ADDRESS
+	jalr	a0
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+
+	.globl doload2
+doload2:
+	jr ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(2)
+	nop
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started before DMA \0"
+mmustr_b: .ascii "mmu started after DMA \0"
+mmustr_c: .ascii "mmu started after FLUSH \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1_a + (TEST_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (TEST_ADDRESS >> 21) /* map PA 0x200000 at VA 0x200000, read-only/exec */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + (DMA_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval/test.S	(revision 232)
@@ -0,0 +1,158 @@
+/*
+ * itlb inval: a write to a PTE2 should invalidate the corresponding
+ * itlb and dtlb entries. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	/* cause a DTLB miss */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* cause a itlb miss */
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, pte2_a
+	la	a0, (BOOT_ADDRESS+0x2000) >> 12
+	sw	a0, 12(t0) /* change PTE2 */
+	sync
+1:
+	ll	a0, 8(t0)
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 8(t0)
+	beqz	a0, 1b
+	nop
+
+	/* now we should get the second values */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	jal	doload 
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval:	.word MAGIC2
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval2:	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PTP and
+ * check that the ITLB has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval2/test.S	(revision 232)
@@ -0,0 +1,160 @@
+/*
+ * itlb inval: a write to a PTE2 should invalidate the corresponding
+ * itlb and dtlb entries. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	/* cause a DTLB miss */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* cause a itlb miss */
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, pte2_a
+	mtc2 	t0, VC_DTLB_INVAL /* force tlb miss on write */
+	la	a0, (BOOT_ADDRESS+0x2000) >> 12
+	sw	a0, 12(t0) /* change PTE2 */
+	sync
+1:
+	ll	a0, 8(t0)
+	mtc2 	t0, VC_DTLB_INVAL /* force tlb miss on write */
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 8(t0)
+	beqz	a0, 1b
+	nop
+
+	/* now we should get the second values */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	jal	doload 
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval:	.word MAGIC2
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval2:	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PTP and
+ * check that the ITLB has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval3/test.S	(revision 232)
@@ -0,0 +1,162 @@
+/*
+ * itlb inval: a write to a PTE2 should invalidate the corresponding
+ * itlb and dtlb entries. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	/* cause a DTLB miss */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* cause a itlb miss */
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, pte2_a
+	mtc2 	t0, VC_DATA_L /* force dcache miss on write */
+	mtc2	zero, VC_DATA_H
+	mtc2	zero, VC_DCACHE_INVAL_PA
+	la	a0, (BOOT_ADDRESS+0x2000) >> 12
+	sw	a0, 12(t0) /* change PTE2 */
+	sync
+1:
+	ll	a0, 8(t0)
+	mtc2 	t0, VC_DTLB_INVAL /* force tlb miss on write */
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 8(t0)
+	beqz	a0, 1b
+	nop
+
+	/* now we should get the second values */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	jal	doload 
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval:	.word MAGIC2
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval2:	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PTP and
+ * check that the ITLB has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_inval4/test.S	(revision 232)
@@ -0,0 +1,166 @@
+/*
+ * itlb inval: a write to a PTD1 should invalidate the corresponding
+ * itlb and dtlb entries. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	/* cause a DTLB miss */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* cause a itlb miss */
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, pte1_ac
+1:
+	ll	a0, 0(t0)
+	la	a0, (0x2000 >> 12) | PTE1_V | PTE1_T /* check real address of pet2_b */
+	sc	a0, 0(t0) /* change PTD1 */
+	beqz	a0, 1b
+	nop
+
+	/* now we should get the second values */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	jal	doload 
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval:	.word MAGIC2
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval2:	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PD and
+ * check that the TLBs has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12 /* address of doload */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte2_b:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x2000) >> 12 /* address of doload2 */
+	.org pte2_b + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+pte1_ac:
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started ptpr_b 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started ptpr_a 0x0000BEEF 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_idtlb_ptprinval/test.S	(revision 232)
@@ -0,0 +1,173 @@
+/*
+ * itlb inval on PTPR write: check that no stale entry exists in the itlb
+ * after MMU context swicth
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_b
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_b)
+	la	t0, rodata
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+#if 0 /* works with this - this shows the old pte2 address is cached */
+	la	a0, pte2_a
+	lw	a1, 12(a0)
+	la	a0, pte2_b
+	sw	a1, 12(a0)
+#endif
+	PRINT(mmustr_a)
+	la	t0, rodata
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started ptpr_a \0"
+mmustr_b: .ascii "mmu started ptpr_b \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+rodata:
+	.word MAGIC2
+	.org doload + 0x1000 /* in the second page, mapped by pte1_b */
+	jr ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(2)
+	nop
+	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * two PD with two different PTE2 for code: check that itlb points to
+ * the right one by executing 2 different code at the same address
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+pte2_b:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x2000) >> 12
+	.org pte2_b + 4092
+	.word 0
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
+	.globl pte1_b
+pte1_b:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_b + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */
+	.org pte1_b + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_b + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_b + 8188
+	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400103 cause 0x00000100 pc 0xBFC00038 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt/test.S	(revision 232)
@@ -0,0 +1,80 @@
+/*
+ * Check that we can take an interrupt, and return from it.
+ * We use a software-triggerted interrupt.
+ */
+#include <registers.h>
+#include <misc.h>
+
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enbale soft interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0101;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* generate an interrupt */
+	mfc0	a0, COP0_CAUSE
+	nop
+	ori	a0, 0x0100
+	mtc0	a0, COP0_CAUSE
+	li	a0, MAGIC1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should end here after taking the exeption */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	xori	a0, 0x100
+	mtc0	a0, COP0_CAUSE
+	nop
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/mtty0	(revision 232)
@@ -0,0 +1,3 @@
+[20hstart
+status 0x00400403 cause 0x80000000 pc 0xBFC00054 badva 0x00000000 xicu 0x00000000
+end 0x0000DEAD
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^end 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400403 cause 0x80000000 pc 0xBFC00054 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F][01][0-9A-F]00$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_delayslot/test.S	(revision 232)
@@ -0,0 +1,110 @@
+/*
+ * Check that we can take an interrupt from the xicu timer0
+ */
+#include <registers.h>
+#include <misc.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+	/*
+	 * interrupt in 42 cycles.
+	 * Without cache this takes us to the delay slot of the jump.
+	 */
+	li	a0, 42
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	nop
+	nop
+	nop
+	j	end
+	li 	s0, MAGIC1
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+end:
+	PRINT(endstr)
+	move	a0, s0
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^eret$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400103 cause 0x00000100 pc 0xBFC00038 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_epc_modify/test.S	(revision 232)
@@ -0,0 +1,85 @@
+/*
+ * Check that we can take an interrupt, and return to a different address.
+ * We use a software-triggerted interrupt.
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enbale soft interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0101;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* generate an interrupt */
+	mfc0	a0, COP0_CAUSE
+	nop
+	ori	a0, 0x0100
+	mtc0	a0, COP0_CAUSE
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+exret:
+	PRINT(eretstr)
+	EXIT(0)
+
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	xori	a0, 0x100
+	mtc0	a0, COP0_CAUSE
+	nop
+	la	a0, exret
+	mtc0	a0, COP0_EXPC
+	nop
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+include ../Makefile.inc
+CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY}
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/run	(revision 232)
@@ -0,0 +1,31 @@
+#!/bin/sh 
+
+check_output()
+{
+	egrep "^end 0x0000DEAE$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep ^status run.out
+	return 0;
+}
+echo 
+for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70; do
+	echo -n "    DELAY=$i: "
+	make INTERRUPT_DELAY=$i --quiet || exit 1
+	../platform/simulation.x > run.out 2>&1 
+	if [ $? -eq 0 ]; then
+		if check_output; then
+			echo "test passsed";
+			make --quiet clean
+		else
+			echo "test FAILED"
+			exit 1
+		fi
+	else 
+		echo "test FAILED"
+		exit 1
+	fi
+done
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_extended/test.S	(revision 232)
@@ -0,0 +1,137 @@
+/*
+ * Check interrupt/return with interrup occuring at various points in
+ * the software. Cache is enabled to we have on interrupt/cycle
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 */
+	li	a0, INTERRUPT_DELAY
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	li      s0, MAGIC1
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	nop
+	j	end
+	addiu	s0, s0, 5
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+end:
+	PRINT(endstr)
+	move	a0, s0
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (XICU_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+include ../Makefile.inc
+CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY}
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/run	(revision 232)
@@ -0,0 +1,31 @@
+#!/bin/sh 
+
+check_output()
+{
+	egrep "^end 0x0000DEAD 0x0000BEF0$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400403" run.out
+	return 0;
+}
+echo 
+for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99; do
+	echo -n "    DELAY=$i: "
+	make INTERRUPT_DELAY=$i --quiet || exit 1
+	../platform/simulation.x > run.out 2>&1 
+	if [ $? -eq 0 ]; then
+		if check_output; then
+			echo "test passsed";
+			make --quiet clean
+		else
+			echo "test FAILED"
+			exit 1
+		fi
+	else 
+		echo "test FAILED"
+		exit 1
+	fi
+done
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_extended2/test.S	(revision 232)
@@ -0,0 +1,181 @@
+/*
+ * Check interrupt/return with interrup occuring at various points in
+ * the software. Cache is enabled to we have on interrupt/cycle
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+
+	/* reset cop0 status (keep BEV), enable soft interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0101;
+	mtc0    a0, COP0_STATUS
+#if 1
+	/* trigger soft interrupt, so that exept is in cache */
+	mfc0    a0, COP0_CAUSE
+	ori     a0, 0x0100
+	mtc0    a0, COP0_CAUSE
+	nop
+#endif
+
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 */
+	la	t0, XICU_BASE
+	li	a0, INTERRUPT_DELAY
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	li      s0, MAGIC1
+	li      s1, MAGIC2
+	addiu	s0, s0, -1
+	jal	incr
+	nop
+	addiu	s0, s0, -1
+	jal	incr
+	nop
+	addiu	s0, s0, -1
+	jal	incr
+	nop
+	addiu	s0, s0, -1
+	jal	incr
+	nop
+	j	end
+	addiu	s1, s1, 5
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+	.align 6
+	nop
+incr:
+	addiu	s1, s1, -1
+	j	ra
+	addiu	s0, s0, 1
+
+	.align 6
+end:
+	PRINT(endstr)
+	move	a0, s0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+fail:
+	EXIT(4)
+
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl excep
+excep:
+	.set noreorder
+	move	s2, ra
+	mfc0	a0, COP0_CAUSE
+	andi	a0, a0, 0x0400
+	beq	a0, zero, softint
+	nop
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+softint:
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	/* fluch cache line of incr */
+	la	a0, incr
+	mtc2	a0, VC_ICACHE_INVAL
+	//mtc2	a0, VC_ITLB_INVAL
+	move	ra, s2
+	la	s2, fail
+	eret
+	/* we should not end there */
+	EXIT(3)
+	.data
+myvar:	.word 0
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (XICU_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x0040CC03 cause 0x00000400 pc 0xBFC00088 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F]0001$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_external_mask/test.S	(revision 232)
@@ -0,0 +1,110 @@
+/*
+ * Check that we can mask an external interrupt
+ */
+#include <registers.h>
+#include <misc.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	ori	a0, 0xc801;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* interrupt in 10 cycles */
+	li	a0, 10
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* interrupts still disabled at the MIPS level */
+	li	a0, MAGIC1
+	PRINTX
+	PUTCHAR('\n')
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	/* enable interrupt from timer0 */
+	mfc0	a0, COP0_STATUS
+	ori	a0, 0x0400
+	mtc0	a0, COP0_STATUS
+
+	nop
+	nop
+
+1:	j 1b
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	/* we should end there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run	(revision 232)
@@ -0,0 +1,12 @@
+#!/bin/sh 
+
+make --quiet || exit 1
+../platform/simulation.x > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	echo "test passsed";
+	make --quiet clean
+	exit 0;
+fi
+echo "test failed"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run.out
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run.out	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run.out	(revision 232)
@@ -0,0 +1,41356 @@
+ ____            _                  ____    _    ____ ____  
+/ ___| _   _ ___| |_ ___ _ __ ___  / ___|  / \  / ___/ ___| 
+\___ \| | | / __| __/ _ \ '_ ` _ \| |     / _ \ \___ \___ \ 
+ ___) | |_| \__ \ ||  __/ | | | | | |___ / ___ \ ___) |__) |
+|____/ \__, |___/\__\___|_| |_| |_|\____/_/   \_\____/____/ 
+       |___/                                                
+
+         Cycle Accurate System Simulator
+            ASIM/LIP6/UPMC
+            E-mail support:  Richard.Buchmann@asim.lip6.fr
+            Contributors : Richard Buchmann, Sami Taktak,
+                           Paul-Jerome Kingbo, Frédéric Pétrot,
+                           Nicolas Pouillon
+
+                           Last change : Mar 10 2008
+
+Loading at 0xbfc00000 size 4194304: .text .reginfo 
+Loading at 0 size 4194304: .data 
+mips0 executeNCycles( 1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c1ad020>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00000 NPC: 0xbfc00004 Ins: 0x3c1ad020
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x1a i: 0xd020
+ r rs: 0 rt: 26 rd: 26 sh: 0 func: 0x20
+ V rs: 0 rt: 0
+  0: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: 00000000 27: 00000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x3c1ad020>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c1be000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00004 NPC: 0xbfc00008 Ins: 0x3c1be000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x1b i: 0xe000
+ r rs: 0 rt: 27 rd: 28 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: 00000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x3c1be000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40806800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00008 NPC: 0xbfc0000c Ins: 0x40806800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x10 (cop0)
+ i rs: 0x4 rt: 0 i: 0x6800
+ r rs: 4 rt: 0 rd: 13 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x40806800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0000c NPC: 0xbfc00010 Ins: 0x3c040000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x3c040000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24842000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00010 NPC: 0xbfc00014 Ins: 0x24842000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x2000
+ r rs: 4 rt: 4 rd: 4 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x24842000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x42342>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00014 NPC: 0xbfc00018 Ins: 0x42342
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0x4 i: 0x2342
+ r rs: 0 rt: 4 rd: 4 sh: 13 func: 0x2
+ V rs: 0 rt: 0x2000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00002000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x42342>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x48840000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00018 NPC: 0xbfc0001c Ins: 0x48840000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x12 (cop2)
+ i rs: 0x4 rt: 0x4 i: 0
+ r rs: 4 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type XTN_WRITE (XTN_PTPR) wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x48840000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0001c NPC: 0xbfc00020 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2404000f>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00020 NPC: 0xbfc00024 Ins: 0x2404000f
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0xf
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xf
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x2404000f>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x48840800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00024 NPC: 0xbfc00028 Ins: 0x48840800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x12 (cop2)
+ i rs: 0x4 rt: 0x4 i: 0x800
+ r rs: 4 rt: 4 rd: 1 sh: 0 func: 0
+ V rs: 0xf rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000f 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x48840800>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00028 NPC: 0xbfc0002c Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000f 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc0002c m_jump_pc: 0xbfc00030 m_ifetch_addr: 0xbfc0002c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840248>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0002c NPC: 0xbfc00030 Ins: 0x24840248
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x248
+ r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x8
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00030 m_jump_pc: 0xbfc00034 m_ifetch_addr: 0xbfc00030
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00030 NPC: 0xbfc00034 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00034 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00034
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00034 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00248 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00248 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00248 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x72617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00248 rt: 0xbfc00248
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00249 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00248 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x72617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00249 rt: 0xbfc00249
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024a rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00248 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x72617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0024a rt: 0xbfc0024a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024b rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00248 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x72617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x72
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x72 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x72
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0024b rt: 0xbfc0024b
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024c rt: 0x72
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0024c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20000a74>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 count: 0x1 le: 0 old: 0x72 from_mem: 0x20000a74 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+rmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0024c rt: 0xbfc0024c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024d rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0024c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20000a74>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 count: 0x1 le: 0x1 old: 0x74 from_mem: 0x20000a74 mask: 0xffffffff new_data: 0xa
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0xa rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0024d rt: 0xbfc0024d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024e rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0024c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20000a74>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 count: 0x1 le: 0x2 old: 0xa from_mem: 0x20000a74 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00038 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00038 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00038 m_jump_pc: 0xbfc0003c m_ifetch_addr: 0xbfc00038
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00038 NPC: 0xbfc0003c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xbfc0024e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0003c m_jump_pc: 0xbfc00040 m_ifetch_addr: 0xbfc0003c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040180>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0003c NPC: 0xbfc00040 Ins: 0x8d040180
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x180
+ r rs: 8 rt: 4 rd: 0 sh: 6 func: 0
+ V rs: 0xd8200000 rt: 0xbfc00248
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200180 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0xbfc00248 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc00040 NPC: 0xbfc00044 Ins: 0x24040001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0x1
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0x1
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00044 m_jump_pc: 0xbfc00048 m_ifetch_addr: 0xbfc00044
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad040280>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00044 NPC: 0xbfc00048 Ins: 0xad040280
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x4 i: 0x280
+ r rs: 8 rt: 4 rd: 0 sh: 10 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200280 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00048 NPC: 0xbfc0004c Ins: 0x3410beef
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xd (ori)
+ i rs: 0 rt: 0x10 i: 0xbeef
+ r rs: 0 rt: 16 rd: 23 sh: 27 func: 0x2f
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0004c m_jump_pc: 0xbfc00050 m_ifetch_addr: 0xbfc0004c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24120001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0004c NPC: 0xbfc00050 Ins: 0x24120001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x12 i: 0x1
+ r rs: 0 rt: 18 rd: 0 sh: 0 func: 0x1
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00050 m_jump_pc: 0xbfc00054 m_ifetch_addr: 0xbfc00050
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad120080>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00050 NPC: 0xbfc00054 Ins: 0xad120080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x12 i: 0x80
+ r rs: 8 rt: 18 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00054 m_jump_pc: 0xbfc00058 m_ifetch_addr: 0xbfc00054
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040180>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00054 NPC: 0xbfc00058 Ins: 0x8d040180
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x180
+ r rs: 8 rt: 4 rd: 0 sh: 6 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200180 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0x1 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc00058 NPC: 0xbfc0005c Ins: 0x3c040040
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0x40
+ r rs: 0 rt: 4 rd: 0 sh: 1 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0005c m_jump_pc: 0xbfc00060 m_ifetch_addr: 0xbfc0005c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840401>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0005c NPC: 0xbfc00060 Ins: 0x24840401
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x401
+ r rs: 4 rt: 4 rd: 0 sh: 16 func: 0x1
+ V rs: 0x400000 rt: 0x400000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00060 m_jump_pc: 0xbfc00064 m_ifetch_addr: 0xbfc00060
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40846000>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00060 NPC: 0xbfc00064 Ins: 0x40846000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x10 (cop0)
+ i rs: 0x4 rt: 0x4 i: 0x6000
+ r rs: 4 rt: 4 rd: 12 sh: 0 func: 0
+ V rs: 0x400401 rt: 0x400401
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00064 m_jump_pc: 0xbfc00068 m_ifetch_addr: 0xbfc00064
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00064 NPC: 0xbfc00068 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 exception: 0
+ m_ins: 0 epc: bfc00068 error_epc: 0 bar: d8200180 cause.xcode: 0 .bd: 0 .ip: 4 status.exl: 1 .erl: 0 exception address: bfc00380
+mips0 executeNCycles( 1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x4d
+ r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd
+ V rs: 0xbfc00038 rt: 0xbeef
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xbeef rt: 0xbeef
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xd8200000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad000080>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0 i: 0x80
+ r rs: 8 rt: 0 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x400401
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840224>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x224
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00038 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00224 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00225 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00225 rt: 0xbfc00225
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00226 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00226 rt: 0xbfc00226
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00227 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00227 rt: 0xbfc00227
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00228 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00228 rt: 0xbfc00228
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00229 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00229 rt: 0xbfc00229
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022a rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022a rt: 0xbfc0022a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022b rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00150 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6000
+ r rs: 0 rt: 4 rd: 12 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0x400403 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x400403 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4004030 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4004030
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40040300 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40040300
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x403000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x403000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4030000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4030000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40300000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40300000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x3000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x3000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x30000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x3 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x33 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0015c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+3mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840234>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x234
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00234 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00235 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x70 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x70 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00235 rt: 0xbfc00235
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00236 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+pmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00236 rt: 0xbfc00236
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00237 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00237 rt: 0xbfc00237
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00238 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0016c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40047000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x7000
+ r rs: 0 rt: 4 rd: 14 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00068 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xbfc00068 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xb0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xb rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xb rt: 0xb
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x42 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xbfc00068
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xfc000680 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xf rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xf rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xfc000680
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc0006800 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xc rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xc rt: 0xc
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x43 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc0006800
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Fmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x68000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x68000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x680000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x680000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x6800000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x6800000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x68000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x60000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 60000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x6 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x36
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x36 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x68000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x36
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x80000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x80000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 80000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+6mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x8 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x38
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x80000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00178 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xbfc00068
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+8mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2484022c>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x22c
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022c rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022d rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022d rt: 0xbfc0022d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022e rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022e rt: 0xbfc0022e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022f rt: 0xbfc0022f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00230 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00230 rt: 0xbfc00230
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00231 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x65 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x65 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00231 rt: 0xbfc00231
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00232 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+emips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00232 rt: 0xbfc00232
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00233 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00188 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6800
+ r rs: 0 rt: 4 rd: 13 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x38
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00194 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840239>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x239
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00239 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023a rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x62 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x62 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023a rt: 0xbfc0023a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023b rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023b rt: 0xbfc0023b
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023c rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x64 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x64 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023c rt: 0xbfc0023c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023d rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x76 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x76 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+dmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023d rt: 0xbfc0023d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023e rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+vmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023e rt: 0xbfc0023e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023f rt: 0xbfc0023f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00240 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001a4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40044000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x4000
+ r rs: 0 rt: 4 rd: 8 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001b0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840241>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x241
+ r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00241 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00242 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x78 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00242 rt: 0xbfc00242
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00243 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x69 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x69 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00243 rt: 0xbfc00243
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00244 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+imips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00244 rt: 0xbfc00244
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00245 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00245 rt: 0xbfc00245
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00246 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00246 rt: 0xbfc00246
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00247 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001c0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xbfc00247
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040780>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x780
+ r rs: 8 rt: 4 rd: 0 sh: 30 func: 0
+ V rs: 0xd8200000 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200780 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001d0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2404000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0xa
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3440000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x4 i: 0
+ r rs: 26 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x32530001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xc (andi)
+ i rs: 0x12 rt: 0x13 i: 0x1
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12600002>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x13 rt: 0 i: 0x2
+ r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e4 m_ifetch_addr: 0xbfc001e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e0 NPC: 0xbfc001e4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e4 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26100001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e4 NPC: 0xbfc001e8 Ins: 0x26100001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0x1
+ r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbeee rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26520001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x12 rt: 0x12 i: 0x1
+ r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24130184>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x13 i: 0x184
+ r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12530008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x12 rt: 0x13 i: 0x8
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8
+ V rs: 0x2 rt: 0x184
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x129842>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x12 i: 0x9842
+ r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2
+ V rs: 0 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad130080>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x13 i: 0x80
+ r rs: 8 rt: 19 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x42000018>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0x10 rt: 0 i: 0x18
+ r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18
+ V rs: 0xbeef rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 ERET  exl jump_pc: bfc0006c
+mips0 m_next_pc: 0xbfc00068 m_jump_pc: 0xbfc0006c m_ifetch_addr: 0xbfc00068
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410dead>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00068 NPC: 0xbfc0006c Ins: 0x3410dead
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0xd (ori)
+ i rs: 0 rt: 0x10 i: 0xdead
+ r rs: 0 rt: 16 rd: 27 sh: 26 func: 0x2d
+ V rs: 0 rt: 0xbeef
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0006c m_jump_pc: 0xbfc00070 m_ifetch_addr: 0xbfc0006c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0006c NPC: 0xbfc00070 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdead rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00070 m_jump_pc: 0xbfc00074 m_ifetch_addr: 0xbfc00070
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00070 NPC: 0xbfc00074 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeac rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00074 m_jump_pc: 0xbfc00078 m_ifetch_addr: 0xbfc00074
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00074 NPC: 0xbfc00078 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeab rt: 0xdeab
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 exception: 0
+ m_ins: 9 epc: bfc00078 error_epc: 0 bar: d8200080 cause.xcode: 0 .bd: 0 .ip: 4 status.exl: 1 .erl: 0 exception address: bfc00380
+mips0 executeNCycles( 1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x4d
+ r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd
+ V rs: 0xbfc001d0 rt: 0xdeaa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeaa rt: 0xdeaa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xd8200000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad000080>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0 i: 0x80
+ r rs: 8 rt: 0 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840224>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x224
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00224 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00225 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00225 rt: 0xbfc00225
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00226 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00226 rt: 0xbfc00226
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00227 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00227 rt: 0xbfc00227
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00228 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00228 rt: 0xbfc00228
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00229 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00229 rt: 0xbfc00229
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022a rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022a rt: 0xbfc0022a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022b rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00150 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6000
+ r rs: 0 rt: 4 rd: 12 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0x400403 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x400403 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4004030 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4004030
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40040300 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40040300
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x403000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x403000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4030000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4030000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40300000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40300000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x3000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x3000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x30000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x3 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x33 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0015c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+3mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840234>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x234
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00234 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00235 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x70 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x70 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00235 rt: 0xbfc00235
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00236 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+pmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00236 rt: 0xbfc00236
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00237 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00237 rt: 0xbfc00237
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00238 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0016c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40047000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x7000
+ r rs: 0 rt: 4 rd: 14 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00078 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xbfc00078 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xb0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xb rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xb rt: 0xb
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x42 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xbfc00078
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xfc000780 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xf rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xf rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xfc000780
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc0007800 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xc rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xc rt: 0xc
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x43 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc0007800
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Fmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x78000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x78000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x780000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x780000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x7800000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x7800000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x78000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x70000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 70000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x7 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x37
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x37 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x78000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x37
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x80000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x80000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 80000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+7mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x8 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x38
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x80000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00178 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xbfc00078
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+8mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2484022c>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x22c
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022c rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022d rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022d rt: 0xbfc0022d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022e rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022e rt: 0xbfc0022e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022f rt: 0xbfc0022f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00230 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00230 rt: 0xbfc00230
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00231 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x65 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x65 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00231 rt: 0xbfc00231
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00232 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+emips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00232 rt: 0xbfc00232
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00233 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00188 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6800
+ r rs: 0 rt: 4 rd: 13 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x38
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00194 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840239>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x239
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00239 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023a rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x62 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x62 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023a rt: 0xbfc0023a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023b rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023b rt: 0xbfc0023b
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023c rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x64 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x64 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023c rt: 0xbfc0023c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023d rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x76 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x76 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+dmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023d rt: 0xbfc0023d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023e rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+vmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023e rt: 0xbfc0023e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023f rt: 0xbfc0023f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00240 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001a4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40044000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x4000
+ r rs: 0 rt: 4 rd: 8 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001b0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840241>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x241
+ r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00241 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00242 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x78 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00242 rt: 0xbfc00242
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00243 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x69 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x69 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00243 rt: 0xbfc00243
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00244 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+imips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00244 rt: 0xbfc00244
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00245 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00245 rt: 0xbfc00245
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00246 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00246 rt: 0xbfc00246
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00247 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001c0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xbfc00247
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040780>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x780
+ r rs: 8 rt: 4 rd: 0 sh: 30 func: 0
+ V rs: 0xd8200000 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200780 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001d0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2404000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0xa
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3440000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x4 i: 0
+ r rs: 26 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x32530001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xc (andi)
+ i rs: 0x12 rt: 0x13 i: 0x1
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1
+ V rs: 0x2 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12600002>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x13 rt: 0 i: 0x2
+ r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e0 NPC: 0xbfc001e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26520001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x12 rt: 0x12 i: 0x1
+ r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24130184>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x13 i: 0x184
+ r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12530008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x12 rt: 0x13 i: 0x8
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8
+ V rs: 0x3 rt: 0x184
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x129842>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x12 i: 0x9842
+ r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2
+ V rs: 0 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad130080>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x13 i: 0x80
+ r rs: 8 rt: 19 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x42000018>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0x10 rt: 0 i: 0x18
+ r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18
+ V rs: 0xdea9 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 ERET  exl jump_pc: bfc0007c
+mips0 m_next_pc: 0xbfc00078 m_jump_pc: 0xbfc0007c m_ifetch_addr: 0xbfc00078
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00078 NPC: 0xbfc0007c Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdea9 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0007c m_jump_pc: 0xbfc00080 m_ifetch_addr: 0xbfc0007c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0007c NPC: 0xbfc00080 Ins: 0xbf00030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x30
+ r rs: 31 rt: 16 rd: 0 sh: 0 func: 0x30
+ V rs: 0xbfc001d0 rt: 0xdea8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea8 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26100005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00080 NPC: 0xbfc000c0 Ins: 0x26100005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0x5
+ r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x5
+ V rs: 0xdea8 rt: 0xdea8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea8 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 exception: 0
+ m_ins: 0x9 epc: 0xbfc000c0 error_epc: 0 bar: 0xd8200080 cause.xcode: 0 .bd: 0 .ip: 0x4 status.exl: 0x1 .erl: 0 exception address: 0xbfc00380
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x4d
+ r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd
+ V rs: 0xbfc001d0 rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdead rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xd8200000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad000080>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0 i: 0x80
+ r rs: 8 rt: 0 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840224>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x224
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00224 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00225 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00225 rt: 0xbfc00225
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00226 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00226 rt: 0xbfc00226
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00227 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00227 rt: 0xbfc00227
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00228 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00228 rt: 0xbfc00228
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00229 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00229 rt: 0xbfc00229
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022a rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022a rt: 0xbfc0022a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022b rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00150 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6000
+ r rs: 0 rt: 4 rd: 12 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0x400403 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x400403 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4004030 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4004030
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40040300 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40040300
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x403000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x403000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4030000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4030000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40300000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40300000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x3000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x3000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x30000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x3 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x33 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0015c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+3mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840234>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x234
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00234 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00235 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x70 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x70 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00235 rt: 0xbfc00235
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00236 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+pmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00236 rt: 0xbfc00236
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00237 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00237 rt: 0xbfc00237
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00238 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0016c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40047000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x7000
+ r rs: 0 rt: 4 rd: 14 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc000c0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xbfc000c0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xb0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xb rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xb rt: 0xb
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x42 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xbfc000c0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xfc000c00 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xf rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xf rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xfc000c00
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc000c000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xc rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xc rt: 0xc
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x43 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc000c000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Fmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc0000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc0000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc00000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc0000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: c0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xc rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 0000000c 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xc rt: 0xc
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x43 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00178 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xbfc000c0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2484022c>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x22c
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022c rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022d rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022d rt: 0xbfc0022d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022e rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022e rt: 0xbfc0022e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022f rt: 0xbfc0022f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00230 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00230 rt: 0xbfc00230
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00231 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x65 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x65 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00231 rt: 0xbfc00231
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00232 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+emips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00232 rt: 0xbfc00232
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00233 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00188 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6800
+ r rs: 0 rt: 4 rd: 13 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00194 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840239>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x239
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00239 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023a rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x62 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x62 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023a rt: 0xbfc0023a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023b rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023b rt: 0xbfc0023b
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023c rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x64 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x64 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023c rt: 0xbfc0023c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023d rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x76 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x76 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+dmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023d rt: 0xbfc0023d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023e rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+vmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023e rt: 0xbfc0023e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023f rt: 0xbfc0023f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00240 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001a4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40044000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x4000
+ r rs: 0 rt: 4 rd: 8 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001b0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840241>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x241
+ r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00241 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00242 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x78 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00242 rt: 0xbfc00242
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00243 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x69 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x69 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00243 rt: 0xbfc00243
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00244 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+imips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00244 rt: 0xbfc00244
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00245 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00245 rt: 0xbfc00245
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00246 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00246 rt: 0xbfc00246
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00247 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001c0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xbfc00247
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040780>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x780
+ r rs: 8 rt: 4 rd: 0 sh: 30 func: 0
+ V rs: 0xd8200000 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200780 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001d0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2404000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0xa
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3440000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x4 i: 0
+ r rs: 26 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x32530001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xc (andi)
+ i rs: 0x12 rt: 0x13 i: 0x1
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1
+ V rs: 0x3 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12600002>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x13 rt: 0 i: 0x2
+ r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e4 m_ifetch_addr: 0xbfc001e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e0 NPC: 0xbfc001e4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e4 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26100001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e4 NPC: 0xbfc001e8 Ins: 0x26100001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0x1
+ r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x1
+ V rs: 0xdeac rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26520001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x12 rt: 0x12 i: 0x1
+ r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24130184>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x13 i: 0x184
+ r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12530008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x12 rt: 0x13 i: 0x8
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8
+ V rs: 0x4 rt: 0x184
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x129842>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x12 i: 0x9842
+ r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2
+ V rs: 0 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad130080>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x13 i: 0x80
+ r rs: 8 rt: 19 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0x2 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x42000018>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0x10 rt: 0 i: 0x18
+ r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18
+ V rs: 0xdead rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 ERET  exl jump_pc: bfc000c4
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000c0 NPC: 0xbfc000c4 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdead rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000c4 m_jump_pc: 0xbfc000c8 m_ifetch_addr: 0xbfc000c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3411dead>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000c4 NPC: 0xbfc000c8 Ins: 0x3411dead
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0xd (ori)
+ i rs: 0 rt: 0x11 i: 0xdead
+ r rs: 0 rt: 17 rd: 27 sh: 26 func: 0x2d
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000c8 m_jump_pc: 0xbfc000cc m_ifetch_addr: 0xbfc000c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1211ffe9>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000c8 NPC: 0xbfc000cc Ins: 0x1211ffe9
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x4 (beq)
+ i rs: 0x10 rt: 0x11 i: 0xffe9
+ r rs: 16 rt: 17 rd: 31 sh: 31 func: 0x29
+ V rs: 0xdeac rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000cc m_jump_pc: 0xbfc000d0 m_ifetch_addr: 0xbfc000cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000cc NPC: 0xbfc000d0 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeac rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000d0 m_jump_pc: 0xbfc000d4 m_ifetch_addr: 0xbfc000d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000d0 NPC: 0xbfc000d4 Ins: 0x24040001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0x1
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0x1
+ V rs: 0 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000d4 m_jump_pc: 0xbfc000d8 m_ifetch_addr: 0xbfc000d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xaf640000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000d4 NPC: 0xbfc000d8 Ins: 0xaf640000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x2b (sw)
+ i rs: 0x1b rt: 0x4 i: 0
+ r rs: 27 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0xe0000000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xe0000000 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 exception: 0
+ m_ins: 0x2 epc: 0xbfc000d8 error_epc: 0 bar: 0xe0000000 cause.xcode: 0 .bd: 0 .ip: 0x4 status.exl: 0x1 .erl: 0 exception address: 0xbfc00380
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x4d
+ r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd
+ V rs: 0xbfc001d0 rt: 0xdeab
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeab rt: 0xdeab
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xd8200000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad000080>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0 i: 0x80
+ r rs: 8 rt: 0 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+vci_exit terminate simulation, status 0x1
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/test.S	(revision 232)
@@ -0,0 +1,166 @@
+/*
+ * Check interrupt/return with interrup occuring at various points in
+ * the software. Cache is enabled to we have on interrupt/cycle
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 */
+	li	s2, 1
+	sw	s2, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	nop
+	li      s0, MAGIC1
+	addiu	s0, s0, -1
+loop:	
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	j	bla
+	addiu	s0, s0, 5
+	EXIT(1)
+	addiu	s0, s0, -1
+	.align 6
+bla:
+	addiu	s0, s0, -1
+	li		s1, MAGIC1
+	beq	    s0, s1, loop
+	addiu	s0, s0, -1
+
+	/* we should not end there */
+	EXIT(1)
+
+	.align 6
+end:
+	PRINT(endstr)
+	move	a0, s0
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+perstr: .ascii " period \0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl excep
+excep:
+	.set noreorder
+	addiu	s0, s0, -10
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+//	PRINT(perstr)
+//	move a0, s2
+//	PRINTX
+//
+	PUTCHAR('\n')
+
+#if 0
+	andi s3, s2, 1
+	beqz s3, noflush
+#endif
+	addiu	s0, s0, 10
+
+#if 1
+	// Flush cache of jump routine
+	la s3, bla
+	mtc2 s3, VC_ICACHE_INVAL
+	mtc2 s3, VC_ITLB_INVAL
+#endif
+		
+noflush:
+	addiu s2, s2, 1
+	li s3, 194*2
+	beq s2, s3, end2
+	srl s3, s2, 1
+	la	t0, XICU_BASE
+	sw	s3, XICU_PTI_PER(0)(t0)
+	eret
+	/* we should not end there */
+	EXIT(1)
+end2:
+	EXIT(0)
+
+	.data
+myvar:	.word 0
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (XICU_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x0040FF03 cause 0x00000100 pc 0xBFC00074 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_interrupt_mask/test.S	(revision 232)
@@ -0,0 +1,95 @@
+/*
+ * Check that the interrupt mask in status is properly handled:
+ * we generate a software-triggerted interrupt with interrupt enabled but
+ * the software interrupt masked. Later we unmask it.
+ */
+#include <registers.h>
+#include <misc.h>
+
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enbale interrupts but mask IM0 */
+	lui     a0, 0x0040;
+	ori	a0, 0xfe01;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* generate an interrupt */
+	mfc0	a0, COP0_CAUSE
+	nop
+	ori	a0, 0x0100
+	mtc0	a0, COP0_CAUSE
+	li	a0, MAGIC1
+	PRINTX
+	PUTCHAR('\n')
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	/* unmask the interrupt */
+	mfc0	a0, COP0_STATUS
+	nop
+	ori	a0, 0x0100
+	mtc0	a0, COP0_STATUS
+	/* we should end here after taking the exeption */
+	li	a0, MAGIC2
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	xori	a0, 0x100
+	mtc0	a0, COP0_CAUSE
+	nop
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_inval/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_inval/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_inval/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_inval/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_inval/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_inval/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_inval/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_inval/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_inval/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000DEAD status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_inval/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_inval/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_inval/test.S	(revision 232)
@@ -0,0 +1,135 @@
+/*
+ * itlb inval: a write to VC_ITLB_INVAL should invalidate the corresponding
+ * itlb entry. On a ccvcache, VC_ITLB_INVAL should not be needed, and
+ * the first access after clearing pte2_a should fail
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+	la	a0, pte2_a
+	sw	zero, 8(a0) /* invalidate PTE2 */
+	sync
+	la      a0, pte2_a /* make the sync synchronous */
+	jal	doload /* TLB entry not invalidated yet, we can do this */
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, doload
+	mtc2	a0, VC_ITLB_INVAL /* invalidate VA */
+	jal	doload /* this should fail now */
+	nop
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_inval2/test.S	(revision 232)
@@ -0,0 +1,142 @@
+/*
+ * itlb inval: a write to a PTE2 should invalidate the corresponding
+ * itlb entry. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, pte2_a
+	la	a0, (BOOT_ADDRESS+0x2000) >> 12
+	sw	a0, 12(t0) /* change PTE2 */
+	sync
+1:
+	ll	a0, 8(t0)
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 8(t0)
+	beqz	a0, 1b
+	nop
+
+	jal	doload /* now we should get the second value */
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PTP and
+ * check that the ITLB has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started ptpr_b 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started ptpr_a 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_itlb_ptprinval/test.S	(revision 232)
@@ -0,0 +1,162 @@
+/*
+ * itlb inval on PTPR write: check that no stale entry exists in the itlb
+ * after MMU context swicth
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_b
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_b)
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+#if 0 /* works with this - this shows the old pte2 address is cached */
+	la	a0, pte2_a
+	lw	a1, 12(a0)
+	la	a0, pte2_b
+	sw	a1, 12(a0)
+#endif
+	PRINT(mmustr_a)
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started ptpr_a \0"
+mmustr_b: .ascii "mmu started ptpr_b \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+	.org doload + 0x1000 /* in the second page, mapped by pte1_b */
+	jr ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(2)
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * two PD with two different PTE2 for code: check that itlb points to
+ * the right one by executing 2 different code at the same address
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+pte2_b:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x2000) >> 12
+	.org pte2_b + 4092
+	.word 0
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
+	.globl pte1_b
+pte1_b:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_b + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */
+	.org pte1_b + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_b + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_b + 8188
+	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_llsc/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_llsc/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_llsc/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_llsc/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_llsc/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_llsc/run	(revision 232)
@@ -0,0 +1,26 @@
+#!/bin/sh 
+
+check_output()
+{
+	egrep "^0x00000000 0xAC4000FF 0xAC4000FF 0x00000000$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+../platform/simulation.x > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_llsc/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_llsc/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_llsc/test.S	(revision 232)
@@ -0,0 +1,104 @@
+/*
+ * Check interraction between cached read/write and ll/sc
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	/* make sure myvar is in cache */
+	la	s1, myvar 
+	lw	a0, 0(s1)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* now write to myvar via ll/sc
+	la	s1, myvar 
+1:
+	ll	a0, 0(s1)
+	li	a1, MAGIC2
+	sc	a1, 0(s1)
+	beqz	a1, 2b
+	nop
+
+	/* restore myvar value via normal write */
+	li	a1, MAGIC1
+	sw	a1, 0(s1)
+
+	/* read myvar */
+	lw	a0, 0(s1)
+	PRINTX
+	PUTCHAR('\n');
+	
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+myvar:	.word MAGIC1
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_mmu_basic/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_mmu_basic/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_mmu_basic/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_mmu_basic/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_mmu_basic/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_mmu_basic/mtty0	(revision 232)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started
+0x00200000: 0x0000DEAD
+0x00000000: status 0x00400006 cause 0x0000001C pc 0xBFC00098 badva 0x00000000
Index: /trunk/softs/tests_ccvcache_v4/test_mmu_basic/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_mmu_basic/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_mmu_basic/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00200000: 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^0x00000000: status 0x00400006 cause 0x0000001C pc 0xBFC00098 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_mmu_basic/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_mmu_basic/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_mmu_basic/test.S	(revision 232)
@@ -0,0 +1,102 @@
+/*
+ * Basic MMU checks: we can read mapped addresses, we can't read unmapped
+ * addresses
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/* we can read our magic number at 0x00200000 */
+	la	s0, 0x00200000
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	lw	a0, 0(s0)
+	PRINTX
+	PUTCHAR('\n')
+	/* but not at 0x00000000 */
+	la	s0, 0x00000000
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	lw	a0, 0(s0) /* this should trigger the exception */
+	PRINTX
+
+	/* we shouldn't get there */
+        EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	li	a0, '\n'
+	sb	a0, 0(k0)
+
+        EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+testval:
+	.word MAGIC1
+	.align 13
+	.globl pte1
+pte1:
+	.word 0x0                            /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x8A000000 0xAA000000 0xAA000000
Index: /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2i_ref/test.S	(revision 232)
@@ -0,0 +1,144 @@
+/*
+ * instruction fetch causes the PTE_L bit to be set
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la	s0, pte2_a
+	lw	s1, 8(s0)
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	beq	a0, a1, fail /* PTE2_L already set, not good */
+	nop
+	jal	doload /* cause page to be referenced */
+	nop
+	lw	s1, 8(s0)
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set not good */
+	nop
+	/* check again, using ll */
+	ll	s1, 8(s0)
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set not good */
+	nop
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2ll_ref/test.S	(revision 232)
@@ -0,0 +1,132 @@
+/*
+ * pte2d_ref: a ll to data should set referenced bit in PTE
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la 	s0, pte2_a
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	beq	a0, a1, fail /* PTE2_L already set, not good */
+	nop
+
+	la	t0, testval + 0x00200000
+	ll 	a0, 0(t0); /* cause page to be referenced */
+
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	/* check again, using ll */
+	ll	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2lw_ref/test.S	(revision 232)
@@ -0,0 +1,132 @@
+/*
+ * pte2d_ref: a lw to data should set referenced bit in PTE
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la 	s0, pte2_a
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	beq	a0, a1, fail /* PTE2_L already set, not good */
+	nop
+
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0); /* cause page to be referenced */
+
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	/* check again, using ll */
+	ll	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/mtty0	(revision 232)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x8E000000 0xAE400000 0xAE400000
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8E000000 0xAE400000 0xAE400000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/test.S	(revision 232)
@@ -0,0 +1,137 @@
+/*
+ * pte2d_ref: a sc to data should set the dirty bits in PTE
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la 	s0, pte2_a
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, zero, fail /* PTE2_L or PTE2_D already set, not good */
+	nop
+
+	la	t0, testval + 0x00200000
+	la	a1, MAGIC3
+1:
+	ll	a0, 0(t0)
+	sc 	a1, 0(t0); /* cause page to be referenced and dirty */
+	beqz	a1, 1b
+	nop
+
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	/* check again, using ll */
+	ll	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X | PTE2_W
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/vcitty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/vcitty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sc_dirty/vcitty0	(revision 232)
@@ -0,0 +1,1 @@
+[20hstart
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/Makefile	(revision 232)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/ldscript
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/ldscript	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/ldscript	(revision 232)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8E000000 0xAE400000 0xAE400000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte2sw_dirty/test.S	(revision 232)
@@ -0,0 +1,132 @@
+/*
+ * pte2d_ref: a sw to data should set referenced and dirty bits in PTE
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la 	s0, pte2_a
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, zero, fail /* PTE2_L or PTE2_D already set, not good */
+	nop
+
+	la	t0, testval + 0x00200000
+	sw 	a0, 0(t0); /* cause page to be referenced and dirty */
+
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	/* check again, using ll */
+	ll	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X | PTE2_W
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: /trunk/softs/tests_ccvcache_v4/test_pte_llsc/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte_llsc/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte_llsc/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_pte_llsc/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte_llsc/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte_llsc/mtty0	(revision 232)
@@ -0,0 +1,1 @@
+[20h0x00000000 0xAC4000FF 0xAC4000FF 0x00000000
Index: /trunk/softs/tests_ccvcache_v4/test_pte_llsc/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte_llsc/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte_llsc/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000000 0xAC4000FF 0xAC4000FF 0x00000000$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_pte_llsc/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_pte_llsc/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_pte_llsc/test.S	(revision 232)
@@ -0,0 +1,124 @@
+/*
+ * Check that the MMU doens't clobber the OS bits in PTEs, and interraction
+ * with ll/sc
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	/* do a swap of pte2[0] to make the entry valid */
+	la	s0, pte2 + 0x00200000
+1:	la	a1, PTE2_V | PTE2_C | PTE2_W | PTE2_os
+	ll	a0, 0(s0)
+	sc	a1, 0(s0)
+	beqz	a1, 1b
+	nop
+	PRINTX
+	PUTCHAR(' ')
+	/* now write to myvar via pte2[0] */
+	li	a0, MAGIC2
+	la	s1, myvar + 0x00200000
+	sw	a0, 0(s1)
+	/*
+	 * and invalidate pte2[0], again using a swap
+	 * check that we get the same value with lw and ll
+	 */
+	lw	s1, 0(s0)
+2:
+	move	a1, zero
+	ll	a0, 0(s0)
+	sc	a1, 0(s0)
+	beqz	a1, 2b
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	/* finally check what lw tells us now */
+	lw	a0, 0(s0)
+	PRINTX
+	PUTCHAR('\n')
+
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+myvar:	.word MAGIC1
+	.globl pte1
+pte2:
+	.align 12
+	.word 0	/* invalid for now */
+	.word 0x0000 >> 12 /* check real value of myvar */
+	.word PTE2_V | PTE2_C | PTE2_W | PTE2_os /* map pte2 too */
+	.word 0x1000 >> 12 /* check real address of pte2 */
+	.org pte2 + 4092
+	.word 0
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_ri/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ri/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ri/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_ri/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ri/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ri/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000028 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_ri/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ri/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ri/test.S	(revision 232)
@@ -0,0 +1,65 @@
+/*
+ * reserved instruction exception test: check that a reserved instruction
+ * generates an exception.
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	.word 0x60000000
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000028 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_ri_delayslot/test.S	(revision 232)
@@ -0,0 +1,86 @@
+/*
+ * reserved instruction exception test: check that a reserved instruction
+ * in a delay slot is properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	j	exit
+	.word 0x60000000
+	nop
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_sanity/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sanity/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sanity/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_sanity/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sanity/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sanity/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^hello world 0x1234ABCD$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_sanity/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sanity/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sanity/test.S	(revision 232)
@@ -0,0 +1,42 @@
+/*
+ * Basic sanity checks:
+ *   we can run a program
+ *   we can write to ram
+ *   we can write to the tty
+ *   we can make the simulator exit
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	la	t0, value
+	lw	t0, 0(t0)
+	la	t1, myvar
+	sw	t0, 0(t1)
+
+	la	a0, string
+	jal	print
+	nop
+
+	la	t1, myvar
+	lw	a0, 0(t1)
+	jal	printx
+	nop
+
+	li	a0, '\n'
+	sb	a0, 0(k0)
+
+	EXIT(0)
+
+	.rodata:
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sc_update_cache/test.S	(revision 232)
@@ -0,0 +1,80 @@
+/*
+ * Check that lc also updates the local L1 cache.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	/* enable caches */
+	li	a0, VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	/* fetch data in cache */
+	la	s0, myvar
+	lw	a0, 0(s0)
+	/* write magic value */
+	li	a0, MAGIC1
+	sw	a0, 0(s0)
+	/* ll/sc another value on the same address */
+2:
+	ll	a0, 0(s0)
+	PRINTX
+	PUTCHAR(' ')
+	li	a0, MAGIC2
+	sc	a0, 0(s0)
+	beqz	a0, 2b
+	/* now check that we got the right value in cache */
+	lw	a0, 0(s0)
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/test_sync/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sync/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sync/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_sync/mtty0
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sync/mtty0	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sync/mtty0	(revision 232)
@@ -0,0 +1,3 @@
+[20hstart
+mmustated
+@@@@@@
Index: /trunk/softs/tests_ccvcache_v4/test_sync/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sync/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sync/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh 
+
+check_output()
+{
+	egrep "^@@@@@@$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_sync/run.out
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sync/run.out	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sync/run.out	(revision 232)
@@ -0,0 +1,23 @@
+
+             SystemC 2.2.0 --- Apr 14 2011 18:52:40
+        Copyright (c) 1996-2006 by all Contributors
+                    ALL RIGHTS RESERVED
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x10 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text 
+Loading at 0 size 33554432: .data 
+start
+mmustrted@@@@@@
+Simulation exiting, retval=0
+couldn't find string in output - mtty not working ?
Index: /trunk/softs/tests_ccvcache_v4/test_sync/subr.o.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sync/subr.o.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sync/subr.o.txt	(revision 232)
@@ -0,0 +1,49 @@
+
+subr.o:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+00000000 <print>:
+   0:	00804021 	move	t0,a0
+   4:	81090000 	lb	t1,0(t0)
+   8:	11200005 	beqz	t1,20 <end>
+   c:	00000000 	nop
+  10:	a3490000 	sb	t1,0(k0)
+  14:	25080001 	addiu	t0,t0,1
+  18:	08000001 	j	4 <print+0x4>
+  1c:	00000000 	nop
+
+00000020 <end>:
+  20:	03e00008 	jr	ra
+  24:	00000000 	nop
+
+00000028 <printx>:
+  28:	00804021 	move	t0,a0
+  2c:	24090030 	li	t1,48
+  30:	a3490000 	sb	t1,0(k0)
+  34:	24090078 	li	t1,120
+  38:	a3490000 	sb	t1,0(k0)
+  3c:	24090008 	li	t1,8
+  40:	3c0af000 	lui	t2,0xf000
+  44:	010a5024 	and	t2,t0,t2
+  48:	000a5702 	srl	t2,t2,0x1c
+  4c:	294b000a 	slti	t3,t2,10
+  50:	11600004 	beqz	t3,64 <printx+0x3c>
+  54:	00000000 	nop
+  58:	214a0030 	addi	t2,t2,48
+  5c:	0800001a 	j	68 <printx+0x40>
+  60:	00000000 	nop
+  64:	214a0037 	addi	t2,t2,55
+  68:	a34a0000 	sb	t2,0(k0)
+  6c:	2129ffff 	addi	t1,t1,-1
+  70:	1d20fff3 	bgtz	t1,40 <printx+0x18>
+  74:	00084100 	sll	t0,t0,0x4
+  78:	03e00008 	jr	ra
+  7c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	84000f10 	lh	zero,3856(zero)
+	...
Index: /trunk/softs/tests_ccvcache_v4/test_sync/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sync/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sync/test.S	(revision 232)
@@ -0,0 +1,101 @@
+/*
+ * sync test: we map the tty cached. If sync doesn't work some chars will be
+ * lost because writes are combined in the write buffer.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/*
+	 * print several chars quickly: without sync not all of them will
+	 * show up
+	 */
+#define WRITE_TTY sb a0, 0(k0); sync
+	la a0, '@'
+	WRITE_TTY
+	WRITE_TTY
+	WRITE_TTY
+	WRITE_TTY
+	WRITE_TTY
+	WRITE_TTY
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 *cached!* */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: /trunk/softs/tests_ccvcache_v4/test_sync/test.elf.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sync/test.elf.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sync/test.elf.txt	(revision 232)
@@ -0,0 +1,181 @@
+
+test.elf:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+bfc00000 <_start>:
+bfc00000:	3c1ad020 	lui	k0,0xd020
+bfc00004:	3c1be000 	lui	k1,0xe000
+bfc00008:	3c04bfc0 	lui	a0,0xbfc0
+bfc0000c:	2484014a 	addiu	a0,a0,330
+bfc00010:	0ff000e2 	jal	bfc00388 <print>
+bfc00014:	00000000 	nop
+bfc00018:	3c040040 	lui	a0,0x40
+bfc0001c:	40846000 	mtc0	a0,c0_status
+bfc00020:	3c040000 	lui	a0,0x0
+bfc00024:	24842000 	addiu	a0,a0,8192
+bfc00028:	00042342 	srl	a0,a0,0xd
+bfc0002c:	48840000 	mtc2	a0,$0
+bfc00030:	00000000 	nop
+bfc00034:	2404000f 	li	a0,15
+bfc00038:	48840800 	mtc2	a0,$1
+bfc0003c:	3c04bfc0 	lui	a0,0xbfc0
+bfc00040:	2484013d 	addiu	a0,a0,317
+bfc00044:	0ff000e2 	jal	bfc00388 <print>
+bfc00048:	00000000 	nop
+bfc0004c:	24040040 	li	a0,64
+bfc00050:	a3440000 	sb	a0,0(k0)
+bfc00054:	0000000f 	sync
+bfc00058:	a3440000 	sb	a0,0(k0)
+bfc0005c:	0000000f 	sync
+bfc00060:	a3440000 	sb	a0,0(k0)
+bfc00064:	0000000f 	sync
+bfc00068:	a3440000 	sb	a0,0(k0)
+bfc0006c:	0000000f 	sync
+bfc00070:	a3440000 	sb	a0,0(k0)
+bfc00074:	0000000f 	sync
+bfc00078:	a3440000 	sb	a0,0(k0)
+bfc0007c:	0000000f 	sync
+bfc00080:	2404000a 	li	a0,10
+bfc00084:	a3440000 	sb	a0,0(k0)
+bfc00088:	24040000 	li	a0,0
+bfc0008c:	af640004 	sw	a0,4(k1)
+bfc00090:	0bf00024 	j	bfc00090 <_start+0x90>
+bfc00094:	00000000 	nop
+
+bfc00098 <excep>:
+bfc00098:	3c04bfc0 	lui	a0,0xbfc0
+bfc0009c:	24840120 	addiu	a0,a0,288
+bfc000a0:	0ff000e2 	jal	bfc00388 <print>
+bfc000a4:	00000000 	nop
+bfc000a8:	40046000 	mfc0	a0,c0_status
+bfc000ac:	0ff000ec 	jal	bfc003b0 <printx>
+bfc000b0:	00000000 	nop
+bfc000b4:	3c04bfc0 	lui	a0,0xbfc0
+bfc000b8:	24840128 	addiu	a0,a0,296
+bfc000bc:	0ff000e2 	jal	bfc00388 <print>
+bfc000c0:	00000000 	nop
+bfc000c4:	40046800 	mfc0	a0,c0_cause
+bfc000c8:	0ff000ec 	jal	bfc003b0 <printx>
+bfc000cc:	00000000 	nop
+bfc000d0:	3c04bfc0 	lui	a0,0xbfc0
+bfc000d4:	24840130 	addiu	a0,a0,304
+bfc000d8:	0ff000e2 	jal	bfc00388 <print>
+bfc000dc:	00000000 	nop
+bfc000e0:	40047000 	mfc0	a0,c0_epc
+bfc000e4:	0ff000ec 	jal	bfc003b0 <printx>
+bfc000e8:	00000000 	nop
+bfc000ec:	3c04bfc0 	lui	a0,0xbfc0
+bfc000f0:	24840135 	addiu	a0,a0,309
+bfc000f4:	0ff000e2 	jal	bfc00388 <print>
+bfc000f8:	00000000 	nop
+bfc000fc:	40044000 	mfc0	a0,c0_badvaddr
+bfc00100:	0ff000ec 	jal	bfc003b0 <printx>
+bfc00104:	00000000 	nop
+bfc00108:	2404000a 	li	a0,10
+bfc0010c:	a3440000 	sb	a0,0(k0)
+bfc00110:	24040001 	li	a0,1
+bfc00114:	af640004 	sw	a0,4(k1)
+bfc00118:	0bf00046 	j	bfc00118 <excep+0x80>
+bfc0011c:	00000000 	nop
+
+bfc00120 <statusstr>:
+bfc00120:	74617473 	jalx	b185d1cc <_stack+0xb145d1dc>
+bfc00124:	00207375 	0x207375
+
+bfc00128 <causestr>:
+bfc00128:	75616320 	jalx	b5858c80 <_stack+0xb5458c90>
+bfc0012c:	00206573 	tltu	at,zero,0x195
+
+bfc00130 <pcstr>:
+bfc00130:	20637020 	addi	v1,v1,28704
+	...
+
+bfc00135 <badvastr>:
+bfc00135:	6220      	sw	ra,128(sp)
+bfc00137:	6461      	restore	8,ra,s0
+bfc00139:	6176      	btnez	bfc00227 <startstr+0xdd>
+bfc0013b:	0020      	addiu	s0,sp,128
+
+bfc0013d <mmustr>:
+bfc0013d:	6d6d      	li	a1,109
+bfc0013f:	2075      	beqz	s0,bfc0022b <startstr+0xe1>
+bfc00141:	7473      	cmpi	a0,115
+bfc00143:	7261      	cmpi	v0,97
+bfc00145:	6574      	move	s3,a0
+bfc00147:	0a64      	la	v0,bfc002d4 <startstr+0x18a>
+	...
+
+bfc0014a <startstr>:
+bfc0014a:	72617473 	0x72617473
+bfc0014e:	00000a74 	teq	zero,zero,0x29
+	...
+
+bfc00380 <evect>:
+bfc00380:	0bf00026 	j	bfc00098 <excep>
+bfc00384:	00000000 	nop
+
+bfc00388 <print>:
+bfc00388:	00804021 	move	t0,a0
+bfc0038c:	81090000 	lb	t1,0(t0)
+bfc00390:	11200005 	beqz	t1,bfc003a8 <end>
+bfc00394:	00000000 	nop
+bfc00398:	a3490000 	sb	t1,0(k0)
+bfc0039c:	25080001 	addiu	t0,t0,1
+bfc003a0:	0bf000e3 	j	bfc0038c <print+0x4>
+bfc003a4:	00000000 	nop
+
+bfc003a8 <end>:
+bfc003a8:	03e00008 	jr	ra
+bfc003ac:	00000000 	nop
+
+bfc003b0 <printx>:
+bfc003b0:	00804021 	move	t0,a0
+bfc003b4:	24090030 	li	t1,48
+bfc003b8:	a3490000 	sb	t1,0(k0)
+bfc003bc:	24090078 	li	t1,120
+bfc003c0:	a3490000 	sb	t1,0(k0)
+bfc003c4:	24090008 	li	t1,8
+bfc003c8:	3c0af000 	lui	t2,0xf000
+bfc003cc:	010a5024 	and	t2,t0,t2
+bfc003d0:	000a5702 	srl	t2,t2,0x1c
+bfc003d4:	294b000a 	slti	t3,t2,10
+bfc003d8:	11600004 	beqz	t3,bfc003ec <printx+0x3c>
+bfc003dc:	00000000 	nop
+bfc003e0:	214a0030 	addi	t2,t2,48
+bfc003e4:	0bf000fc 	j	bfc003f0 <printx+0x40>
+bfc003e8:	00000000 	nop
+bfc003ec:	214a0037 	addi	t2,t2,55
+bfc003f0:	a34a0000 	sb	t2,0(k0)
+bfc003f4:	2129ffff 	addi	t1,t1,-1
+bfc003f8:	1d20fff3 	bgtz	t1,bfc003c8 <printx+0x18>
+bfc003fc:	00084100 	sll	t0,t0,0x4
+bfc00400:	03e00008 	jr	ra
+bfc00404:	00000000 	nop
+
+Disassembly of section .data:
+
+00000000 <testval-0x4>:
+       0:	0000dead 	0xdead
+
+00000004 <testval>:
+       4:	0000beef 	0xbeef
+	...
+
+00002000 <pte1>:
+    2000:	8c000000 	lw	zero,0(zero)
+	...
+    37f8:	8a0005fe 	lwl	zero,1534(s0)
+	...
+    3a04:	8c000681 	lw	zero,1665(zero)
+	...
+    3c00:	84000700 	lh	zero,1792(zero)
+	...
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	9c000010 	0x9c000010
+	...
+  14:	00006000 	sll	t4,zero,0x0
Index: /trunk/softs/tests_ccvcache_v4/test_sync/test.o.txt
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_sync/test.o.txt	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_sync/test.o.txt	(revision 232)
@@ -0,0 +1,142 @@
+
+test.o:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+00000000 <_start>:
+   0:	3c1ad020 	lui	k0,0xd020
+   4:	3c1be000 	lui	k1,0xe000
+   8:	3c040000 	lui	a0,0x0
+   c:	2484014a 	addiu	a0,a0,330
+  10:	0c000000 	jal	0 <_start>
+  14:	00000000 	nop
+  18:	3c040040 	lui	a0,0x40
+  1c:	40846000 	mtc0	a0,c0_status
+  20:	3c040000 	lui	a0,0x0
+  24:	24840000 	addiu	a0,a0,0
+  28:	00042342 	srl	a0,a0,0xd
+  2c:	48840000 	mtc2	a0,$0
+  30:	00000000 	nop
+  34:	2404000f 	li	a0,15
+  38:	48840800 	mtc2	a0,$1
+  3c:	3c040000 	lui	a0,0x0
+  40:	2484013d 	addiu	a0,a0,317
+  44:	0c000000 	jal	0 <_start>
+  48:	00000000 	nop
+  4c:	24040040 	li	a0,64
+  50:	a3440000 	sb	a0,0(k0)
+  54:	0000000f 	sync
+  58:	a3440000 	sb	a0,0(k0)
+  5c:	0000000f 	sync
+  60:	a3440000 	sb	a0,0(k0)
+  64:	0000000f 	sync
+  68:	a3440000 	sb	a0,0(k0)
+  6c:	0000000f 	sync
+  70:	a3440000 	sb	a0,0(k0)
+  74:	0000000f 	sync
+  78:	a3440000 	sb	a0,0(k0)
+  7c:	0000000f 	sync
+  80:	2404000a 	li	a0,10
+  84:	a3440000 	sb	a0,0(k0)
+  88:	24040000 	li	a0,0
+  8c:	af640004 	sw	a0,4(k1)
+  90:	08000024 	j	90 <_start+0x90>
+  94:	00000000 	nop
+
+00000098 <excep>:
+  98:	3c040000 	lui	a0,0x0
+  9c:	24840120 	addiu	a0,a0,288
+  a0:	0c000000 	jal	0 <_start>
+  a4:	00000000 	nop
+  a8:	40046000 	mfc0	a0,c0_status
+  ac:	0c000000 	jal	0 <_start>
+  b0:	00000000 	nop
+  b4:	3c040000 	lui	a0,0x0
+  b8:	24840128 	addiu	a0,a0,296
+  bc:	0c000000 	jal	0 <_start>
+  c0:	00000000 	nop
+  c4:	40046800 	mfc0	a0,c0_cause
+  c8:	0c000000 	jal	0 <_start>
+  cc:	00000000 	nop
+  d0:	3c040000 	lui	a0,0x0
+  d4:	24840130 	addiu	a0,a0,304
+  d8:	0c000000 	jal	0 <_start>
+  dc:	00000000 	nop
+  e0:	40047000 	mfc0	a0,c0_epc
+  e4:	0c000000 	jal	0 <_start>
+  e8:	00000000 	nop
+  ec:	3c040000 	lui	a0,0x0
+  f0:	24840135 	addiu	a0,a0,309
+  f4:	0c000000 	jal	0 <_start>
+  f8:	00000000 	nop
+  fc:	40044000 	mfc0	a0,c0_badvaddr
+ 100:	0c000000 	jal	0 <_start>
+ 104:	00000000 	nop
+ 108:	2404000a 	li	a0,10
+ 10c:	a3440000 	sb	a0,0(k0)
+ 110:	24040001 	li	a0,1
+ 114:	af640004 	sw	a0,4(k1)
+ 118:	08000046 	j	118 <excep+0x80>
+ 11c:	00000000 	nop
+
+00000120 <statusstr>:
+ 120:	74617473 	jalx	185d1cc <pte1+0x185b1cc>
+ 124:	00207375 	0x207375
+
+00000128 <causestr>:
+ 128:	75616320 	jalx	5858c80 <pte1+0x5856c80>
+ 12c:	00206573 	tltu	at,zero,0x195
+
+00000130 <pcstr>:
+ 130:	20637020 	addi	v1,v1,28704
+	...
+
+00000135 <badvastr>:
+ 135:	6220      	sw	ra,128(sp)
+ 137:	6461      	restore	8,ra,s0
+ 139:	6176      	btnez	227 <startstr+0xdd>
+ 13b:	0020      	addiu	s0,sp,128
+
+0000013d <mmustr>:
+ 13d:	6d6d      	li	a1,109
+ 13f:	2075      	beqz	s0,22b <startstr+0xe1>
+ 141:	7473      	cmpi	a0,115
+ 143:	7261      	cmpi	v0,97
+ 145:	6574      	move	s3,a0
+ 147:	0a64      	la	v0,2d4 <startstr+0x18a>
+	...
+
+0000014a <startstr>:
+ 14a:	72617473 	0x72617473
+ 14e:	00000a74 	teq	zero,zero,0x29
+	...
+
+00000380 <evect>:
+ 380:	08000000 	j	0 <_start>
+ 384:	00000000 	nop
+
+Disassembly of section .data:
+
+00000000 <testval-0x4>:
+       0:	0000dead 	0xdead
+
+00000004 <testval>:
+       4:	0000beef 	0xbeef
+	...
+
+00002000 <pte1>:
+    2000:	8c000000 	lw	zero,0(zero)
+	...
+    37f8:	8a0005fe 	lwl	zero,1534(s0)
+	...
+    3a04:	8c000681 	lw	zero,1665(zero)
+	...
+    3c00:	84000700 	lh	zero,1792(zero)
+	...
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	9c000010 	0x9c000010
+	...
Index: /trunk/softs/tests_ccvcache_v4/test_syscall/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_syscall/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_syscall/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_syscall/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_syscall/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_syscall/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400012 cause 0x00000020 pc 0xBFC00050 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_syscall/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_syscall/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_syscall/test.S	(revision 232)
@@ -0,0 +1,91 @@
+/*
+ * syscall test: check that a syscall generates an exception, and we can
+ * return 
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	/* switch to user mode */
+	mfc0	a0, COP0_STATUS
+	ori	a0, 0x10
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	PRINT(usrstr)
+	syscall
+	bne a3, zero, exit
+	nop
+	/* we should not get there, a3 is not 0 */
+	EXIT(2)
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	mfc0	a0, COP0_EXPC
+	addiu	a0, a0, 4
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/run	(revision 232)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400012 cause 0x80000020 pc 0xBFC00050 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^usrmode$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_syscall_delayslot/test.S	(revision 232)
@@ -0,0 +1,90 @@
+/*
+ * syscall test: check that a syscall in a delay slot is properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	/* switch to user mode */
+	mfc0	a0, COP0_STATUS
+	ori	a0, 0x10
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	PRINT(usrstr)
+	j	exit
+	syscall
+	nop
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_trap/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_trap/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_trap/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_trap/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_trap/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_trap/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_trap/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_trap/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_trap/test.S	(revision 232)
@@ -0,0 +1,64 @@
+/*
+ * trap test: check that a we can generate a trap
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	teq	zero, zero
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_trap_delayslot/test.S	(revision 232)
@@ -0,0 +1,85 @@
+/*
+ * trap test: check that a trap in a delay slot is
+ * properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	j exit
+	teq	zero, zero
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: /trunk/softs/tests_ccvcache_v4/test_xicu_timer/Makefile
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_xicu_timer/Makefile	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_xicu_timer/Makefile	(revision 232)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: /trunk/softs/tests_ccvcache_v4/test_xicu_timer/run
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_xicu_timer/run	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_xicu_timer/run	(revision 232)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400403 cause 0x[08]0000400 pc 0xBFC00040 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F]0001$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: /trunk/softs/tests_ccvcache_v4/test_xicu_timer/test.S
===================================================================
--- /trunk/softs/tests_ccvcache_v4/test_xicu_timer/test.S	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/test_xicu_timer/test.S	(revision 232)
@@ -0,0 +1,89 @@
+/*
+ * Check that we can take an interrupt from the xicu timer0
+ */
+#include <registers.h>
+#include <misc.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* interrupt in 10 cycles */
+	li	a0, 10
+	sw	a0, XICU_PTI_PER(0)(t0)
+
+1:	j 1b
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	/* we should end there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: /trunk/softs/tests_ccvcache_v4/tmp
===================================================================
--- /trunk/softs/tests_ccvcache_v4/tmp	(revision 232)
+++ /trunk/softs/tests_ccvcache_v4/tmp	(revision 232)
@@ -0,0 +1,72 @@
+-n test_sanity: 
+-n test_exceptions: 
+-n test_mmu_basic: 
+test FAILED
+-n test_excep_ls: 
+test FAILED
+-n test_excep_ls_delayslot: 
+-n test_excep_ls_llsc: 
+test FAILED
+-n test_excep_if: 
+test FAILED
+-n test_excep_if_delayslot: 
+test FAILED
+-n test_excep_if_llsc: 
+test FAILED
+-n test_exception_epc_modify: 
+-n test_dtlb_inval: 
+-n test_dtlb_inval2: 
+test FAILED
+-n test_dtlb_inval3: 
+test FAILED
+-n test_itlb_inval: 
+-n test_itlb_inval2: 
+test FAILED
+-n test_idtlb_inval: 
+test FAILED
+-n test_idtlb_inval2: 
+test FAILED
+-n test_idtlb_inval3: 
+test FAILED
+-n test_idtlb_inval4: 
+test FAILED
+-n test_dtlb_ptprinval: 
+-n test_itlb_ptprinval: 
+-n test_idtlb_ptprinval: 
+test FAILED
+-n test_sync: 
+-n test_sc_update_cache: 
+-n test_pte_llsc: 
+test FAILED
+-n test_interrupt: 
+-n test_interrupt_epc_modify: 
+-n test_xicu_timer: 
+-n test_interrupt_delayslot: 
+test FAILED
+-n test_interrupt_mask: 
+-n test_interrupt_external_mask: 
+-n test_excep_cop: 
+-n test_excep_cop_delayslot: 
+-n test_excep_cop1: 
+-n test_syscall: 
+-n test_syscall_delayslot: 
+-n test_breakpoint: 
+-n test_breakpoint_delayslot: 
+-n test_ri: 
+-n test_ri_delayslot: 
+-n test_ao: 
+-n test_ao_delayslot: 
+-n test_trap: 
+-n test_trap_delayslot: 
+-n test_fpe: 
+-n test_fpe_delayslot: 
+test FAILED
+-n test_dcache_inval_pa: 
+test FAILED
+-n test_icache_inval_pa: 
+test FAILED
+-n test_pte2i_ref: 
+-n test_pte2lw_ref: 
+-n test_pte2ll_ref: 
+-n test_pte2sw_dirty: 
+-n test_pte2sc_dirty: 
