Changeset 233 for trunk/modules

Timestamp:

May 25, 2012, 3:50:13 PM (13 years ago)

Author:

alain

Message:

Fixing a bug in the DCACHE_IDLE state: The coherence request were not
taken in case of blocking write caused by write buffer full.
This is a dead-lock case.

File:

• trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (modified) (4 diffs)

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

@@ -1986 +1986 @@
                         //  1  / 1  / write(A2) / read(A1)  / read request delayed
     { 
+        bool tlb_inval_required = false;
+        bool write_pipe_frozen  = false;
+
         ////////////////////////////////////////////////////////////////////////////////
         // Handling P2 pipe-line stage 
@@ -1992 +1995 @@
         // If the modified cache line has copies in TLBs, we launch a TLB invalidate
         // operation, going to DCACHE_INVAL_TLB_SCAN state.
-
-        bool tlb_inval_required = false;
 
         if ( r_dcache_p1_valid.read() )         // P2 stage activated
@@ -2045 +2046 @@
         // We must write into wbuf and test the hit in dcache.
         // If the write request is non cacheable, and there is a pending
-        // non cacheable write, or if the write buffer is full, we break,
-        // because the P0 and P1 pipe-line stages are frozen until the write
-        // request registration is possible, but he P2 stage is not frozen.
+        // non cacheable write, or if the write buffer is full, the P0 and P1 stages 
+        // are frozen until the write request registration is possible, 
+        // while the P2 stage is not frozen.
         // The r_dcache_p1_valid bit must be computed at all cycles, and 
-        // the P2 stage must be activated if there is local copy in dcache. 
+        // the P2 stage must be activated if there is a local copy in dcache. 
 
         if ( r_dcache_p0_valid.read() )  // P1 stage activated
         {
-            // write not cacheable, and previous non cacheable write registered
+            // frozen if write not cacheable, and previous non cacheable write registered
             if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() ) 
             {
                 r_dcache_p1_valid = false;
-                break;
-            }
-
-            // try a registration into write buffer
-            bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
-                                     r_dcache_p0_be.read(),
-                                     r_dcache_p0_wdata.read(),
-                                     r_dcache_p0_cacheable.read() );
-#ifdef INSTRUMENTATION
+                write_pipe_frozen = true;
+            }
+            else                // try a registration into write buffer
+            {
+
+                bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
+                                         r_dcache_p0_be.read(),
+                                         r_dcache_p0_wdata.read(),
+                                         r_dcache_p0_cacheable.read() );
+#ifdef INSTRUMENTATION 
 m_cpt_wbuf_write++;
 #endif
-            // write buffer full
-            if ( not wok ) 
-            {
-                r_dcache_p1_valid = false;
-                break; 
-            }
-            // update the write_buffer state extension
-            r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
-
-            // read directory to check local copy
-            size_t  cache_way;
-            size_t  cache_set;
-            size_t  cache_word;
-            bool    local_copy;
-            if ( r_mmu_mode.read() & DATA_CACHE_MASK)   // cache activated
-            {
-                local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
-                                           &cache_way,
-                                           &cache_set,
-                                           &cache_word );
+                if ( not wok ) // frozen if write buffer full
+                {
+                    r_dcache_p1_valid = false;
+                    write_pipe_frozen = true;
+                }
+                else          // update the write_buffer state extension
+                {
+                    r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
+
+                    // read directory to check local copy
+                    size_t  cache_way;
+                    size_t  cache_set;
+                    size_t  cache_word;
+                    bool    local_copy;
+                    if ( r_mmu_mode.read() & DATA_CACHE_MASK)   // cache activated
+                    {
+                        local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
+                                                   &cache_way,
+                                                   &cache_set,
+                                                   &cache_word );
 #ifdef INSTRUMENTATION
 m_cpt_dcache_dir_read++; 
 #endif
-            }
-            else
-            {
-                local_copy = false;
-            }
-
-            // store values for P2 pipe stage
-            if ( local_copy )
-            {
-                r_dcache_p1_valid       = true;
-                r_dcache_p1_wdata       = r_dcache_p0_wdata.read();
-                r_dcache_p1_be          = r_dcache_p0_be.read();
-                r_dcache_p1_paddr       = r_dcache_p0_paddr.read();
-                r_dcache_p1_cache_way   = cache_way;
-                r_dcache_p1_cache_set   = cache_set;
-                r_dcache_p1_cache_word  = cache_word;
-            }
-            else
-            {
-                r_dcache_p1_valid       = false;
-            }
-        }
-        else                            // P1 stage not activated 
+                    }
+                    else
+                    {
+                        local_copy = false;
+                    }
+
+                    // store values for P2 pipe stage
+                    if ( local_copy )
+                    {
+                        r_dcache_p1_valid       = true;
+                        r_dcache_p1_wdata       = r_dcache_p0_wdata.read();
+                        r_dcache_p1_be          = r_dcache_p0_be.read();
+                        r_dcache_p1_paddr       = r_dcache_p0_paddr.read();
+                        r_dcache_p1_cache_way   = cache_way;
+                        r_dcache_p1_cache_set   = cache_set;
+                        r_dcache_p1_cache_word  = cache_word;
+                    }
+                    else
+                    {
+                        r_dcache_p1_valid       = false;
+                    }
+                }
+            }
+        }
+        else  // P1 stage not activated 
         {
             r_dcache_p1_valid = false; 
@@ -2168 +2172 @@
 
         // processor request
-        else if ( m_dreq.valid )
+        else if ( m_dreq.valid and not write_pipe_frozen )
         {
             // dcache access using speculative PPN only if pipe-line empty
-            paddr_t     cache_paddr;
-            size_t      cache_way;
-            size_t      cache_set;
-            size_t      cache_word;
+            paddr_t             cache_paddr;
+            size_t              cache_way;
+            size_t              cache_set;
+            size_t              cache_word;
             uint32_t    cache_rdata;
-            bool        cache_hit;
+            bool            cache_hit;
 
             if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and      // cache activated