Changeset 238

Timestamp:

Jul 16, 2012, 5:52:01 PM (12 years ago)

Author:

fraga

Message:

Changing ICACHE TLB MISS requests priority in DCACHE_IDLE. Now, the data is treated first. This solves the following livelock problem: A processor's simultaneous request of instruction and data that generates miss on PTE1 and PTE2 in the instruction address, PTE1 and PTE2 in the data address and on the data itself. In the case where all these data occupy the same set and the DCACHE contains 4 ways, the instruction page table entry may be overwritten producing a new TLB MISS request to the DCACHE. The cycle then restarts.

File:

• trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (modified) (2 diffs)

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

@@ -2165 +2165 @@
         }        
 
-        // itlb miss request 
-        else if ( r_icache_tlb_miss_req.read() )
-        {
-            r_dcache_tlb_ins    = true;
-            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
-            r_dcache_fsm        = DCACHE_TLB_MISS;
-            r_dcache_p0_valid = false;
-        }
-
         // processor request
         else if ( m_dreq.valid and not write_pipe_frozen )
@@ -2716 +2707 @@
             }  // end if read/write/ll/sc request       
         } // end dreq.valid
+        
+        // itlb miss request 
+        else if ( r_icache_tlb_miss_req.read() )
+        {
+            r_dcache_tlb_ins    = true;
+            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
+            r_dcache_fsm        = DCACHE_TLB_MISS;
+            r_dcache_p0_valid = false;
+        }
         else
         {