- Timestamp:
- Aug 8, 2012, 12:03:25 PM (12 years ago)
- Location:
- trunk
- Files:
-
- 6 edited
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modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h (modified) (2 diffs)
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modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (modified) (3 diffs)
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modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (modified) (15 diffs)
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platforms/tsarv4_generic_mmu/top.cpp (modified) (7 diffs)
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platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (modified) (21 diffs)
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platforms/tsarv4_mono_mmu/top.cpp (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h
r217 r247 254 254 const size_t m_dcache_words; 255 255 256 const size_t m_x_width; 257 const size_t m_y_width; 258 259 const size_t m_memory_cache_local_id; 260 256 261 const size_t m_proc_id; 257 262 … … 625 630 size_t wbuf_nlines, 626 631 size_t wbuf_nwords, 632 size_t x_width, 633 size_t y_width, 634 uint32_t memory_cache_local_id, 627 635 uint32_t max_frozen_cycles, 628 636 uint32_t debug_start_cycle, -
trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
r239 r247 166 166 size_t wbuf_nlines, 167 167 size_t wbuf_nwords, 168 uint32_t max_frozen_cycles, 169 uint32_t debug_start_cycle, 168 size_t x_width, 169 size_t y_width, 170 uint32_t memory_cache_local_id, 171 uint32_t max_frozen_cycles, 172 uint32_t debug_start_cycle, 170 173 bool debug_ok) 171 174 : soclib::caba::BaseModule(name), … … 197 200 m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)), 198 201 m_dcache_words(dcache_words), 202 203 m_x_width(x_width), 204 m_y_width(y_width), 205 206 m_memory_cache_local_id(memory_cache_local_id), 199 207 200 208 m_proc_id(proc_id), … … 4812 4820 // it depends on the CLEANUP FSM state 4813 4821 4822 paddr_t cleanup_nline; 4814 4823 paddr_t address; 4815 4824 4816 4825 if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO ) 4817 address = r_dcache_cleanup_line.read()*m_dcache_words*4; 4826 { 4827 cleanup_nline = r_dcache_cleanup_line.read(); 4828 address = (m_x_width + m_y_width) ? (cleanup_nline * m_dcache_words * 4 ) >> 4829 (vci_param::N - m_x_width - m_y_width ) : 0; 4830 } 4818 4831 else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO ) 4819 address = r_icache_cleanup_line.read()*m_icache_words*4; 4832 { 4833 cleanup_nline = r_icache_cleanup_line.read(); 4834 address = (m_x_width + m_y_width) ? (cleanup_nline * m_icache_words * 4 ) >> 4835 (vci_param::N - m_x_width - m_y_width ) : 0; 4836 } 4820 4837 else 4821 address = 0; 4838 { 4839 cleanup_nline = 0; 4840 address = 0; 4841 } 4842 4843 address <<= vci_param::S - m_x_width - m_y_width; 4844 address |= m_memory_cache_local_id; 4845 address <<= vci_param::N - vci_param::S; 4822 4846 4823 4847 p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or 4824 4848 (r_cleanup_fsm.read() == CLEANUP_INS_GO) ); 4825 4849 p_vci_ini_c.address = address; 4826 p_vci_ini_c.wdata = 0;4827 p_vci_ini_c.be = 0xF;4850 p_vci_ini_c.wdata = (uint32_t) cleanup_nline; 4851 p_vci_ini_c.be = (cleanup_nline >> 32) & 0x3; 4828 4852 p_vci_ini_c.plen = 4; 4829 4853 p_vci_ini_c.cmd = vci_param::CMD_WRITE; -
trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r246 r247 273 273 m_seglist(mtp.getSegmentList(vci_tgt_index)), 274 274 m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)), 275 m_coherence_table( mtc.getCoherenceTable<vci_addr_t>() ),276 275 m_transaction_tab_lines(transaction_tab_lines), 277 276 m_transaction_tab( transaction_tab_lines, nwords ), … … 354 353 r_alloc_dir_fsm("r_alloc_dir_fsm"), 355 354 r_alloc_trt_fsm("r_alloc_trt_fsm"), 356 r_alloc_upt_fsm("r_alloc_upt_fsm") 357 355 r_alloc_upt_fsm("r_alloc_upt_fsm"), 356 r_alloc_heap_fsm("r_alloc_heap_fsm") 358 357 { 359 358 assert(IS_POW_OF_2(nsets)); … … 552 551 } 553 552 delete [] m_cache_data; 554 delete [] m_coherence_table;555 553 556 554 delete [] r_ixr_rsp_to_xram_rsp_rok; … … 587 585 r_cleanup_fsm = CLEANUP_IDLE; 588 586 r_alloc_dir_fsm = ALLOC_DIR_READ; 587 r_alloc_heap_fsm = ALLOC_HEAP_READ; 589 588 r_alloc_trt_fsm = ALLOC_TRT_READ; 590 589 r_alloc_upt_fsm = ALLOC_UPT_WRITE; … … 3298 3297 ((p_vci_tgt_cleanup.address.read() & 0x3) == 0) && reached) 3299 3298 { 3300 addr_t line = (addr_t)(m_nline[(vci_addr_t)(p_vci_tgt_cleanup.address.read())]); 3299 addr_t line =(((addr_t) p_vci_tgt_cleanup.be.read() << (vci_param::B*8))) | 3300 (((addr_t) p_vci_tgt_cleanup.wdata.read())); 3301 3301 3302 3302 r_cleanup_nline = line; … … 5253 5253 switch ( r_alloc_dir_fsm.read() ) 5254 5254 { 5255 5256 5255 //////////////////// 5257 5256 case ALLOC_DIR_READ: … … 5881 5880 p_vci_ini.cfixed = false; 5882 5881 5882 vci_addr_t vci_ini_address = 0; 5883 5883 switch ( r_init_cmd_fsm.read() ) { 5884 5884 … … 5897 5897 case INIT_CMD_INVAL_NLINE: 5898 5898 { 5899 vci_ini_address = (vci_addr_t) 5900 m_xram_rsp_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); 5901 5899 5902 p_vci_ini.cmdval = m_xram_rsp_to_init_cmd_inst_fifo.rok(); 5900 5903 if(m_xram_rsp_to_init_cmd_inst_fifo.rok()){ 5901 5904 if(m_xram_rsp_to_init_cmd_inst_fifo.read()) { 5902 p_vci_ini.address = (addr_t)(m_coherence_table[m_xram_rsp_to_init_cmd_srcid_fifo.read()]+4);5905 p_vci_ini.address = (addr_t) (vci_ini_address+4); 5903 5906 } else { 5904 p_vci_ini.address = (addr_t)(m_coherence_table[m_xram_rsp_to_init_cmd_srcid_fifo.read()]);5907 p_vci_ini.address = (addr_t) (vci_ini_address); 5905 5908 } 5906 5909 } else p_vci_ini.address = 0; // prevent segmentation faults by reading an empty fifo … … 5935 5938 break; 5936 5939 case INIT_CMD_UPDT_NLINE: 5940 vci_ini_address = (vci_addr_t) 5941 m_write_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); 5942 5937 5943 p_vci_ini.cmdval = m_write_to_init_cmd_inst_fifo.rok(); 5938 5944 if(m_write_to_init_cmd_inst_fifo.rok()){ 5939 5945 if(m_write_to_init_cmd_inst_fifo.read()) { 5940 p_vci_ini.address = (addr_t)( m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()]+ 12);5946 p_vci_ini.address = (addr_t)(vci_ini_address + 12); 5941 5947 } else { 5942 p_vci_ini.address = (addr_t)( m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()]+ 8);5948 p_vci_ini.address = (addr_t)(vci_ini_address + 8); 5943 5949 } 5944 5950 } else { … … 5953 5959 break; 5954 5960 case INIT_CMD_UPDT_INDEX: 5961 vci_ini_address = (vci_addr_t) 5962 m_write_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); 5963 5955 5964 p_vci_ini.cmdval = true; 5956 5965 if(m_write_to_init_cmd_inst_fifo.read()) { 5957 p_vci_ini.address = (addr_t)( m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()]+ 12);5966 p_vci_ini.address = (addr_t)(vci_ini_address + 12); 5958 5967 } else { 5959 p_vci_ini.address = (addr_t)( m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()]+ 8);5968 p_vci_ini.address = (addr_t)(vci_ini_address + 8); 5960 5969 } 5961 5970 p_vci_ini.wdata = r_write_to_init_cmd_index.read(); … … 5967 5976 break; 5968 5977 case INIT_CMD_UPDT_DATA: 5978 vci_ini_address = (vci_addr_t) 5979 m_write_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); 5980 5969 5981 p_vci_ini.cmdval = true; 5970 5982 if(m_write_to_init_cmd_inst_fifo.read()) { 5971 p_vci_ini.address = (addr_t)( m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()]+ 12);5983 p_vci_ini.address = (addr_t)(vci_ini_address + 12); 5972 5984 } else { 5973 p_vci_ini.address = (addr_t)( m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()]+ 8);5985 p_vci_ini.address = (addr_t)(vci_ini_address + 8); 5974 5986 } 5975 5987 p_vci_ini.wdata = r_write_to_init_cmd_data[r_init_cmd_cpt.read() + … … 5994 6006 break; 5995 6007 case INIT_CMD_SC_UPDT_NLINE: 6008 vci_ini_address = (vci_addr_t) 6009 m_sc_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); 6010 5996 6011 p_vci_ini.cmdval = m_sc_to_init_cmd_inst_fifo.rok(); 5997 6012 if(m_sc_to_init_cmd_inst_fifo.rok()){ 5998 6013 if( m_sc_to_init_cmd_inst_fifo.read() ) { 5999 p_vci_ini.address = (addr_t)( m_coherence_table[m_sc_to_init_cmd_srcid_fifo.read()]+ 12);6014 p_vci_ini.address = (addr_t)(vci_ini_address + 12); 6000 6015 } else { 6001 p_vci_ini.address = (addr_t)( m_coherence_table[m_sc_to_init_cmd_srcid_fifo.read()]+ 8);6016 p_vci_ini.address = (addr_t)(vci_ini_address + 8); 6002 6017 } 6003 6018 } else { … … 6016 6031 break; 6017 6032 case INIT_CMD_SC_UPDT_INDEX: 6033 vci_ini_address = (vci_addr_t) 6034 m_sc_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); 6035 6018 6036 p_vci_ini.cmdval = true; 6019 6037 if( m_sc_to_init_cmd_inst_fifo.read() ) { 6020 p_vci_ini.address = (addr_t)( m_coherence_table[m_sc_to_init_cmd_srcid_fifo.read()]+ 12);6038 p_vci_ini.address = (addr_t)(vci_ini_address + 12); 6021 6039 } else { 6022 p_vci_ini.address = (addr_t)( m_coherence_table[m_sc_to_init_cmd_srcid_fifo.read()]+ 8);6040 p_vci_ini.address = (addr_t)(vci_ini_address + 8); 6023 6041 } 6024 6042 p_vci_ini.wdata = r_sc_to_init_cmd_index.read(); … … 6034 6052 break; 6035 6053 case INIT_CMD_SC_UPDT_DATA: 6054 vci_ini_address = (vci_addr_t) 6055 m_sc_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); 6056 6036 6057 p_vci_ini.cmdval = true; 6037 6058 if( m_sc_to_init_cmd_inst_fifo.read() ) { 6038 p_vci_ini.address = (addr_t)( m_coherence_table[m_sc_to_init_cmd_srcid_fifo.read()]+ 12);6059 p_vci_ini.address = (addr_t)(vci_ini_address + 12); 6039 6060 } else { 6040 p_vci_ini.address = (addr_t)( m_coherence_table[m_sc_to_init_cmd_srcid_fifo.read()]+ 8);6061 p_vci_ini.address = (addr_t)(vci_ini_address + 8); 6041 6062 } 6042 6063 p_vci_ini.wdata = r_sc_to_init_cmd_wdata.read(); … … 6053 6074 break; 6054 6075 case INIT_CMD_SC_UPDT_DATA_HIGH: 6076 vci_ini_address = (vci_addr_t) 6077 m_sc_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); 6078 6055 6079 p_vci_ini.cmdval = true; 6056 6080 if( m_sc_to_init_cmd_inst_fifo.read() ) { 6057 p_vci_ini.address = (addr_t)( m_coherence_table[m_sc_to_init_cmd_srcid_fifo.read()]+ 12);6081 p_vci_ini.address = (addr_t)(vci_ini_address + 12); 6058 6082 } else { 6059 p_vci_ini.address = (addr_t)( m_coherence_table[m_sc_to_init_cmd_srcid_fifo.read()]+ 8);6083 p_vci_ini.address = (addr_t)(vci_ini_address + 8); 6060 6084 } 6061 6085 p_vci_ini.wdata = r_sc_to_init_cmd_wdata_high.read(); -
trunk/platforms/tsarv4_generic_mmu/top.cpp
r189 r247 58 58 /////////////////////////////////////////////////// 59 59 60 #define USE_ALMOS 160 #define USE_ALMOS 0 61 61 #define almos_bootloader_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/bootloader/bin/bootloader-soclib-mipsel.bin" 62 62 #define almos_kernel_pathname "/Users/alain/soc/tsar-svn-june-2010/softs/almos/kernel/bin/kernel-soclib-mipsel.bin@0xbfc10000:D" … … 100 100 #define MESH_YMAX 2 101 101 102 #define NPROCS 1102 #define NPROCS 4 103 103 #define XRAM_LATENCY 0 104 104 … … 112 112 #define L1_DSETS 64 113 113 114 #define FBUF_X_SIZE 128115 #define FBUF_Y_SIZE 128114 #define FBUF_X_SIZE 512 115 #define FBUF_Y_SIZE 512 116 116 117 117 #define BDEV_SECTOR_SIZE 128 … … 120 120 #define BOOT_SOFT_NAME "../../softs/soft_transpose_giet/bin.soft" 121 121 122 #define MAX_FROZEN_CYCLES 1000 122 #define MAX_FROZEN_CYCLES 100000 123 123 124 124 ///////////////////////////////////////////////////////// … … 394 394 // - tgtid_c_memc = srcid_c_memc = nprocs 395 395 MappingTable maptabc(address_width, 396 IntTab(x_width + y_width, 16- x_width - y_width),396 IntTab(x_width + y_width, srcid_width - x_width - y_width), 397 397 IntTab(x_width + y_width, srcid_width - x_width - y_width), 398 398 0x00FF0000); … … 407 407 std::ostringstream sh; 408 408 sh << "c_seg_memc_" << x << "_" << y; 409 maptabc.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y), nprocs), false)); 410 411 // cleanup requests regarding the BROM segment are also be routed to the memory cache 412 if ( cluster(x,y) == cluster_io_index ) 413 { 414 maptabc.add(Segment("c_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false)); 415 } 409 maptabc.add( 410 Segment( 411 sh.str() 412 , (nprocs << (address_width - srcid_width)) + offset 413 , 0x10 414 , IntTab(cluster(x,y), nprocs) 415 , false 416 ) 417 ); 416 418 417 419 // update & invalidate requests must be routed to the proper processor … … 420 422 std::ostringstream sp; 421 423 sp << "c_seg_proc_" << x << "_" << y << "_" << p; 422 maptabc.add(Segment(sp.str(), PROC_BASE+offset+(p*0x10000), PROC_SIZE, 423 IntTab(cluster(x,y), p), false, true, IntTab(cluster(x,y), p))); 424 maptabc.add( 425 Segment( 426 sp.str() 427 , (p << (address_width - srcid_width)) + offset 428 , 0x10 429 , IntTab(cluster(x,y), p) 430 , false 431 ) 432 ); 424 433 } 425 434 } -
trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
r234 r247 14 14 size_t y_id, 15 15 size_t cluster_id, 16 const 17 const 18 const 16 const soclib::common::MappingTable &mtd, 17 const soclib::common::MappingTable &mtc, 18 const soclib::common::MappingTable &mtx, 19 19 size_t x_width, 20 20 size_t y_width, 21 size_t 22 size_t 23 size_t 24 size_t 25 size_t 26 size_t 27 size_t 28 size_t 29 size_t 30 size_t 31 size_t 32 size_t 33 size_t 34 size_t 21 size_t tgtid_memc, 22 size_t tgtid_xicu, 23 size_t tgtid_fbuf, 24 size_t tgtid_mtty, 25 size_t tgtid_brom, 26 size_t tgtid_bdev, 27 size_t tgtid_mdma, 28 size_t memc_ways, 29 size_t memc_sets, 30 size_t l1_i_ways, 31 size_t l1_i_sets, 32 size_t l1_d_ways, 33 size_t l1_d_sets, 34 size_t xram_latency, 35 35 bool io, 36 size_t 37 size_t 38 char* 39 size_t 36 size_t xfb, 37 size_t yfb, 38 char* disk_name, 39 size_t block_size, 40 40 const Loader &loader, 41 uint32_t 42 uint32_t 41 uint32_t frozen_cycles, 42 uint32_t debug_start_cycle, 43 43 bool debug_ok) 44 44 : soclib::caba::BaseModule(insname), … … 55 55 signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), 56 56 57 58 57 signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), 58 signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), 59 59 60 60 signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), … … 86 86 87 87 // on coherence network : local srcid[proc] in [0...nprocs-1] 88 88 // on coherence network : local srcid[memc] = nprocs 89 89 90 90 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; … … 97 97 sproc.str().c_str(), 98 98 cluster_id*nprocs + p, 99 mtd, // Mapping Table Direct 100 mtc, // Mapping Table Coherence 101 IntTab(cluster_id,p), // SRCID_D 102 IntTab(cluster_id,p), // SRCID_C 103 IntTab(cluster_id,p), // TGTID_C 104 8, // ITLB ways 105 8, // ITLB sets 106 8, // DTLB ways 107 8, // DTLB sets 108 l1_i_ways,l1_i_sets,16, // ICACHE size 109 l1_d_ways,l1_d_sets,16, // DCACHE size 110 4, // WBUF width 111 4, // WBUF depth 112 frozen_cycles, // max frozen cycles 99 mtd, // Mapping Table Direct 100 mtc, // Mapping Table Coherence 101 IntTab(cluster_id,p), // SRCID_D 102 IntTab(cluster_id,p), // SRCID_C 103 IntTab(cluster_id,p), // TGTID_C 104 8, // ITLB ways 105 8, // ITLB sets 106 8, // DTLB ways 107 8, // DTLB sets 108 l1_i_ways,l1_i_sets,16, // ICACHE size 109 l1_d_ways,l1_d_sets,16, // DCACHE size 110 4, // WBUF width 111 4, // WBUF depth 112 x_width, // X Width 113 y_width, // Y Width 114 nprocs, // Memory Cache Local Id (coherence) 115 frozen_cycles, // max frozen cycles 113 116 debug_start_cycle, 114 117 debug_ok); … … 122 125 smemc.str().c_str(), 123 126 mtd, mtc, mtx, 124 IntTab(cluster_id), 125 IntTab(cluster_id, nprocs), 126 IntTab(cluster_id, tgtid_memc), 127 IntTab(cluster_id, nprocs), 128 memc_ways, memc_sets, 16, 129 4096, 130 8, 131 8, 127 IntTab(cluster_id), // SRCID_X 128 IntTab(cluster_id, nprocs), // SRCID_C 129 IntTab(cluster_id, tgtid_memc), // TGTID_D 130 IntTab(cluster_id, nprocs), // TGTID_C 131 memc_ways, memc_sets, 16, // CACHE SIZE 132 4096, // HEAP SIZE 133 8, // TRANSACTION TABLE DEPTH 134 8, // UPDATE TABLE DEPTH 132 135 debug_start_cycle, 133 136 debug_ok); … … 147 150 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 148 151 149 size_t nhwi = 4; 150 if( io == true ) nhwi = 9; 152 size_t nhwi = 4; // always 4 (or 9) ports, even if 153 if( io == true ) nhwi = 9; // there if less than 4 processors 151 154 std::ostringstream sicu; 152 155 sicu << "xicu_" << x_id << "_" << y_id; 153 156 xicu = new VciXicu<vci_param>( 154 157 sicu.str().c_str(), 155 mtd, 156 IntTab(cluster_id, tgtid_xicu), 157 0, 158 nhwi, 159 0, 160 nprocs); 158 mtd, // mapping table 159 IntTab(cluster_id, tgtid_xicu), // TGTID_D 160 0, // number of timer IRQs 161 nhwi, // number of hard IRQs 162 0, // number of soft IRQs 163 nprocs); // number of output IRQs 161 164 162 165 std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; … … 168 171 sdma.str().c_str(), 169 172 mtd, 170 IntTab(cluster_id, nprocs), 171 IntTab(cluster_id, tgtid_mdma), 172 64, 173 nprocs); 173 IntTab(cluster_id, nprocs), // SRCID 174 IntTab(cluster_id, tgtid_mdma), // TGTID 175 64, // burst size 176 nprocs); // number of IRQs 174 177 175 178 std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; … … 182 185 nb_direct_initiators = nprocs + 2; 183 186 nb_direct_targets = 7; 184 187 } 185 188 std::ostringstream sd; 186 189 sd << "xbard_" << x_id << "_" << y_id; … … 188 191 sd.str().c_str(), 189 192 mtd, 190 IntTab(cluster_id), 191 IntTab(cluster_id), 192 nb_direct_initiators, 193 nb_direct_targets); 193 IntTab(cluster_id), // cluster initiator index 194 IntTab(cluster_id), // cluster target index 195 nb_direct_initiators, // number of initiators 196 nb_direct_targets); // number of targets 194 197 195 198 std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; … … 201 204 sc.str().c_str(), 202 205 mtc, 203 IntTab(cluster_id), 204 IntTab(cluster_id), 205 nprocs + 1, 206 nprocs + 1); 206 IntTab(cluster_id), // cluster initiator index 207 IntTab(cluster_id), // cluster target index 208 nprocs + 1, // number of initiators 209 nprocs + 1); // number of targets 207 210 208 211 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; … … 213 216 iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 214 217 wid.str().c_str(), 215 4, 216 4); 218 4, // cmd fifo depth 219 4); // rsp fifo depth 217 220 218 221 // direct target wrapper … … 221 224 tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 222 225 wtd.str().c_str(), 223 4, 224 4); 226 4, // cmd fifo depth 227 4); // rsp fifo depth 225 228 226 229 // coherence initiator wrapper … … 229 232 iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 230 233 wic.str().c_str(), 231 4, 232 4); 234 4, // cmd fifo depth 235 4); // rsp fifo depth 233 236 234 237 // coherence target wrapper … … 237 240 tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 238 241 wtc.str().c_str(), 239 4, 240 4); 242 4, // cmd fifo depth 243 4); // rsp fifo depth 241 244 242 245 std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; … … 264 267 // IO cluster components 265 268 if ( io == true ) 266 269 { 267 270 brom = new VciSimpleRam<vci_param>( 268 271 "brom", … … 275 278 IntTab(cluster_id, tgtid_fbuf), 276 279 mtd, 277 280 xfb, yfb); 278 281 279 282 bdev = new VciBlockDeviceTsarV4<vci_param>( … … 290 293 mtd, 291 294 "tty0", "tty1", "tty2", "tty3", NULL); 292 295 } 293 296 294 297 std::cout << " - all components constructed" << std::endl; … … 299 302 300 303 // CMDROUTER and RSPROUTER 301 cmdrouter->p_clk 302 cmdrouter->p_resetn 303 rsprouter->p_clk 304 rsprouter->p_resetn 304 cmdrouter->p_clk (this->p_clk); 305 cmdrouter->p_resetn (this->p_resetn); 306 rsprouter->p_clk (this->p_clk); 307 rsprouter->p_resetn (this->p_resetn); 305 308 for(int x = 0; x < 2; x++) 306 309 { … … 314 317 } 315 318 316 cmdrouter->p_out[0][4] 317 cmdrouter->p_out[1][4] 318 cmdrouter->p_in[0][4] 319 cmdrouter->p_in[1][4] 320 321 rsprouter->p_out[0][4] 322 rsprouter->p_out[1][4] 323 rsprouter->p_in[0][4] 324 rsprouter->p_in[1][4] 319 cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); 320 cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); 321 cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); 322 cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); 323 324 rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); 325 rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); 326 rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); 327 rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); 325 328 326 329 // VCI/DSPIN WRAPPERS 327 iniwrapperd->p_clk 328 iniwrapperd->p_resetn 329 iniwrapperd->p_vci(signal_vci_l2g_d);330 iniwrapperd->p_dspin_out(signal_dspin_cmd_l2g_d);331 iniwrapperd->p_dspin_in(signal_dspin_rsp_g2l_d);332 333 tgtwrapperd->p_clk 334 tgtwrapperd->p_resetn 335 tgtwrapperd->p_vci(signal_vci_g2l_d);336 tgtwrapperd->p_dspin_out(signal_dspin_rsp_l2g_d);337 tgtwrapperd->p_dspin_in(signal_dspin_cmd_g2l_d);338 339 iniwrapperc->p_clk 340 iniwrapperc->p_resetn 341 iniwrapperc->p_vci(signal_vci_l2g_c);342 iniwrapperc->p_dspin_out(signal_dspin_cmd_l2g_c);343 iniwrapperc->p_dspin_in(signal_dspin_rsp_g2l_c);344 345 tgtwrapperc->p_clk 346 tgtwrapperc->p_resetn 347 tgtwrapperc->p_vci(signal_vci_g2l_c);348 tgtwrapperc->p_dspin_out(signal_dspin_rsp_l2g_c);349 tgtwrapperc->p_dspin_in(signal_dspin_cmd_g2l_c);330 iniwrapperd->p_clk (this->p_clk); 331 iniwrapperd->p_resetn (this->p_resetn); 332 iniwrapperd->p_vci (signal_vci_l2g_d); 333 iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); 334 iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); 335 336 tgtwrapperd->p_clk (this->p_clk); 337 tgtwrapperd->p_resetn (this->p_resetn); 338 tgtwrapperd->p_vci (signal_vci_g2l_d); 339 tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); 340 tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); 341 342 iniwrapperc->p_clk (this->p_clk); 343 iniwrapperc->p_resetn (this->p_resetn); 344 iniwrapperc->p_vci (signal_vci_l2g_c); 345 iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); 346 iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); 347 348 tgtwrapperc->p_clk (this->p_clk); 349 tgtwrapperc->p_resetn (this->p_resetn); 350 tgtwrapperc->p_vci (signal_vci_g2l_c); 351 tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); 352 tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); 350 353 351 354 // CROSSBAR direct 352 xbard->p_clk 353 xbard->p_resetn 354 xbard->p_initiator_to_up 355 xbard->p_target_to_up 355 xbard->p_clk (this->p_clk); 356 xbard->p_resetn (this->p_resetn); 357 xbard->p_initiator_to_up (signal_vci_l2g_d); 358 xbard->p_target_to_up (signal_vci_g2l_d); 356 359 357 xbard->p_to_target[tgtid_memc] 358 xbard->p_to_target[tgtid_xicu] 359 xbard->p_to_target[tgtid_mdma] 360 xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); 361 xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); 362 xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); 360 363 361 xbard->p_to_initiator[nprocs] 364 xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); 362 365 363 366 for ( size_t p=0 ; p<nprocs ; p++) 364 367 { 365 xbard->p_to_initiator[p] 366 } 367 368 369 370 xbard->p_to_target[tgtid_mtty] 371 xbard->p_to_target[tgtid_brom] 372 xbard->p_to_target[tgtid_bdev] 373 xbard->p_to_target[tgtid_fbuf] 368 xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); 369 } 370 371 if ( io == true ) 372 { 373 xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); 374 xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); 375 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 376 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 374 377 375 xbard->p_to_initiator[nprocs+1] 376 378 xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); 379 } 377 380 378 381 // CROSSBAR coherence 379 xbarc->p_clk 380 xbarc->p_resetn 381 xbarc->p_initiator_to_up 382 xbarc->p_target_to_up 383 xbarc->p_to_initiator[nprocs] 384 xbarc->p_to_target[nprocs] 382 xbarc->p_clk (this->p_clk); 383 xbarc->p_resetn (this->p_resetn); 384 xbarc->p_initiator_to_up (signal_vci_l2g_c); 385 xbarc->p_target_to_up (signal_vci_g2l_c); 386 xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); 387 xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); 385 388 for ( size_t p=0 ; p<nprocs ; p++) 386 389 { 387 xbarc->p_to_target[p] 388 xbarc->p_to_initiator[p] 390 xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); 391 xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); 389 392 } 390 393 … … 392 395 for ( size_t p=0 ; p<nprocs ; p++) 393 396 { 394 proc[p]->p_clk 395 proc[p]->p_resetn 396 proc[p]->p_vci_ini_d 397 proc[p]->p_vci_ini_c 398 proc[p]->p_vci_tgt_c 399 proc[p]->p_irq[0] 397 proc[p]->p_clk (this->p_clk); 398 proc[p]->p_resetn (this->p_resetn); 399 proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); 400 proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); 401 proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); 402 proc[p]->p_irq[0] (signal_proc_it[p]); 400 403 for ( size_t j = 1 ; j < 6 ; j++ ) 401 404 { 402 proc[p]->p_irq[j] 405 proc[p]->p_irq[j] (signal_false); 403 406 } 404 407 } 405 408 406 409 // XICU 407 xicu->p_clk 408 xicu->p_resetn 409 xicu->p_vci 410 xicu->p_clk (this->p_clk); 411 xicu->p_resetn (this->p_resetn); 412 xicu->p_vci (signal_vci_tgt_d_xicu); 410 413 for ( size_t p=0 ; p<nprocs ; p++) 411 414 { 412 xicu->p_irq[p] 415 xicu->p_irq[p] (signal_proc_it[p]); 413 416 } 414 417 for ( size_t p=0 ; p<nprocs ; p++) 415 418 { 416 xicu->p_hwi[p] 419 xicu->p_hwi[p] (signal_irq_mdma[p]); 417 420 } 418 421 for ( size_t x=nprocs ; x<4 ; x++) 419 422 { 420 xicu->p_hwi[x] 423 xicu->p_hwi[x] (signal_false); 421 424 } 422 425 if ( io == true ) 423 424 xicu->p_hwi[4] 425 xicu->p_hwi[5] 426 xicu->p_hwi[6] 427 xicu->p_hwi[7] 428 xicu->p_hwi[8] 429 426 { 427 xicu->p_hwi[4] (signal_irq_tty0); 428 xicu->p_hwi[5] (signal_irq_tty1); 429 xicu->p_hwi[6] (signal_irq_tty2); 430 xicu->p_hwi[7] (signal_irq_tty3); 431 xicu->p_hwi[8] (signal_irq_bdev); 432 } 430 433 431 434 // MEMC 432 memc->p_clk 433 memc->p_resetn 434 memc->p_vci_ixr 435 memc->p_vci_tgt 436 memc->p_vci_ini 437 memc->p_vci_tgt_cleanup 435 memc->p_clk (this->p_clk); 436 memc->p_resetn (this->p_resetn); 437 memc->p_vci_ixr (signal_vci_xram); 438 memc->p_vci_tgt (signal_vci_tgt_d_memc); 439 memc->p_vci_ini (signal_vci_ini_c_memc); 440 memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); 438 441 439 442 // XRAM 440 xram->p_clk 441 xram->p_resetn 442 xram->p_vci 443 xram->p_clk (this->p_clk); 444 xram->p_resetn (this->p_resetn); 445 xram->p_vci (signal_vci_xram); 443 446 444 447 // CDMA 445 mdma->p_clk 446 mdma->p_resetn 447 mdma->p_vci_target 448 mdma->p_vci_initiator 448 mdma->p_clk (this->p_clk); 449 mdma->p_resetn (this->p_resetn); 450 mdma->p_vci_target (signal_vci_tgt_d_mdma); 451 mdma->p_vci_initiator (signal_vci_ini_d_mdma); 449 452 for (size_t p=0 ; p<nprocs ; p++) 450 453 { … … 452 455 } 453 456 454 455 456 457 458 459 bdev->p_clk(this->p_clk);460 bdev->p_resetn(this->p_resetn);461 bdev->p_irq(signal_irq_bdev);462 bdev->p_vci_target(signal_vci_tgt_d_bdev);463 bdev->p_vci_initiator(signal_vci_ini_d_bdev);464 465 466 fbuf->p_clk(this->p_clk);467 fbuf->p_resetn(this->p_resetn);468 fbuf->p_vci(signal_vci_tgt_d_fbuf);469 470 471 brom->p_clk(this->p_clk);472 brom->p_resetn(this->p_resetn);473 brom->p_vci(signal_vci_tgt_d_brom);457 // Components in IO cluster 458 459 if ( io == true ) 460 { 461 // BDEV 462 bdev->p_clk (this->p_clk); 463 bdev->p_resetn (this->p_resetn); 464 bdev->p_irq (signal_irq_bdev); 465 bdev->p_vci_target (signal_vci_tgt_d_bdev); 466 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 467 468 // FBUF 469 fbuf->p_clk (this->p_clk); 470 fbuf->p_resetn (this->p_resetn); 471 fbuf->p_vci (signal_vci_tgt_d_fbuf); 472 473 // BROM 474 brom->p_clk (this->p_clk); 475 brom->p_resetn (this->p_resetn); 476 brom->p_vci (signal_vci_tgt_d_brom); 474 477 475 478 // MTTY 476 mtty->p_clk 477 mtty->p_resetn 478 mtty->p_vci 479 mtty->p_irq[0] 480 mtty->p_irq[1] 481 mtty->p_irq[2] 482 mtty->p_irq[3] 479 mtty->p_clk (this->p_clk); 480 mtty->p_resetn (this->p_resetn); 481 mtty->p_vci (signal_vci_tgt_d_mtty); 482 mtty->p_irq[0] (signal_irq_tty0); 483 mtty->p_irq[1] (signal_irq_tty1); 484 mtty->p_irq[2] (signal_irq_tty2); 485 mtty->p_irq[3] (signal_irq_tty3); 483 486 } 484 487 } // end constructor -
trunk/platforms/tsarv4_mono_mmu/top.cpp
r207 r247 54 54 #define MEMC_SIZE 0x02000000 55 55 56 // segments definition in coherence space57 58 #define C_L1_BASE 0x1000000059 #define C_L1_SIZE 0x0000001060 61 #define C_MC_BASE 0x0000000062 #define C_MC_SIZE 0x0200001063 64 #define C_BR_BASE 0xbfc0000065 #define C_BR_SIZE 0x0004000066 67 56 ///////////////////////////////// 68 57 int _main(int argc, char *argv[]) … … 84 73 size_t from_cycle = 0; // debug start cycle 85 74 size_t max_frozen = 1000; // max number of frozen cycles 75 size_t nprocs = 1; 86 76 87 77 /////////////// command line arguments //////////////// … … 146 136 147 137 // Mapping table for coherence network 148 soclib::common::MappingTable maptabc(32, IntTab(6), IntTab(6), 0xF0000000); 149 maptabc.add(Segment("proc_c" , C_L1_BASE , C_L1_SIZE , IntTab(0), false, true, IntTab(0))); 150 maptabc.add(Segment("memc_c" , C_MC_BASE , C_MC_SIZE , IntTab(1), false )); 151 maptabc.add(Segment("brom_c" , C_BR_BASE , C_BR_SIZE , IntTab(1), false )); 138 soclib::common::MappingTable maptabc(32, IntTab(srcid_width), IntTab(srcid_width), 0xF0000000); 139 maptabc.add( 140 Segment( "proc_c" 141 , 0x0000000 142 , 0x10 143 , IntTab(0) 144 , false 145 ) 146 ); 147 148 maptabc.add( 149 Segment( "memc_c" 150 , nprocs << (address_width - srcid_width) 151 , 0x10 152 , IntTab(nprocs) 153 , false 154 ) 155 ); 152 156 std::cout << maptabc << std::endl; 153 157 154 158 // Signals 155 159 156 sc_clock 160 sc_clock signal_clk ("signal_clk"); 157 161 sc_signal<bool> signal_resetn ("isgnal_resetn"); 158 162 … … 201 205 4,64,16, // dcache size 202 206 4, 4, // wbuf size 207 0, 0, // x, y Width 208 nprocs, // memory cache local id 203 209 max_frozen, // max frozen cycles 204 210 from_cycle, trace_ok);
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