Changeset 247 for trunk/modules/vci_cc_vcache_wrapper_v4/caba/source

Timestamp:

Aug 8, 2012, 12:03:25 PM (12 years ago)

Author:

cfuguet

Message:

Introducing new CLEANUP transaction address specification in the components:

• vci_cc_vcache_wrapper_v4
• vci_mem_cache_v4

The new specification uses the VCI WDATA and the VCI BE to send the cleanup
nline. The VCI ADDRESS is like follows:

• NLINE MSb | Memory Cache local ID | 00....00

The platforms:

• tsarv4_mono_mmu
• tsarv4_generic_mmu

has been modified to use the modified components and the mapping table for the coherence
address space has been updated.

Location:

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source

Files:

• include/vci_cc_vcache_wrapper_v4.h (modified) (2 diffs)
• src/vci_cc_vcache_wrapper_v4.cpp (modified) (3 diffs)

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h

@@ -254 +254 @@
     const size_t                                                m_dcache_words;
 
+    const size_t                        m_x_width;
+    const size_t                        m_y_width;
+
+    const size_t                        m_memory_cache_local_id;
+
     const size_t                        m_proc_id;
 
@@ -625 +630 @@
         size_t   wbuf_nlines, 
         size_t   wbuf_nwords, 
+        size_t   x_width,
+        size_t   y_width,
+        uint32_t memory_cache_local_id,
         uint32_t max_frozen_cycles,
         uint32_t debug_start_cycle,

trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

@@ -166 +166 @@
     size_t                              wbuf_nlines, 
     size_t                              wbuf_nwords, 
-    uint32_t                            max_frozen_cycles,
-    uint32_t                            debug_start_cycle,
+    size_t                              x_width,
+    size_t                              y_width,
+    uint32_t                    memory_cache_local_id,
+    uint32_t                    max_frozen_cycles,
+    uint32_t                    debug_start_cycle,
     bool                                debug_ok)
     : soclib::caba::BaseModule(name),
@@ -197 +200 @@
       m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
       m_dcache_words(dcache_words),
+
+      m_x_width(x_width),
+      m_y_width(y_width),
+
+      m_memory_cache_local_id(memory_cache_local_id),      
 
       m_proc_id(proc_id),
@@ -4812 +4820 @@
     // it depends on the CLEANUP FSM state
 
+    paddr_t  cleanup_nline;
     paddr_t  address;
 
     if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
-        address = r_dcache_cleanup_line.read()*m_dcache_words*4;
+    {
+        cleanup_nline = r_dcache_cleanup_line.read();
+        address       = (m_x_width + m_y_width) ? (cleanup_nline * m_dcache_words * 4    ) >>
+                                                  (vci_param::N  - m_x_width - m_y_width ) : 0;
+    }
     else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
-        address = r_icache_cleanup_line.read()*m_icache_words*4;
+    {
+        cleanup_nline = r_icache_cleanup_line.read();
+        address       = (m_x_width + m_y_width) ? (cleanup_nline * m_icache_words * 4    ) >>
+                                                  (vci_param::N  - m_x_width - m_y_width ) : 0;
+    }
     else
-        address = 0;
+    {
+        cleanup_nline = 0;
+        address       = 0;
+    }
+
+    address           <<= vci_param::S - m_x_width - m_y_width;
+    address            |= m_memory_cache_local_id;
+    address           <<= vci_param::N - vci_param::S;
 
     p_vci_ini_c.cmdval  = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
                            (r_cleanup_fsm.read() == CLEANUP_INS_GO) );
     p_vci_ini_c.address = address;
-    p_vci_ini_c.wdata   = 0;
-    p_vci_ini_c.be      = 0xF;
+    p_vci_ini_c.wdata   = (uint32_t) cleanup_nline;
+    p_vci_ini_c.be      = (cleanup_nline >> 32) & 0x3;
     p_vci_ini_c.plen    = 4;
     p_vci_ini_c.cmd     = vci_param::CMD_WRITE;