- Timestamp:
- Aug 9, 2012, 11:26:59 AM (12 years ago)
- Location:
- trunk/platforms/tsarv4_generic_mmu
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsarv4_generic_mmu/top.cpp
r247 r249 55 55 56 56 /////////////////////////////////////////////////// 57 // 57 // OS 58 58 /////////////////////////////////////////////////// 59 59 … … 75 75 76 76 // cluster index (computed from x,y coordinates) 77 #define cluster(x,y) 77 #define cluster(x,y) (y + ymax*x) 78 78 79 79 // flit widths for the DSPIN network 80 #define cmd_width 81 #define rsp_width 80 #define cmd_width 40 81 #define rsp_width 33 82 82 83 83 // VCI format 84 #define cell_width 85 #define address_width 86 #define plen_width 87 #define error_width 88 #define clen_width 89 #define rflag_width 90 #define srcid_width 91 #define pktid_width 92 #define trdid_width 93 #define wrplen_width 84 #define cell_width 4 85 #define address_width 32 86 #define plen_width 8 87 #define error_width 2 88 #define clen_width 1 89 #define rflag_width 1 90 #define srcid_width 14 91 #define pktid_width 4 92 #define trdid_width 4 93 #define wrplen_width 1 94 94 95 95 /////////////////////////////////////////////////// … … 97 97 /////////////////////////////////////////////////// 98 98 99 #define MESH_XMAX 100 #define MESH_YMAX 101 102 #define NPROCS 99 #define MESH_XMAX 2 100 #define MESH_YMAX 2 101 102 #define NPROCS 4 103 103 #define XRAM_LATENCY 0 104 104 … … 115 115 #define FBUF_Y_SIZE 512 116 116 117 #define BDEV_SECTOR_SIZE128118 #define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw"119 120 #define BOOT_SOFT_NAME 121 122 #define MAX_FROZEN_CYCLES 117 #define BDEV_SECTOR_SIZE 128 118 #define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/couple_512.raw" 119 120 #define BOOT_SOFT_NAME "../../softs/soft_transpose_giet/bin.soft" 121 122 #define MAX_FROZEN_CYCLES 100000 123 123 124 124 ///////////////////////////////////////////////////////// 125 // 125 // Physical segments definition 126 126 ///////////////////////////////////////////////////////// 127 127 // There is 3 segments replicated in all clusters: 128 // - seg_memc -> MEMC / BASE = 0x**000000 129 // - seg_icu 130 // - seg_dma 128 // - seg_memc -> MEMC / BASE = 0x**000000 (12 M bytes) 129 // - seg_icu -> ICU / BASE = 0x**F00000 130 // - seg_dma -> CDMA / BASE = 0x**F30000 131 131 // 132 132 // There is 4 specific segments in the "IO" cluster 133 133 // (containing address 0xBF000000) 134 // - seg_reset -> BROM / BASE = 0xBFC00000(1 Mbytes)135 // - seg_fbuf -> FBUF / BASE = 0xBFD00000(2 M bytes)136 // - seg_bdev 137 // - seg_tty 134 // - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) 135 // - seg_fbuf -> FBUF / BASE = 0xBFD00000 (2 M bytes) 136 // - seg_bdev -> BDEV / BASE = 0xBFF10000 137 // - seg_tty -> MTTY / BASE = 0x**F20000 138 138 // 139 139 // There is one special segment corresponding to 140 140 // the processors in the coherence address space 141 // - seg_proc 141 // - seg_proc -> PROC / BASE = 0x**B0 to 0xBF 142 142 /////////////////////////////////////////////////// 143 143 … … 186 186 int _main(int argc, char *argv[]) 187 187 { 188 using namespace sc_core; 189 using namespace soclib::caba; 190 using namespace soclib::common; 191 192 193 char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code 194 size_t ncycles = 1000000000; // simulated cycles 195 size_t xmax = MESH_XMAX; // number of clusters in a row 196 size_t ymax = MESH_YMAX; // number of clusters in a column 197 size_t nprocs = NPROCS; // number of processors per cluster 198 size_t xfb = FBUF_X_SIZE; // frameBuffer column number 199 size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number 200 size_t memc_ways = MEMC_WAYS; 201 size_t memc_sets = MEMC_SETS; 202 size_t l1_d_ways = L1_DWAYS; 203 size_t l1_d_sets = L1_DSETS; 204 size_t l1_i_ways = L1_IWAYS; 205 size_t l1_i_sets = L1_ISETS; 206 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image 207 size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) 208 size_t xram_latency = XRAM_LATENCY; // external RAM latency 209 bool trace_ok = false; // trace activated 210 size_t trace_period = 1; // trace period 211 uint32_t from_cycle = 0; // debug start cycle 212 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 213 214 ////////////// command line arguments ////////////////////// 215 if (argc > 1) 216 { 217 for( int n=1 ; n<argc ; n=n+2 ) 218 { 219 if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) ) 220 { 221 ncycles = atoi(argv[n+1]); 222 } 223 else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) ) 224 { 225 nprocs = atoi(argv[n+1]); 226 assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) && 227 "NPROCS must be equal to 1, 2, or 4"); 228 } 229 else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) ) 230 { 231 xmax = atoi(argv[n+1]); 232 assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) 233 && "The XMAX parameter must be 2, 4, 8, or 16" ); 234 } 235 236 else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) ) 237 { 238 ymax = atoi(argv[n+1]); 239 assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) 240 && "The YMAX parameter must be 2, 4, 8, or 16" ); 241 } 242 else if( (strcmp(argv[n],"-XFB") == 0) && (n+1<argc) ) 243 { 244 xfb = atoi(argv[n+1]); 245 } 246 else if( (strcmp(argv[n],"-YFB") == 0) && (n+1<argc) ) 247 { 248 yfb = atoi(argv[n+1]); 249 } 250 else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) 251 { 252 strcpy(soft_name, argv[n+1]); 253 } 254 else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) 255 { 256 strcpy(disk_name, argv[n+1]); 257 } 258 else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) ) 259 { 260 trace_ok = true; 261 from_cycle = atoi(argv[n+1]); 262 } 263 else if((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc)) 264 { 265 memc_ways = atoi(argv[n+1]); 266 } 267 else if((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc)) 268 { 269 memc_sets = atoi(argv[n+1]); 270 } 271 else if((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc)) 272 { 273 xram_latency = atoi(argv[n+1]); 274 } 275 else if((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) 276 { 277 frozen_cycles = atoi(argv[n+1]); 278 } 279 else if((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) 280 { 281 trace_period = atoi(argv[n+1]); 282 } 283 else 284 { 285 std::cout << " Arguments on the command line are (key,value) couples." << std::endl; 286 std::cout << " The order is not important." << std::endl; 287 std::cout << " Accepted arguments are :" << std::endl << std::endl; 288 std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; 289 std::cout << " -DISK pathname_for_disk_image" << std::endl; 290 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; 291 std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; 292 std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl; 293 std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl; 294 std::cout << " -TRACE debug_start_cycle" << std::endl; 295 std::cout << " -MCWAYS memory_cache_number_of_ways" << std::endl; 296 std::cout << " -MCSETS memory_cache_number_of_sets" << std::endl; 297 std::cout << " -XLATENCY external_ram_latency_value" << std::endl; 298 std::cout << " -XFB fram_buffer_number_of_pixels" << std::endl; 299 std::cout << " -YFB fram_buffer_number_of_lines" << std::endl; 300 std::cout << " -FROZEN max_number_of_lines" << std::endl; 301 std::cout << " -PERIOD number_of_cycles between trace" << std::endl; 302 exit(0); 303 } 304 } 305 } 306 307 std::cout << std::endl; 308 std::cout << " - NPROCS = " << nprocs << std::endl; 309 std::cout << " - NCLUSTERS = " << xmax*ymax << std::endl; 310 std::cout << " - MAX FROZEN = " << frozen_cycles << std::endl; 311 std::cout << " - MEMC_WAYS = " << memc_ways << std::endl; 312 std::cout << " - MEMC_SETS = " << memc_sets << std::endl; 313 std::cout << " - RAM_LATENCY = " << xram_latency << std::endl; 314 315 std::cout << std::endl; 188 using namespace sc_core; 189 using namespace soclib::caba; 190 using namespace soclib::common; 191 192 193 char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code 194 size_t ncycles = 1000000000; // simulated cycles 195 size_t xmax = MESH_XMAX; // number of clusters in a row 196 size_t ymax = MESH_YMAX; // number of clusters in a column 197 size_t nprocs = NPROCS; // number of processors per cluster 198 size_t xfb = FBUF_X_SIZE; // frameBuffer column number 199 size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number 200 size_t memc_ways = MEMC_WAYS; 201 size_t memc_sets = MEMC_SETS; 202 size_t l1_d_ways = L1_DWAYS; 203 size_t l1_d_sets = L1_DSETS; 204 size_t l1_i_ways = L1_IWAYS; 205 size_t l1_i_sets = L1_ISETS; 206 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image 207 size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) 208 size_t xram_latency = XRAM_LATENCY; // external RAM latency 209 bool trace_ok = false; // trace activated 210 size_t trace_period = 1; // trace period 211 uint32_t from_cycle = 0; // debug start cycle 212 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 213 214 ////////////// command line arguments ////////////////////// 215 if (argc > 1){ 216 for (int n = 1; n < argc; n = n + 2){ 217 if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)){ 218 ncycles = atoi(argv[n+1]); 219 } 220 else if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc)){ 221 nprocs = atoi(argv[n+1]); 222 assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) && 223 "NPROCS must be equal to 1, 2, or 4"); 224 } 225 else if ((strcmp(argv[n],"-XMAX") == 0) && (n+1<argc)){ 226 xmax = atoi(argv[n+1]); 227 assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) 228 && "The XMAX parameter must be 2, 4, 8, or 16" ); 229 } 230 231 else if ((strcmp(argv[n],"-YMAX") == 0) && (n+1<argc)){ 232 ymax = atoi(argv[n+1]); 233 assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) 234 && "The YMAX parameter must be 2, 4, 8, or 16" ); 235 } 236 else if ((strcmp(argv[n],"-XFB") == 0) && (n+1<argc)){ 237 xfb = atoi(argv[n+1]); 238 } 239 else if ((strcmp(argv[n],"-YFB") == 0) && (n+1<argc) ){ 240 yfb = atoi(argv[n+1]); 241 } 242 else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ){ 243 strcpy(soft_name, argv[n+1]); 244 } 245 else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ){ 246 strcpy(disk_name, argv[n+1]); 247 } 248 else if ((strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) ){ 249 trace_ok = true; 250 from_cycle = atoi(argv[n+1]); 251 } 252 else if ((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc)){ 253 memc_ways = atoi(argv[n+1]); 254 } 255 else if ((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc)){ 256 memc_sets = atoi(argv[n+1]); 257 } 258 else if ((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc)){ 259 xram_latency = atoi(argv[n+1]); 260 } 261 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)){ 262 frozen_cycles = atoi(argv[n+1]); 263 } 264 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)){ 265 trace_period = atoi(argv[n+1]); 266 } 267 else 268 { 269 std::cout << " Arguments on the command line are (key,value) couples." << std::endl; 270 std::cout << " The order is not important." << std::endl; 271 std::cout << " Accepted arguments are :" << std::endl << std::endl; 272 std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; 273 std::cout << " -DISK pathname_for_disk_image" << std::endl; 274 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; 275 std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; 276 std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl; 277 std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl; 278 std::cout << " -TRACE debug_start_cycle" << std::endl; 279 std::cout << " -MCWAYS memory_cache_number_of_ways" << std::endl; 280 std::cout << " -MCSETS memory_cache_number_of_sets" << std::endl; 281 std::cout << " -XLATENCY external_ram_latency_value" << std::endl; 282 std::cout << " -XFB fram_buffer_number_of_pixels" << std::endl; 283 std::cout << " -YFB fram_buffer_number_of_lines" << std::endl; 284 std::cout << " -FROZEN max_number_of_lines" << std::endl; 285 std::cout << " -PERIOD number_of_cycles between trace" << std::endl; 286 exit(0); 287 } 288 } 289 } 290 291 std::cout << std::endl; 292 std::cout << " - NPROCS = " << nprocs << std::endl; 293 std::cout << " - NCLUSTERS = " << xmax*ymax << std::endl; 294 std::cout << " - MAX FROZEN = " << frozen_cycles << std::endl; 295 std::cout << " - MEMC_WAYS = " << memc_ways << std::endl; 296 std::cout << " - MEMC_SETS = " << memc_sets << std::endl; 297 std::cout << " - RAM_LATENCY = " << xram_latency << std::endl; 298 299 std::cout << std::endl; 316 300 317 301 #if USE_OPENMP 318 319 320 302 omp_set_dynamic(false); 303 omp_set_num_threads(threads_nr); 304 std::cerr << "Built with openmp version " << _OPENMP << std::endl; 321 305 #endif 322 306 323 // Define VCI parameters 324 typedef soclib::caba::VciParams<cell_width, 325 plen_width, 326 address_width, 327 error_width, 328 clen_width, 329 rflag_width, 330 srcid_width, 331 pktid_width, 332 trdid_width, 333 wrplen_width> vci_param; 334 335 size_t cluster_io_index; 336 size_t x_width; 337 size_t y_width; 338 339 if (xmax == 1) x_width = 0; 340 else if (xmax == 2) x_width = 1; 341 else if (xmax <= 4) x_width = 2; 342 else if (xmax <= 8) x_width = 3; 343 else x_width = 4; 344 345 if (ymax == 1) y_width = 0; 346 else if (ymax == 2) y_width = 1; 347 else if (ymax <= 4) y_width = 2; 348 else if (ymax <= 8) y_width = 3; 349 else y_width = 4; 350 351 cluster_io_index = 0xBF >> (8 - x_width - y_width); 352 353 ///////////////////// 354 // Mapping Tables 355 ///////////////////// 356 357 // direct network 358 MappingTable maptabd(address_width, 359 IntTab(x_width + y_width, 16 - x_width - y_width), 360 IntTab(x_width + y_width, srcid_width - x_width - y_width), 361 0x00FF0000); 362 363 for ( size_t x = 0 ; x < xmax ; x++) 364 { 365 for ( size_t y = 0 ; y < ymax ; y++) 366 { 367 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 368 369 std::ostringstream sh; 370 sh << "d_seg_memc_" << x << "_" << y; 371 maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); 372 373 std::ostringstream si; 374 si << "d_seg_xicu_" << x << "_" << y; 375 maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); 376 377 std::ostringstream sd; 378 sd << "d_seg_mdma_" << x << "_" << y; 379 maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); 380 381 if ( cluster(x,y) == cluster_io_index ) 382 { 383 maptabd.add(Segment("d_seg_mtty ", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); 384 maptabd.add(Segment("d_seg_fbuf ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); 385 maptabd.add(Segment("d_seg_bdev ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); 386 maptabd.add(Segment("d_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); 387 } 388 } 389 } 390 std::cout << maptabd << std::endl; 391 392 // coherence network 393 // - tgtid_c_proc = srcid_c_proc = local procid 394 // - tgtid_c_memc = srcid_c_memc = nprocs 395 MappingTable maptabc(address_width, 396 IntTab(x_width + y_width, srcid_width - x_width - y_width), 397 IntTab(x_width + y_width, srcid_width - x_width - y_width), 398 0x00FF0000); 399 400 for ( size_t x = 0 ; x < xmax ; x++) 401 { 402 for ( size_t y = 0 ; y < ymax ; y++) 403 { 404 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 405 406 // cleanup requests regarding the memc segment must be routed to the memory cache 407 std::ostringstream sh; 408 sh << "c_seg_memc_" << x << "_" << y; 409 maptabc.add( 410 Segment( 411 sh.str() 412 , (nprocs << (address_width - srcid_width)) + offset 413 , 0x10 414 , IntTab(cluster(x,y), nprocs) 415 , false 416 ) 417 ); 418 419 // update & invalidate requests must be routed to the proper processor 420 for ( size_t p = 0 ; p < nprocs ; p++) 421 { 422 std::ostringstream sp; 423 sp << "c_seg_proc_" << x << "_" << y << "_" << p; 424 maptabc.add( 425 Segment( 426 sp.str() 427 , (p << (address_width - srcid_width)) + offset 428 , 0x10 429 , IntTab(cluster(x,y), p) 430 , false 431 ) 432 ); 433 } 434 } 435 } 436 std::cout << maptabc << std::endl; 437 438 // external network 439 MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); 440 441 for ( size_t x = 0 ; x < xmax ; x++) 442 { 443 for ( size_t y = 0 ; y < ymax ; y++) 444 { 445 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 446 std::ostringstream sh; 447 sh << "x_seg_memc_" << x << "_" << y; 448 maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false)); 449 } 450 } 451 std::cout << maptabx << std::endl; 452 453 //////////////////// 454 // Signals 455 /////////////////// 456 457 sc_clock signal_clk("clk"); 458 sc_signal<bool> signal_resetn("resetn"); 459 460 // Horizontal inter-clusters DSPIN signals 461 DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc = 307 // Define VCI parameters 308 typedef soclib::caba::VciParams<cell_width, 309 plen_width, 310 address_width, 311 error_width, 312 clen_width, 313 rflag_width, 314 srcid_width, 315 pktid_width, 316 trdid_width, 317 wrplen_width> vci_param; 318 319 size_t cluster_io_index; 320 size_t x_width; 321 size_t y_width; 322 323 if (xmax == 1) x_width = 0; 324 else if (xmax == 2) x_width = 1; 325 else if (xmax <= 4) x_width = 2; 326 else if (xmax <= 8) x_width = 3; 327 else x_width = 4; 328 329 if (ymax == 1) y_width = 0; 330 else if (ymax == 2) y_width = 1; 331 else if (ymax <= 4) y_width = 2; 332 else if (ymax <= 8) y_width = 3; 333 else y_width = 4; 334 335 cluster_io_index = 0xBF >> (8 - x_width - y_width); 336 337 ///////////////////// 338 // Mapping Tables 339 ///////////////////// 340 341 // direct network 342 MappingTable maptabd(address_width, 343 IntTab(x_width + y_width, 16 - x_width - y_width), 344 IntTab(x_width + y_width, srcid_width - x_width - y_width), 345 0x00FF0000); 346 347 for (size_t x = 0; x < xmax; x++){ 348 for (size_t y = 0; y < ymax; y++){ 349 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 350 351 std::ostringstream sh; 352 sh << "d_seg_memc_" << x << "_" << y; 353 maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); 354 355 std::ostringstream si; 356 si << "d_seg_xicu_" << x << "_" << y; 357 maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); 358 359 std::ostringstream sd; 360 sd << "d_seg_mdma_" << x << "_" << y; 361 maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); 362 363 if ( cluster(x,y) == cluster_io_index ) 364 { 365 maptabd.add(Segment("d_seg_mtty ", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); 366 maptabd.add(Segment("d_seg_fbuf ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); 367 maptabd.add(Segment("d_seg_bdev ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); 368 maptabd.add(Segment("d_seg_brom ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); 369 } 370 } 371 } 372 std::cout << maptabd << std::endl; 373 374 // coherence network 375 // - tgtid_c_proc = srcid_c_proc = local procid 376 // - tgtid_c_memc = srcid_c_memc = nprocs 377 MappingTable maptabc(address_width, 378 IntTab(x_width + y_width, srcid_width - x_width - y_width), 379 IntTab(x_width + y_width, srcid_width - x_width - y_width), 380 0x00FF0000); 381 382 for (size_t x = 0; x < xmax; x++){ 383 for (size_t y = 0; y < ymax; y++){ 384 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 385 386 // cleanup requests regarding the memc segment must be routed to the memory cache 387 std::ostringstream sh; 388 sh << "c_seg_memc_" << x << "_" << y; 389 maptabc.add(Segment(sh.str(), (nprocs << (address_width - srcid_width)) + offset, 0x10, IntTab(cluster(x,y), nprocs), false)); 390 391 // update & invalidate requests must be routed to the proper processor 392 for ( size_t p = 0 ; p < nprocs ; p++) { 393 std::ostringstream sp; 394 sp << "c_seg_proc_" << x << "_" << y << "_" << p; 395 maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 0x10 , IntTab(cluster(x,y), p) , false)); 396 } 397 } 398 } 399 std::cout << maptabc << std::endl; 400 401 // external network 402 MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); 403 404 for (size_t x = 0; x < xmax; x++){ 405 for (size_t y = 0; y < ymax ; y++){ 406 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 407 std::ostringstream sh; 408 sh << "x_seg_memc_" << x << "_" << y; 409 maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false)); 410 } 411 } 412 std::cout << maptabx << std::endl; 413 414 //////////////////// 415 // Signals 416 /////////////////// 417 418 sc_clock signal_clk("clk"); 419 sc_signal<bool> signal_resetn("resetn"); 420 421 // Horizontal inter-clusters DSPIN signals 422 DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc = 462 423 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2); 463 424 DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec = 464 425 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2); 465 426 DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc = 466 427 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2); 467 428 DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec = 468 429 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2); 469 430 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 431 // Vertical inter-clusters DSPIN signals 432 DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc = 433 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2); 434 DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec = 435 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2); 436 DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc = 437 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2); 438 DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec = 439 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2); 440 441 // Mesh boundaries DSPIN signals 442 DspinSignals<cmd_width>**** signal_dspin_false_cmd_in = 443 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4); 444 DspinSignals<cmd_width>**** signal_dspin_false_cmd_out = 445 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4); 446 DspinSignals<rsp_width>**** signal_dspin_false_rsp_in = 447 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4); 448 DspinSignals<rsp_width>**** signal_dspin_false_rsp_out = 449 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4); 450 451 452 //////////////////////////// 453 // Components 454 //////////////////////////// 494 455 495 456 #if USE_ALMOS 496 497 498 457 soclib::common::Loader loader(almos_bootloader_pathname, 458 almos_archinfo_pathname, 459 almos_kernel_pathname); 499 460 #else 500 461 soclib::common::Loader loader(soft_name); 501 462 #endif 502 463 503 504 505 506 464 typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; 465 proc_iss::set_loader(loader); 466 467 TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax]; 507 468 508 469 #if USE_OPENMP 509 470 510 471 #pragma omp parallel 511 {472 { 512 473 #pragma omp for 513 for( size_t i = 0 ; i < (xmax * ymax); i++) 514 { 515 size_t x = i / ymax; 516 size_t y = i % ymax; 474 for(size_t i = 0; i < (xmax * ymax); i++){ 475 size_t x = i / ymax; 476 size_t y = i % ymax; 517 477 518 478 #pragma omp critical 519 520 521 522 479 std::ostringstream sc; 480 sc << "cluster_" << x << "_" << y; 481 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 482 (sc.str().c_str(), 523 483 nprocs, 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 484 x, 485 y, 486 cluster(x,y), 487 maptabd, 488 maptabc, 489 maptabx, 490 x_width, 491 y_width, 492 MEMC_TGTID, 493 XICU_TGTID, 494 FBUF_TGTID, 495 MTTY_TGTID, 496 BROM_TGTID, 497 BDEV_TGTID, 498 CDMA_TGTID, 539 499 memc_ways, 540 500 memc_sets, … … 544 504 l1_d_sets, 545 505 xram_latency, 546 547 548 549 550 551 506 (cluster(x,y) == cluster_io_index), 507 xfb, 508 yfb, 509 disk_name, 510 blk_size, 511 loader, 552 512 frozen_cycles, 553 513 from_cycle, 554 514 trace_ok and (cluster_io_index == cluster(x,y)) ); 555 } 515 } 516 } 556 517 557 518 #else // NO OPENMP 558 519 559 for( size_t x = 0 ; x < xmax ; x++) 560 { 561 for( size_t y = 0 ; y < ymax ; y++ ) 562 { 563 564 std::cout << "building cluster_" << x << "_" << y << std::endl; 565 566 std::ostringstream sc; 567 sc << "cluster_" << x << "_" << y; 568 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 569 (sc.str().c_str(), 520 for (size_t x = 0; x < xmax; x++){ 521 for (size_t y = 0; y < ymax; y++){ 522 523 std::cout << "building cluster_" << x << "_" << y << std::endl; 524 525 std::ostringstream sc; 526 sc << "cluster_" << x << "_" << y; 527 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 528 (sc.str().c_str(), 570 529 nprocs, 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 530 x, 531 y, 532 cluster(x,y), 533 maptabd, 534 maptabc, 535 maptabx, 536 x_width, 537 y_width, 538 MEMC_TGTID, 539 XICU_TGTID, 540 FBUF_TGTID, 541 MTTY_TGTID, 542 BROM_TGTID, 543 BDEV_TGTID, 544 CDMA_TGTID, 586 545 memc_ways, 587 546 memc_sets, … … 591 550 l1_d_sets, 592 551 xram_latency, 593 594 595 596 597 598 552 (cluster(x,y) == cluster_io_index), 553 xfb, 554 yfb, 555 disk_name, 556 blk_size, 557 loader, 599 558 frozen_cycles, 600 559 from_cycle, 601 560 trace_ok and (cluster_io_index == cluster(x,y)) ); 602 561 603 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; 604 605 } 606 } 607 608 #endif // USE_OPENMP 609 610 /////////////////////////////////////////////////////////////// 611 // Net-list 612 /////////////////////////////////////////////////////////////// 613 614 // Clock & RESET 615 for ( size_t x = 0 ; x < (xmax) ; x++ ) 616 { 617 for ( size_t y = 0 ; y < ymax ; y++ ) 618 { 619 clusters[x][y]->p_clk (signal_clk); 620 clusters[x][y]->p_resetn (signal_resetn); 621 } 622 } 623 624 // Inter Clusters horizontal connections 625 if ( xmax > 1 ) 626 { 627 for ( size_t x = 0 ; x < (xmax-1) ; x++ ) 628 { 629 for ( size_t y = 0 ; y < ymax ; y++ ) 630 { 631 for ( size_t k = 0 ; k < 2 ; k++ ) 632 { 633 clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); 634 clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); 635 clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); 636 clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); 637 clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); 638 clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); 639 clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); 640 clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); 641 } 562 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; 563 564 } 565 } 566 567 #endif // USE_OPENMP 568 569 /////////////////////////////////////////////////////////////// 570 // Net-list 571 /////////////////////////////////////////////////////////////// 572 573 // Clock & RESET 574 for (size_t x = 0; x < (xmax); x++){ 575 for (size_t y = 0; y < ymax; y++){ 576 clusters[x][y]->p_clk (signal_clk); 577 clusters[x][y]->p_resetn (signal_resetn); 578 } 579 } 580 581 // Inter Clusters horizontal connections 582 if (xmax > 1){ 583 for (size_t x = 0; x < (xmax-1); x++){ 584 for (size_t y = 0; y < ymax; y++){ 585 for (size_t k = 0; k < 2; k++){ 586 clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); 587 clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); 588 clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); 589 clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); 590 clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); 591 clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); 592 clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); 593 clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); 642 594 } 643 } 644 } 645 std::cout << "Horizontal connections established" << std::endl; 646 647 // Inter Clusters vertical connections 648 if ( ymax > 1 ) 649 { 650 for ( size_t y = 0 ; y < (ymax-1) ; y++ ) 651 { 652 for ( size_t x = 0 ; x < xmax ; x++ ) 653 { 654 for ( size_t k = 0 ; k < 2 ; k++ ) 655 { 656 clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); 657 clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); 658 clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); 659 clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); 660 clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); 661 clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); 662 clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); 663 clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); 664 } 595 } 596 } 597 } 598 std::cout << "Horizontal connections established" << std::endl; 599 600 // Inter Clusters vertical connections 601 if (ymax > 1) { 602 for (size_t y = 0; y < (ymax-1); y++){ 603 for (size_t x = 0; x < xmax; x++){ 604 for (size_t k = 0; k < 2; k++){ 605 clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); 606 clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); 607 clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); 608 clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); 609 clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); 610 clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); 611 clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); 612 clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); 665 613 } 666 } 667 } 668 std::cout << "Vertical connections established" << std::endl; 669 670 // East & West boundary cluster connections 671 for ( size_t y = 0 ; y < ymax ; y++ ) 672 { 673 for ( size_t k = 0 ; k < 2 ; k++ ) 674 { 675 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); 676 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); 677 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); 678 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); 679 680 clusters[xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]); 681 clusters[xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]); 682 clusters[xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]); 683 clusters[xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]); 684 } 685 } 686 687 // North & South boundary clusters connections 688 for ( size_t x = 0 ; x < xmax ; x++ ) 689 { 690 for ( size_t k = 0 ; k < 2 ; k++ ) 691 { 692 clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); 693 clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); 694 clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); 695 clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); 696 697 clusters[x][ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]); 698 clusters[x][ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]); 699 clusters[x][ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]); 700 clusters[x][ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]); 701 } 702 } 703 704 705 //////////////////////////////////////////////////////// 706 // Simulation 707 /////////////////////////////////////////////////////// 708 709 sc_start(sc_core::sc_time(0, SC_NS)); 710 signal_resetn = false; 711 712 // network boundaries signals 713 for(size_t x=0; x<xmax ; x++) 714 { 715 for(size_t y=0 ; y<ymax ; y++) 716 { 717 for (size_t k=0; k<2; k++) 718 { 719 for(size_t a=0; a<4; a++) 720 { 721 signal_dspin_false_cmd_in[x][y][k][a].write = false; 722 signal_dspin_false_cmd_in[x][y][k][a].read = true; 723 signal_dspin_false_cmd_out[x][y][k][a].write = false; 724 signal_dspin_false_cmd_out[x][y][k][a].read = true; 725 726 signal_dspin_false_rsp_in[x][y][k][a].write = false; 727 signal_dspin_false_rsp_in[x][y][k][a].read = true; 728 signal_dspin_false_rsp_out[x][y][k][a].write = false; 729 signal_dspin_false_rsp_out[x][y][k][a].read = true; 730 } 614 } 615 } 616 } 617 std::cout << "Vertical connections established" << std::endl; 618 619 // East & West boundary cluster connections 620 for (size_t y = 0; y < ymax; y++){ 621 for (size_t k = 0; k < 2; k++){ 622 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); 623 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); 624 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); 625 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); 626 627 clusters[xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]); 628 clusters[xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]); 629 clusters[xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]); 630 clusters[xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]); 631 } 632 } 633 634 // North & South boundary clusters connections 635 for (size_t x = 0; x < xmax; x++){ 636 for (size_t k = 0; k < 2; k++){ 637 clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); 638 clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); 639 clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); 640 clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); 641 642 clusters[x][ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]); 643 clusters[x][ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]); 644 clusters[x][ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]); 645 clusters[x][ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]); 646 } 647 } 648 649 650 //////////////////////////////////////////////////////// 651 // Simulation 652 /////////////////////////////////////////////////////// 653 654 sc_start(sc_core::sc_time(0, SC_NS)); 655 signal_resetn = false; 656 657 // network boundaries signals 658 for (size_t x = 0; x < xmax ; x++){ 659 for (size_t y = 0; y < ymax ; y++){ 660 for (size_t k = 0; k < 2; k++){ 661 for (size_t a = 0; a < 4; a++){ 662 signal_dspin_false_cmd_in[x][y][k][a].write = false; 663 signal_dspin_false_cmd_in[x][y][k][a].read = true; 664 signal_dspin_false_cmd_out[x][y][k][a].write = false; 665 signal_dspin_false_cmd_out[x][y][k][a].read = true; 666 667 signal_dspin_false_rsp_in[x][y][k][a].write = false; 668 signal_dspin_false_rsp_in[x][y][k][a].read = true; 669 signal_dspin_false_rsp_out[x][y][k][a].write = false; 670 signal_dspin_false_rsp_out[x][y][k][a].read = true; 731 671 } 732 } 733 } 734 735 sc_start(sc_core::sc_time(1, SC_NS)); 736 signal_resetn = true; 737 738 for ( size_t n=1 ; n<ncycles ; n++) 739 { 740 if ( trace_ok and (n > from_cycle) and (n%trace_period == 0) ) 741 { 742 std::cout << "****************** cycle " << std::dec << n ; 743 std::cout << " ************************************************" << std::endl; 744 745 // components cluster 00 ///////////////////// 746 // clusters[0][0]->proc[0]->print_trace(); 747 // clusters[0][0]->memc->print_trace(); 748 749 // signals cluster 00 //////////////////////// 750 // clusters[0][0]->signal_vci_ini_d_proc[0].print_trace("proc_0_0_0_ini_d"); 751 // clusters[0][0]->signal_vci_ini_c_proc[0].print_trace("proc_0_0_0_ini_c"); 752 // clusters[0][0]->signal_vci_tgt_c_proc[0].print_trace("proc_0_0_0_tgt_c"); 753 // clusters[0][0]->signal_vci_xram.print_trace("memc_0_0_xram"); 754 755 // components cluster 01 ///////////////////// 756 // clusters[0][1]->proc[0]->print_trace(); 757 // clusters[0][1]->memc->print_trace(); 758 759 // signals cluster 01 /////////////////////// 760 // clusters[0][1]->signal_vci_ini_d_proc[0].print_trace("proc_0_1_0_ini_d"); 761 // clusters[0][1]->signal_vci_ini_c_proc[0].print_trace("proc_0_1_0_ini_c"); 762 // clusters[0][1]->signal_vci_tgt_c_proc[0].print_trace("proc_0_1_0_tgt_c"); 763 // clusters[0][1]->signal_vci_xram.print_trace("memc_0_1_xram"); 764 765 // components cluster 10 //////////////////// 766 clusters[1][0]->proc[0]->print_trace(1); 767 clusters[1][0]->memc->print_trace(); 768 // clusters[1][0]->bdev->print_trace(); 769 // clusters[1][0]->mdma->print_trace(); 770 771 // signals cluster 10 /////////////////////// 772 clusters[1][0]->signal_vci_ini_d_proc[0].print_trace("proc_1_0_0_ini_d"); 773 // clusters[1][0]->signal_vci_ini_c_proc[0].print_trace("proc_1_0_0_ini_c"); 774 // clusters[1][0]->signal_vci_tgt_c_proc[0].print_trace("proc_1_0_0_tgt_c"); 775 clusters[1][0]->signal_vci_tgt_d_memc.print_trace("memc_1_0_tgt_d "); 776 // clusters[1][0]->signal_vci_ini_c_memc.print_trace("memc_1_0_ini_c "); 777 // clusters[1][0]->signal_vci_tgt_c_memc.print_trace("memc_1_0_tgt_c "); 778 // clusters[1][0]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); 779 // clusters[1][0]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); 780 // clusters[1][0]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); 781 // clusters[1][0]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); 782 clusters[1][0]->signal_vci_tgt_d_mtty.print_trace("mtty_1_0_tgt_d "); 783 clusters[1][0]->signal_vci_xram.print_trace("memc_1_0_xram"); 784 785 // components cluster 11 ///////////////////// 786 // clusters[1][1]->proc[0]->print_trace(); 787 // clusters[1][1]->memc->print_trace(); 788 789 // signals cluster 11 //////////////////////// 790 // clusters[1][1]->signal_vci_ini_d_proc[0].print_trace("proc_1_1_0_ini_d"); 791 // clusters[1][1]->signal_vci_ini_c_proc[0].print_trace("proc_1_1_0_ini_c"); 792 // clusters[1][1]->signal_vci_tgt_c_proc[0].print_trace("proc_1_1_0_tgt_c"); 793 // clusters[1][1]->signal_vci_xram.print_trace("memc_1_1_xram"); 794 } 795 796 sc_start(sc_core::sc_time(1, SC_NS)); 797 } 798 return EXIT_SUCCESS; 672 } 673 } 674 } 675 676 sc_start(sc_core::sc_time(1, SC_NS)); 677 signal_resetn = true; 678 679 for (size_t n = 1; n < ncycles; n++){ 680 if (trace_ok and (n > from_cycle) and (n % trace_period == 0)){ 681 std::cout << "****************** cycle " << std::dec << n ; 682 std::cout << " ************************************************" << std::endl; 683 684 // components cluster 00 ///////////////////// 685 // clusters[0][0]->proc[0]->print_trace(); 686 // clusters[0][0]->memc->print_trace(); 687 688 // signals cluster 00 //////////////////////// 689 // clusters[0][0]->signal_vci_ini_d_proc[0].print_trace("proc_0_0_0_ini_d"); 690 // clusters[0][0]->signal_vci_ini_c_proc[0].print_trace("proc_0_0_0_ini_c"); 691 // clusters[0][0]->signal_vci_tgt_c_proc[0].print_trace("proc_0_0_0_tgt_c"); 692 // clusters[0][0]->signal_vci_xram.print_trace("memc_0_0_xram"); 693 694 // components cluster 01 ///////////////////// 695 // clusters[0][1]->proc[0]->print_trace(); 696 // clusters[0][1]->memc->print_trace(); 697 698 // signals cluster 01 /////////////////////// 699 // clusters[0][1]->signal_vci_ini_d_proc[0].print_trace("proc_0_1_0_ini_d"); 700 // clusters[0][1]->signal_vci_ini_c_proc[0].print_trace("proc_0_1_0_ini_c"); 701 // clusters[0][1]->signal_vci_tgt_c_proc[0].print_trace("proc_0_1_0_tgt_c"); 702 // clusters[0][1]->signal_vci_xram.print_trace("memc_0_1_xram"); 703 704 // components cluster 10 //////////////////// 705 clusters[1][0]->proc[0]->print_trace(1); 706 clusters[1][0]->memc->print_trace(); 707 // clusters[1][0]->bdev->print_trace(); 708 // clusters[1][0]->mdma->print_trace(); 709 710 // signals cluster 10 /////////////////////// 711 clusters[1][0]->signal_vci_ini_d_proc[0].print_trace("proc_1_0_0_ini_d"); 712 // clusters[1][0]->signal_vci_ini_c_proc[0].print_trace("proc_1_0_0_ini_c"); 713 // clusters[1][0]->signal_vci_tgt_c_proc[0].print_trace("proc_1_0_0_tgt_c"); 714 clusters[1][0]->signal_vci_tgt_d_memc.print_trace("memc_1_0_tgt_d "); 715 // clusters[1][0]->signal_vci_ini_c_memc.print_trace("memc_1_0_ini_c "); 716 // clusters[1][0]->signal_vci_tgt_c_memc.print_trace("memc_1_0_tgt_c "); 717 // clusters[1][0]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); 718 // clusters[1][0]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); 719 // clusters[1][0]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); 720 // clusters[1][0]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); 721 clusters[1][0]->signal_vci_tgt_d_mtty.print_trace("mtty_1_0_tgt_d "); 722 clusters[1][0]->signal_vci_xram.print_trace("memc_1_0_xram"); 723 724 // components cluster 11 ///////////////////// 725 // clusters[1][1]->proc[0]->print_trace(); 726 // clusters[1][1]->memc->print_trace(); 727 728 // signals cluster 11 //////////////////////// 729 // clusters[1][1]->signal_vci_ini_d_proc[0].print_trace("proc_1_1_0_ini_d"); 730 // clusters[1][1]->signal_vci_ini_c_proc[0].print_trace("proc_1_1_0_ini_c"); 731 // clusters[1][1]->signal_vci_tgt_c_proc[0].print_trace("proc_1_1_0_tgt_c"); 732 // clusters[1][1]->signal_vci_xram.print_trace("memc_1_1_xram"); 733 } 734 735 sc_start(sc_core::sc_time(1, SC_NS)); 736 } 737 return EXIT_SUCCESS; 799 738 } 800 739 801 740 int sc_main (int argc, char *argv[]) 802 741 { 803 804 805 806 807 808 809 810 811 742 try { 743 return _main(argc, argv); 744 } catch (std::exception &e) { 745 std::cout << e.what() << std::endl; 746 } catch (...) { 747 std::cout << "Unknown exception occured" << std::endl; 748 throw; 749 } 750 return 1; 812 751 } 752 753 754 // Local Variables: 755 // tab-width: 3 756 // c-basic-offset: 3 757 // c-file-offsets:((innamespace . 0)(inline-open . 0)) 758 // indent-tabs-mode: nil 759 // End: 760 761 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 762 763 764 765 -
trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
r247 r249 8 8 ////////////////////////////////////////////////////////////////////////// 9 9 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 10 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu( 11 sc_module_name insname, 12 size_t nprocs, 13 size_t x_id, 14 size_t y_id, 15 size_t cluster_id, 16 const soclib::common::MappingTable &mtd, 17 const soclib::common::MappingTable &mtc, 18 const soclib::common::MappingTable &mtx, 19 size_t x_width, 20 size_t y_width, 21 size_t tgtid_memc, 22 size_t tgtid_xicu, 23 size_t tgtid_fbuf, 24 size_t tgtid_mtty, 25 size_t tgtid_brom, 26 size_t tgtid_bdev, 27 size_t tgtid_mdma, 28 size_t memc_ways, 29 size_t memc_sets, 30 size_t l1_i_ways, 31 size_t l1_i_sets, 32 size_t l1_d_ways, 33 size_t l1_d_sets, 34 size_t xram_latency, 35 bool io, 36 size_t xfb, 37 size_t yfb, 38 char* disk_name, 39 size_t block_size, 40 const Loader &loader, 41 uint32_t frozen_cycles, 42 uint32_t debug_start_cycle, 43 bool debug_ok) 44 : soclib::caba::BaseModule(insname), 45 p_clk("clk"), 46 p_resetn("resetn"), 47 48 signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), 49 signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), 50 signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), 51 signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), 52 signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), 53 signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), 54 signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), 55 signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), 56 57 signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), 58 signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), 59 60 signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), 61 signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), 62 signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), 63 signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), 64 signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), 65 signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), 66 signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), 67 68 signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 69 signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), 70 71 signal_vci_xram("signal_vci_xram") 72 73 { 74 // Vectors of ports definition 75 76 p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4); 77 p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4); 78 p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4); 79 p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); 80 81 // Components definition 82 83 // on direct network : local srcid[proc] in [0...nprocs-1] 84 // on direct network : local srcid[mdma] = nprocs 85 // on direct network : local srcid[bdev] = nprocs + 1 86 87 // on coherence network : local srcid[proc] in [0...nprocs-1] 88 // on coherence network : local srcid[memc] = nprocs 89 90 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; 91 92 for ( size_t p=0 ; p<nprocs ; p++ ) 93 { 94 std::ostringstream sproc; 95 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 96 proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>( 97 sproc.str().c_str(), 98 cluster_id*nprocs + p, 99 mtd, // Mapping Table Direct 100 mtc, // Mapping Table Coherence 101 IntTab(cluster_id,p), // SRCID_D 102 IntTab(cluster_id,p), // SRCID_C 103 IntTab(cluster_id,p), // TGTID_C 104 8, // ITLB ways 105 8, // ITLB sets 106 8, // DTLB ways 107 8, // DTLB sets 108 l1_i_ways,l1_i_sets,16, // ICACHE size 109 l1_d_ways,l1_d_sets,16, // DCACHE size 110 4, // WBUF width 111 4, // WBUF depth 112 x_width, // X Width 113 y_width, // Y Width 114 nprocs, // Memory Cache Local Id (coherence) 115 frozen_cycles, // max frozen cycles 116 debug_start_cycle, 117 debug_ok); 118 } 119 120 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 121 122 std::ostringstream smemc; 123 smemc << "memc_" << x_id << "_" << y_id; 124 memc = new VciMemCacheV4<vci_param>( 125 smemc.str().c_str(), 126 mtd, mtc, mtx, 127 IntTab(cluster_id), // SRCID_X 128 IntTab(cluster_id, nprocs), // SRCID_C 129 IntTab(cluster_id, tgtid_memc), // TGTID_D 130 IntTab(cluster_id, nprocs), // TGTID_C 131 memc_ways, memc_sets, 16, // CACHE SIZE 132 4096, // HEAP SIZE 133 8, // TRANSACTION TABLE DEPTH 134 8, // UPDATE TABLE DEPTH 135 debug_start_cycle, 136 debug_ok); 137 138 139 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 140 141 std::ostringstream sxram; 142 sxram << "xram_" << x_id << "_" << y_id; 143 xram = new VciSimpleRam<vci_param>( 144 sxram.str().c_str(), 145 IntTab(cluster_id), 146 mtx, 147 loader, 148 xram_latency); 149 150 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 151 152 size_t nhwi = 4; // always 4 (or 9) ports, even if 153 if( io == true ) nhwi = 9; // there if less than 4 processors 154 std::ostringstream sicu; 155 sicu << "xicu_" << x_id << "_" << y_id; 156 xicu = new VciXicu<vci_param>( 157 sicu.str().c_str(), 158 mtd, // mapping table 159 IntTab(cluster_id, tgtid_xicu), // TGTID_D 160 0, // number of timer IRQs 161 nhwi, // number of hard IRQs 162 0, // number of soft IRQs 163 nprocs); // number of output IRQs 164 165 std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; 166 167 // dma multi-canaux 168 std::ostringstream sdma; 169 sdma << "dma_" << x_id << "_" << y_id; 170 mdma = new VciMultiDma<vci_param>( 171 sdma.str().c_str(), 172 mtd, 173 IntTab(cluster_id, nprocs), // SRCID 174 IntTab(cluster_id, tgtid_mdma), // TGTID 175 64, // burst size 176 nprocs); // number of IRQs 177 178 std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; 179 180 // direct local crossbar 181 size_t nb_direct_initiators = nprocs + 1; 182 size_t nb_direct_targets = 3; 183 if( io == true ) 184 { 185 nb_direct_initiators = nprocs + 2; 186 nb_direct_targets = 7; 187 } 188 std::ostringstream sd; 189 sd << "xbard_" << x_id << "_" << y_id; 190 xbard = new VciLocalCrossbar<vci_param>( 191 sd.str().c_str(), 192 mtd, 193 IntTab(cluster_id), // cluster initiator index 194 IntTab(cluster_id), // cluster target index 195 nb_direct_initiators, // number of initiators 196 nb_direct_targets); // number of targets 197 198 std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; 199 200 // coherence local crossbar 201 std::ostringstream sc; 202 sc << "xbarc_" << x_id << "_" << y_id; 203 xbarc = new VciLocalCrossbar<vci_param>( 204 sc.str().c_str(), 205 mtc, 206 IntTab(cluster_id), // cluster initiator index 207 IntTab(cluster_id), // cluster target index 208 nprocs + 1, // number of initiators 209 nprocs + 1); // number of targets 210 211 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; 212 213 // direct initiator wrapper 214 std::ostringstream wid; 215 wid << "iniwrapperd_" << x_id << "_" << y_id; 216 iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 217 wid.str().c_str(), 218 4, // cmd fifo depth 219 4); // rsp fifo depth 220 221 // direct target wrapper 222 std::ostringstream wtd; 223 wtd << "tgtwrapperd_" << x_id << "_" << y_id; 224 tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 225 wtd.str().c_str(), 226 4, // cmd fifo depth 227 4); // rsp fifo depth 228 229 // coherence initiator wrapper 230 std::ostringstream wic; 231 wic << "iniwrapperc_" << x_id << "_" << y_id; 232 iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 233 wic.str().c_str(), 234 4, // cmd fifo depth 235 4); // rsp fifo depth 236 237 // coherence target wrapper 238 std::ostringstream wtc; 239 wtc << "tgtwrapperc_" << x_id << "_" << y_id; 240 tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 241 wtc.str().c_str(), 242 4, // cmd fifo depth 243 4); // rsp fifo depth 244 245 std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; 246 247 // CMD router 248 std::ostringstream scmd; 249 scmd << "cmdrouter_" << x_id << "_" << y_id; 250 cmdrouter = new VirtualDspinRouter<cmd_width>( 251 scmd.str().c_str(), 252 x_id,y_id, // coordinate in the mesh 253 x_width, y_width, // x & y fields width 254 4,4); // input & output fifo depths 255 256 std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; 257 258 // RSP router 259 std::ostringstream srsp; 260 srsp << "rsprouter_" << x_id << "_" << y_id; 261 rsprouter = new VirtualDspinRouter<rsp_width>( 262 srsp.str().c_str(), 263 x_id,y_id, // coordinates in mesh 264 x_width, y_width, // x & y fields width 265 4,4); // input & output fifo depths 266 267 // IO cluster components 268 if ( io == true ) 269 { 270 brom = new VciSimpleRam<vci_param>( 271 "brom", 272 IntTab(cluster_id, tgtid_brom), 273 mtd, 274 loader); 275 276 fbuf = new VciFrameBuffer<vci_param>( 277 "fbuf", 278 IntTab(cluster_id, tgtid_fbuf), 279 mtd, 280 xfb, yfb); 281 282 bdev = new VciBlockDeviceTsarV4<vci_param>( 283 "bdev", 284 mtd, 285 IntTab(cluster_id, nprocs+1), 286 IntTab(cluster_id, tgtid_bdev), 287 disk_name, 288 block_size); 289 290 mtty = new VciMultiTty<vci_param>( 291 "mtty", 292 IntTab(cluster_id, tgtid_mtty), 293 mtd, 294 "tty0", "tty1", "tty2", "tty3", NULL); 295 } 296 297 std::cout << " - all components constructed" << std::endl; 298 299 //////////////////////////////////// 300 // Connections are defined here 301 //////////////////////////////////// 302 303 // CMDROUTER and RSPROUTER 304 cmdrouter->p_clk (this->p_clk); 305 cmdrouter->p_resetn (this->p_resetn); 306 rsprouter->p_clk (this->p_clk); 307 rsprouter->p_resetn (this->p_resetn); 308 for(int x = 0; x < 2; x++) 309 { 310 for(int y = 0; y < 4; y++) 311 { 312 cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); 313 cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); 314 rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); 315 rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); 316 } 317 } 318 319 cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); 320 cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); 321 cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); 322 cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); 323 324 rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); 325 rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); 326 rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); 327 rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); 328 329 // VCI/DSPIN WRAPPERS 330 iniwrapperd->p_clk (this->p_clk); 331 iniwrapperd->p_resetn (this->p_resetn); 332 iniwrapperd->p_vci (signal_vci_l2g_d); 333 iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); 334 iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); 335 336 tgtwrapperd->p_clk (this->p_clk); 337 tgtwrapperd->p_resetn (this->p_resetn); 338 tgtwrapperd->p_vci (signal_vci_g2l_d); 339 tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); 340 tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); 341 342 iniwrapperc->p_clk (this->p_clk); 343 iniwrapperc->p_resetn (this->p_resetn); 344 iniwrapperc->p_vci (signal_vci_l2g_c); 345 iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); 346 iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); 347 348 tgtwrapperc->p_clk (this->p_clk); 349 tgtwrapperc->p_resetn (this->p_resetn); 350 tgtwrapperc->p_vci (signal_vci_g2l_c); 351 tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); 352 tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); 353 354 // CROSSBAR direct 355 xbard->p_clk (this->p_clk); 356 xbard->p_resetn (this->p_resetn); 357 xbard->p_initiator_to_up (signal_vci_l2g_d); 358 xbard->p_target_to_up (signal_vci_g2l_d); 359 360 xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); 361 xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); 362 xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); 363 364 xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); 365 366 for ( size_t p=0 ; p<nprocs ; p++) 367 { 368 xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); 369 } 370 371 if ( io == true ) 372 { 373 xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); 374 xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); 375 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 376 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 377 378 xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); 379 } 380 381 // CROSSBAR coherence 382 xbarc->p_clk (this->p_clk); 383 xbarc->p_resetn (this->p_resetn); 384 xbarc->p_initiator_to_up (signal_vci_l2g_c); 385 xbarc->p_target_to_up (signal_vci_g2l_c); 386 xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); 387 xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); 388 for ( size_t p=0 ; p<nprocs ; p++) 389 { 390 xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); 391 xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); 392 } 393 394 // Processors 395 for ( size_t p=0 ; p<nprocs ; p++) 396 { 397 proc[p]->p_clk (this->p_clk); 398 proc[p]->p_resetn (this->p_resetn); 399 proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); 400 proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); 401 proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); 402 proc[p]->p_irq[0] (signal_proc_it[p]); 403 for ( size_t j = 1 ; j < 6 ; j++ ) 10 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu( 11 sc_module_name insname, 12 size_t nprocs, 13 size_t x_id, 14 size_t y_id, 15 size_t cluster_id, 16 const soclib::common::MappingTable &mtd, 17 const soclib::common::MappingTable &mtc, 18 const soclib::common::MappingTable &mtx, 19 size_t x_width, 20 size_t y_width, 21 size_t tgtid_memc, 22 size_t tgtid_xicu, 23 size_t tgtid_fbuf, 24 size_t tgtid_mtty, 25 size_t tgtid_brom, 26 size_t tgtid_bdev, 27 size_t tgtid_mdma, 28 size_t memc_ways, 29 size_t memc_sets, 30 size_t l1_i_ways, 31 size_t l1_i_sets, 32 size_t l1_d_ways, 33 size_t l1_d_sets, 34 size_t xram_latency, 35 bool io, 36 size_t xfb, 37 size_t yfb, 38 char* disk_name, 39 size_t block_size, 40 const Loader &loader, 41 uint32_t frozen_cycles, 42 uint32_t debug_start_cycle, 43 bool debug_ok) 44 : soclib::caba::BaseModule(insname), 45 p_clk("clk"), 46 p_resetn("resetn"), 47 48 signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), 49 signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), 50 signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), 51 signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), 52 signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), 53 signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), 54 signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), 55 signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), 56 57 signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), 58 signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), 59 60 signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), 61 signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), 62 signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), 63 signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), 64 signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), 65 signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), 66 signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), 67 68 signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 69 signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), 70 71 signal_vci_xram("signal_vci_xram") 72 404 73 { 405 proc[p]->p_irq[j] (signal_false); 406 } 407 } 408 409 // XICU 410 xicu->p_clk (this->p_clk); 411 xicu->p_resetn (this->p_resetn); 412 xicu->p_vci (signal_vci_tgt_d_xicu); 413 for ( size_t p=0 ; p<nprocs ; p++) 414 { 415 xicu->p_irq[p] (signal_proc_it[p]); 416 } 417 for ( size_t p=0 ; p<nprocs ; p++) 418 { 419 xicu->p_hwi[p] (signal_irq_mdma[p]); 420 } 421 for ( size_t x=nprocs ; x<4 ; x++) 422 { 423 xicu->p_hwi[x] (signal_false); 424 } 425 if ( io == true ) 426 { 427 xicu->p_hwi[4] (signal_irq_tty0); 428 xicu->p_hwi[5] (signal_irq_tty1); 429 xicu->p_hwi[6] (signal_irq_tty2); 430 xicu->p_hwi[7] (signal_irq_tty3); 431 xicu->p_hwi[8] (signal_irq_bdev); 432 } 433 434 // MEMC 435 memc->p_clk (this->p_clk); 436 memc->p_resetn (this->p_resetn); 437 memc->p_vci_ixr (signal_vci_xram); 438 memc->p_vci_tgt (signal_vci_tgt_d_memc); 439 memc->p_vci_ini (signal_vci_ini_c_memc); 440 memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); 441 442 // XRAM 443 xram->p_clk (this->p_clk); 444 xram->p_resetn (this->p_resetn); 445 xram->p_vci (signal_vci_xram); 446 447 // CDMA 448 mdma->p_clk (this->p_clk); 449 mdma->p_resetn (this->p_resetn); 450 mdma->p_vci_target (signal_vci_tgt_d_mdma); 451 mdma->p_vci_initiator (signal_vci_ini_d_mdma); 452 for (size_t p=0 ; p<nprocs ; p++) 453 { 454 mdma->p_irq[p] (signal_irq_mdma[p]); 455 } 456 457 // Components in IO cluster 458 459 if ( io == true ) 460 { 461 // BDEV 462 bdev->p_clk (this->p_clk); 463 bdev->p_resetn (this->p_resetn); 464 bdev->p_irq (signal_irq_bdev); 465 bdev->p_vci_target (signal_vci_tgt_d_bdev); 466 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 467 468 // FBUF 469 fbuf->p_clk (this->p_clk); 470 fbuf->p_resetn (this->p_resetn); 471 fbuf->p_vci (signal_vci_tgt_d_fbuf); 472 473 // BROM 474 brom->p_clk (this->p_clk); 475 brom->p_resetn (this->p_resetn); 476 brom->p_vci (signal_vci_tgt_d_brom); 477 478 // MTTY 479 mtty->p_clk (this->p_clk); 480 mtty->p_resetn (this->p_resetn); 481 mtty->p_vci (signal_vci_tgt_d_mtty); 482 mtty->p_irq[0] (signal_irq_tty0); 483 mtty->p_irq[1] (signal_irq_tty1); 484 mtty->p_irq[2] (signal_irq_tty2); 485 mtty->p_irq[3] (signal_irq_tty3); 486 } 487 } // end constructor 74 // Vectors of ports definition 75 76 p_cmd_in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4); 77 p_cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4); 78 p_rsp_in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4); 79 p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); 80 81 // Components definition 82 83 // on direct network : local srcid[proc] in [0...nprocs-1] 84 // on direct network : local srcid[mdma] = nprocs 85 // on direct network : local srcid[bdev] = nprocs + 1 86 87 // on coherence network : local srcid[proc] in [0...nprocs-1] 88 // on coherence network : local srcid[memc] = nprocs 89 90 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; 91 92 for (size_t p = 0; p < nprocs; p++){ 93 std::ostringstream sproc; 94 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 95 proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>( 96 sproc.str().c_str(), 97 cluster_id*nprocs + p, 98 mtd, // Mapping Table Direct 99 mtc, // Mapping Table Coherence 100 IntTab(cluster_id,p), // SRCID_D 101 IntTab(cluster_id,p), // SRCID_C 102 IntTab(cluster_id,p), // TGTID_C 103 8, // ITLB ways 104 8, // ITLB sets 105 8, // DTLB ways 106 8, // DTLB sets 107 l1_i_ways,l1_i_sets,16, // ICACHE size 108 l1_d_ways,l1_d_sets,16, // DCACHE size 109 4, // WBUF width 110 4, // WBUF depth 111 x_width, // X Width 112 y_width, // Y Width 113 nprocs, // Memory Cache Local Id (coherence) 114 frozen_cycles, // max frozen cycles 115 debug_start_cycle, 116 debug_ok); 117 } 118 119 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 120 121 std::ostringstream smemc; 122 smemc << "memc_" << x_id << "_" << y_id; 123 memc = new VciMemCacheV4<vci_param>( 124 smemc.str().c_str(), 125 mtd, mtc, mtx, 126 IntTab(cluster_id), // SRCID_X 127 IntTab(cluster_id, nprocs), // SRCID_C 128 IntTab(cluster_id, tgtid_memc), // TGTID_D 129 IntTab(cluster_id, nprocs), // TGTID_C 130 memc_ways, memc_sets, 16, // CACHE SIZE 131 4096, // HEAP SIZE 132 8, // TRANSACTION TABLE DEPTH 133 8, // UPDATE TABLE DEPTH 134 debug_start_cycle, 135 debug_ok); 136 137 138 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 139 140 std::ostringstream sxram; 141 sxram << "xram_" << x_id << "_" << y_id; 142 xram = new VciSimpleRam<vci_param>( 143 sxram.str().c_str(), 144 IntTab(cluster_id), 145 mtx, 146 loader, 147 xram_latency); 148 149 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 150 151 size_t nhwi = 4; // always 4 (or 9) ports, even if 152 if (io){ 153 nhwi = 9; // there if less than 4 processors 154 } 155 std::ostringstream sicu; 156 sicu << "xicu_" << x_id << "_" << y_id; 157 xicu = new VciXicu<vci_param>( 158 sicu.str().c_str(), 159 mtd, // mapping table 160 IntTab(cluster_id, tgtid_xicu), // TGTID_D 161 0, // number of timer IRQs 162 nhwi, // number of hard IRQs 163 0, // number of soft IRQs 164 nprocs); // number of output IRQs 165 166 std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; 167 168 // dma multi-canaux 169 std::ostringstream sdma; 170 sdma << "dma_" << x_id << "_" << y_id; 171 mdma = new VciMultiDma<vci_param>( 172 sdma.str().c_str(), 173 mtd, 174 IntTab(cluster_id, nprocs), // SRCID 175 IntTab(cluster_id, tgtid_mdma), // TGTID 176 64, // burst size 177 nprocs); // number of IRQs 178 179 std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; 180 181 // direct local crossbar 182 size_t nb_direct_initiators = nprocs + 1; 183 size_t nb_direct_targets = 3; 184 if (io){ 185 nb_direct_initiators = nprocs + 2; 186 nb_direct_targets = 7; 187 } 188 std::ostringstream sd; 189 sd << "xbard_" << x_id << "_" << y_id; 190 xbard = new VciLocalCrossbar<vci_param>( 191 sd.str().c_str(), 192 mtd, 193 IntTab(cluster_id), // cluster initiator index 194 IntTab(cluster_id), // cluster target index 195 nb_direct_initiators, // number of initiators 196 nb_direct_targets); // number of targets 197 198 std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; 199 200 // coherence local crossbar 201 std::ostringstream sc; 202 sc << "xbarc_" << x_id << "_" << y_id; 203 xbarc = new VciLocalCrossbar<vci_param>( 204 sc.str().c_str(), 205 mtc, 206 IntTab(cluster_id), // cluster initiator index 207 IntTab(cluster_id), // cluster target index 208 nprocs + 1, // number of initiators 209 nprocs + 1); // number of targets 210 211 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; 212 213 // direct initiator wrapper 214 std::ostringstream wid; 215 wid << "iniwrapperd_" << x_id << "_" << y_id; 216 iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 217 wid.str().c_str(), 218 4, // cmd fifo depth 219 4); // rsp fifo depth 220 221 // direct target wrapper 222 std::ostringstream wtd; 223 wtd << "tgtwrapperd_" << x_id << "_" << y_id; 224 tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 225 wtd.str().c_str(), 226 4, // cmd fifo depth 227 4); // rsp fifo depth 228 229 // coherence initiator wrapper 230 std::ostringstream wic; 231 wic << "iniwrapperc_" << x_id << "_" << y_id; 232 iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 233 wic.str().c_str(), 234 4, // cmd fifo depth 235 4); // rsp fifo depth 236 237 // coherence target wrapper 238 std::ostringstream wtc; 239 wtc << "tgtwrapperc_" << x_id << "_" << y_id; 240 tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 241 wtc.str().c_str(), 242 4, // cmd fifo depth 243 4); // rsp fifo depth 244 245 std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; 246 247 // CMD router 248 std::ostringstream scmd; 249 scmd << "cmdrouter_" << x_id << "_" << y_id; 250 cmdrouter = new VirtualDspinRouter<cmd_width>( 251 scmd.str().c_str(), 252 x_id,y_id, // coordinate in the mesh 253 x_width, y_width, // x & y fields width 254 4,4); // input & output fifo depths 255 256 std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; 257 258 // RSP router 259 std::ostringstream srsp; 260 srsp << "rsprouter_" << x_id << "_" << y_id; 261 rsprouter = new VirtualDspinRouter<rsp_width>( 262 srsp.str().c_str(), 263 x_id,y_id, // coordinates in mesh 264 x_width, y_width, // x & y fields width 265 4,4); // input & output fifo depths 266 267 // IO cluster components 268 if (io){ 269 brom = new VciSimpleRam<vci_param>( 270 "brom", 271 IntTab(cluster_id, tgtid_brom), 272 mtd, 273 loader); 274 275 fbuf = new VciFrameBuffer<vci_param>( 276 "fbuf", 277 IntTab(cluster_id, tgtid_fbuf), 278 mtd, 279 xfb, yfb); 280 281 bdev = new VciBlockDeviceTsarV4<vci_param>( 282 "bdev", 283 mtd, 284 IntTab(cluster_id, nprocs+1), 285 IntTab(cluster_id, tgtid_bdev), 286 disk_name, 287 block_size); 288 289 mtty = new VciMultiTty<vci_param>( 290 "mtty", 291 IntTab(cluster_id, tgtid_mtty), 292 mtd, 293 "tty0", "tty1", "tty2", "tty3", NULL); 294 } 295 296 std::cout << " - all components constructed" << std::endl; 297 298 //////////////////////////////////// 299 // Connections are defined here 300 //////////////////////////////////// 301 302 // CMDROUTER and RSPROUTER 303 cmdrouter->p_clk (this->p_clk); 304 cmdrouter->p_resetn (this->p_resetn); 305 rsprouter->p_clk (this->p_clk); 306 rsprouter->p_resetn (this->p_resetn); 307 for (int x = 0; x < 2; x++){ 308 for(int y = 0; y < 4; y++){ 309 cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); 310 cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); 311 rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); 312 rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); 313 } 314 } 315 316 cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); 317 cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); 318 cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); 319 cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); 320 321 rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); 322 rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); 323 rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); 324 rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); 325 326 // VCI/DSPIN WRAPPERS 327 iniwrapperd->p_clk (this->p_clk); 328 iniwrapperd->p_resetn (this->p_resetn); 329 iniwrapperd->p_vci (signal_vci_l2g_d); 330 iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); 331 iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); 332 333 tgtwrapperd->p_clk (this->p_clk); 334 tgtwrapperd->p_resetn (this->p_resetn); 335 tgtwrapperd->p_vci (signal_vci_g2l_d); 336 tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); 337 tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); 338 339 iniwrapperc->p_clk (this->p_clk); 340 iniwrapperc->p_resetn (this->p_resetn); 341 iniwrapperc->p_vci (signal_vci_l2g_c); 342 iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); 343 iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); 344 345 tgtwrapperc->p_clk (this->p_clk); 346 tgtwrapperc->p_resetn (this->p_resetn); 347 tgtwrapperc->p_vci (signal_vci_g2l_c); 348 tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); 349 tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); 350 351 // CROSSBAR direct 352 xbard->p_clk (this->p_clk); 353 xbard->p_resetn (this->p_resetn); 354 xbard->p_initiator_to_up (signal_vci_l2g_d); 355 xbard->p_target_to_up (signal_vci_g2l_d); 356 357 xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); 358 xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); 359 xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); 360 361 xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); 362 363 for (size_t p = 0; p < nprocs; p++){ 364 xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); 365 } 366 367 if (io){ 368 xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); 369 xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); 370 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 371 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 372 373 xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); 374 } 375 376 // CROSSBAR coherence 377 xbarc->p_clk (this->p_clk); 378 xbarc->p_resetn (this->p_resetn); 379 xbarc->p_initiator_to_up (signal_vci_l2g_c); 380 xbarc->p_target_to_up (signal_vci_g2l_c); 381 xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); 382 xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); 383 for (size_t p = 0; p < nprocs; p++) { 384 xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); 385 xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); 386 } 387 388 // Processors 389 for (size_t p = 0; p < nprocs; p++){ 390 proc[p]->p_clk (this->p_clk); 391 proc[p]->p_resetn (this->p_resetn); 392 proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); 393 proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); 394 proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); 395 proc[p]->p_irq[0] (signal_proc_it[p]); 396 for ( size_t j = 1 ; j < 6 ; j++){ 397 proc[p]->p_irq[j] (signal_false); 398 } 399 } 400 401 // XICU 402 xicu->p_clk (this->p_clk); 403 xicu->p_resetn (this->p_resetn); 404 xicu->p_vci (signal_vci_tgt_d_xicu); 405 for (size_t p = 0; p < nprocs; p++){ 406 xicu->p_irq[p] (signal_proc_it[p]); 407 } 408 for (size_t p = 0; p < nprocs; p++){ 409 xicu->p_hwi[p] (signal_irq_mdma[p]); 410 } 411 for (size_t x = nprocs; x < 4; x++){ 412 xicu->p_hwi[x] (signal_false); 413 } 414 415 if (io){ 416 xicu->p_hwi[4] (signal_irq_tty0); 417 xicu->p_hwi[5] (signal_irq_tty1); 418 xicu->p_hwi[6] (signal_irq_tty2); 419 xicu->p_hwi[7] (signal_irq_tty3); 420 421 xicu->p_hwi[8] (signal_irq_bdev); 422 } 423 424 // MEMC 425 memc->p_clk (this->p_clk); 426 memc->p_resetn (this->p_resetn); 427 memc->p_vci_ixr (signal_vci_xram); 428 memc->p_vci_tgt (signal_vci_tgt_d_memc); 429 memc->p_vci_ini (signal_vci_ini_c_memc); 430 memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); 431 432 // XRAM 433 xram->p_clk (this->p_clk); 434 xram->p_resetn (this->p_resetn); 435 xram->p_vci (signal_vci_xram); 436 437 // CDMA 438 mdma->p_clk (this->p_clk); 439 mdma->p_resetn (this->p_resetn); 440 mdma->p_vci_target (signal_vci_tgt_d_mdma); 441 mdma->p_vci_initiator (signal_vci_ini_d_mdma); 442 for (size_t p = 0; p < nprocs; p++){ 443 mdma->p_irq[p] (signal_irq_mdma[p]); 444 } 445 446 // Components in IO cluster 447 448 if (io){ 449 // BDEV 450 bdev->p_clk (this->p_clk); 451 bdev->p_resetn (this->p_resetn); 452 bdev->p_irq (signal_irq_bdev); 453 bdev->p_vci_target (signal_vci_tgt_d_bdev); 454 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 455 456 // FBUF 457 fbuf->p_clk (this->p_clk); 458 fbuf->p_resetn (this->p_resetn); 459 fbuf->p_vci (signal_vci_tgt_d_fbuf); 460 461 // BROM 462 brom->p_clk (this->p_clk); 463 brom->p_resetn (this->p_resetn); 464 brom->p_vci (signal_vci_tgt_d_brom); 465 466 // MTTY 467 mtty->p_clk (this->p_clk); 468 mtty->p_resetn (this->p_resetn); 469 mtty->p_vci (signal_vci_tgt_d_mtty); 470 mtty->p_irq[0] (signal_irq_tty0); 471 mtty->p_irq[1] (signal_irq_tty1); 472 mtty->p_irq[2] (signal_irq_tty2); 473 mtty->p_irq[3] (signal_irq_tty3); 474 } 475 } // end constructor 488 476 489 477 /////////////////////////////////////////////////////////////////////////// … … 491 479 /////////////////////////////////////////////////////////////////////////// 492 480 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 493 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {} 494 495 }} 481 TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {} 482 483 } 484 } 485 486 487 // Local Variables: 488 // tab-width: 3 489 // c-basic-offset: 3 490 // c-file-offsets:((innamespace . 0)(inline-open . 0)) 491 // indent-tabs-mode: nil 492 // End: 493 494 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 495 496 497
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