Index: trunk/platforms/tsarv4_generic_mmu/top.cpp
===================================================================
--- trunk/platforms/tsarv4_generic_mmu/top.cpp	(revision 247)
+++ trunk/platforms/tsarv4_generic_mmu/top.cpp	(revision 249)
@@ -55,5 +55,5 @@
 
 ///////////////////////////////////////////////////
-//		OS
+//      OS
 ///////////////////////////////////////////////////
 
@@ -75,21 +75,21 @@
 
 //  cluster index (computed from x,y coordinates)
-#define cluster(x,y)	(y + ymax*x)
+#define cluster(x,y)   (y + ymax*x)
 
 // flit widths for the DSPIN network
-#define cmd_width	         40
-#define rsp_width	         33
+#define cmd_width            40
+#define rsp_width            33
 
 // VCI format
-#define cell_width	         4
-#define address_width	         32
-#define plen_width	         8
-#define error_width	         2
-#define clen_width	         1
-#define rflag_width	         1
-#define srcid_width	         14
-#define pktid_width	         4
-#define trdid_width	         4
-#define wrplen_width	         1
+#define cell_width            4
+#define address_width         32
+#define plen_width            8
+#define error_width           2
+#define clen_width            1
+#define rflag_width           1
+#define srcid_width           14
+#define pktid_width           4
+#define trdid_width           4
+#define wrplen_width          1
 
 ///////////////////////////////////////////////////
@@ -97,8 +97,8 @@
 ///////////////////////////////////////////////////
 
-#define MESH_XMAX		2
-#define MESH_YMAX		2
-
-#define NPROCS			4
+#define MESH_XMAX      2
+#define MESH_YMAX      2
+
+#define NPROCS         4
 #define XRAM_LATENCY            0
 
@@ -115,29 +115,29 @@
 #define FBUF_Y_SIZE             512
 
-#define	BDEV_SECTOR_SIZE 	128
-#define BDEV_IMAGE_NAME	        "../../softs/soft_transpose_giet/images.raw"
-
-#define BOOT_SOFT_NAME	 	"../../softs/soft_transpose_giet/bin.soft"
-
-#define MAX_FROZEN_CYCLES	100000
+#define   BDEV_SECTOR_SIZE    128
+#define BDEV_IMAGE_NAME           "../../softs/soft_transpose_giet/couple_512.raw"
+
+#define BOOT_SOFT_NAME       "../../softs/soft_transpose_giet/bin.soft"
+
+#define MAX_FROZEN_CYCLES   100000
 
 /////////////////////////////////////////////////////////
-// 	Physical segments definition
+//    Physical segments definition
 /////////////////////////////////////////////////////////
 // There is 3 segments replicated in all clusters:
-// - seg_memc   -> MEMC / BASE = 0x**000000 	(12 M bytes)
-// - seg_icu 	-> ICU  / BASE = 0x**F00000
-// - seg_dma 	-> CDMA / BASE = 0x**F30000
+// - seg_memc   -> MEMC / BASE = 0x**000000    (12 M bytes)
+// - seg_icu    -> ICU  / BASE = 0x**F00000
+// - seg_dma    -> CDMA / BASE = 0x**F30000
 //
 // There is 4 specific segments in the "IO" cluster 
 // (containing address 0xBF000000)
-// - seg_reset	-> BROM / BASE = 0xBFC00000	(1 Mbytes)
-// - seg_fbuf	-> FBUF / BASE = 0xBFD00000	(2 M bytes)
-// - seg_bdev	-> BDEV / BASE = 0xBFF10000
-// - seg_tty 	-> MTTY / BASE = 0x**F20000
+// - seg_reset   -> BROM / BASE = 0xBFC00000   (1 Mbytes)
+// - seg_fbuf   -> FBUF / BASE = 0xBFD00000   (2 M bytes)
+// - seg_bdev   -> BDEV / BASE = 0xBFF10000
+// - seg_tty    -> MTTY / BASE = 0x**F20000
 //
 // There is one special segment corresponding to
 // the processors in the coherence address space
-// - seg_proc	-> PROC / BASE = 0x**B0 to 0xBF
+// - seg_proc   -> PROC / BASE = 0x**B0 to 0xBF
 ///////////////////////////////////////////////////
 
@@ -186,355 +186,315 @@
 int _main(int argc, char *argv[])
 {
-    using namespace sc_core;
-    using namespace soclib::caba;
-    using namespace soclib::common;
-    
-    
-    char     soft_name[256] = BOOT_SOFT_NAME;  	  // pathname to binary code
-    size_t   ncycles        = 1000000000;         // simulated cycles
-    size_t   xmax           = MESH_XMAX;  	  // number of clusters in a row
-    size_t   ymax           = MESH_YMAX;          // number of clusters in a column
-    size_t   nprocs         = NPROCS;    	  // number of processors per cluster
-    size_t   xfb            = FBUF_X_SIZE;	  // frameBuffer column number
-    size_t   yfb            = FBUF_Y_SIZE;        // frameBuffer lines number
-    size_t   memc_ways      = MEMC_WAYS;
-    size_t   memc_sets      = MEMC_SETS;
-    size_t   l1_d_ways      = L1_DWAYS;
-    size_t   l1_d_sets      = L1_DSETS;
-    size_t   l1_i_ways      = L1_IWAYS;
-    size_t   l1_i_sets      = L1_ISETS;
-    char     disk_name[256] = BDEV_IMAGE_NAME;    // pathname to the disk image
-    size_t   blk_size       = BDEV_SECTOR_SIZE;   // block size (in bytes)
-    size_t   xram_latency   = XRAM_LATENCY;	  // external RAM latency
-    bool     trace_ok       = false;              // trace activated
-    size_t   trace_period   = 1;                  // trace period
-    uint32_t from_cycle     = 0;                  // debug start cycle
-    uint32_t frozen_cycles  = MAX_FROZEN_CYCLES;  // monitoring frozen processor
-
-    ////////////// command line arguments //////////////////////
-    if (argc > 1)
-    {
-        for( int n=1 ; n<argc ; n=n+2 )
-        {
-            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
-            {
-                ncycles = atoi(argv[n+1]);
-            }
-            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
-            {
-                nprocs = atoi(argv[n+1]);
-                assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) &&
-                        "NPROCS must be equal to 1, 2, or 4");
-            }
-            else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
-            {
-                xmax = atoi(argv[n+1]);
-                assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) 
-                         && "The XMAX parameter must be 2, 4, 8, or 16" );
-            }
-            
-	    else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
-            {
-                ymax = atoi(argv[n+1]);
-                assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) 
-                         && "The YMAX parameter must be 2, 4, 8, or 16" );
-            }
-	    else if( (strcmp(argv[n],"-XFB") == 0) && (n+1<argc) )
-            {
-	        xfb = atoi(argv[n+1]);
-            }
-	    else if( (strcmp(argv[n],"-YFB") == 0) && (n+1<argc) )
-            {
-                yfb = atoi(argv[n+1]);
-            }
-            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
-            {
-                strcpy(soft_name, argv[n+1]);
-            }
-            else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
-            {
-                strcpy(disk_name, argv[n+1]);
-            }
-            else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
-            {
-                trace_ok = true;
-                from_cycle = atoi(argv[n+1]);
-            }
-	    else if((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc))
-	    {
-	        memc_ways = atoi(argv[n+1]);
-	    }
-	    else if((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc))
-	    {
-	        memc_sets = atoi(argv[n+1]);
-	    }
-	    else if((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc))
-	    {
-	        xram_latency = atoi(argv[n+1]);
-	    }
-	    else if((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
-	    {
-	        frozen_cycles = atoi(argv[n+1]);
-	    }
-	    else if((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
-	    {
-	        trace_period = atoi(argv[n+1]);
-	    }
-            else
-            {
-                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
-                std::cout << "   The order is not important." << std::endl;
-                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
-                std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
-                std::cout << "     -DISK pathname_for_disk_image" << std::endl;
-                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
-                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
-                std::cout << "     -XMAX number_of_clusters_in_a_row" << std::endl;
-                std::cout << "     -YMAX number_of_clusters_in_a_column" << std::endl;
-                std::cout << "     -TRACE debug_start_cycle" << std::endl;
-                std::cout << "     -MCWAYS memory_cache_number_of_ways" << std::endl;
-                std::cout << "     -MCSETS memory_cache_number_of_sets" << std::endl;
-                std::cout << "     -XLATENCY external_ram_latency_value" << std::endl;
-                std::cout << "     -XFB fram_buffer_number_of_pixels" << std::endl;
-                std::cout << "     -YFB fram_buffer_number_of_lines" << std::endl;
-                std::cout << "     -FROZEN max_number_of_lines" << std::endl;
-                std::cout << "     -PERIOD number_of_cycles between trace" << std::endl;
-                exit(0);
-            }
-        }
-    }
-
-    std::cout << std::endl;
-    std::cout << " - NPROCS      = " << nprocs <<  std::endl;
-    std::cout << " - NCLUSTERS   = " << xmax*ymax << std::endl;
-    std::cout << " - MAX FROZEN  = " << frozen_cycles << std::endl;
-    std::cout << " - MEMC_WAYS   = " << memc_ways << std::endl;
-    std::cout << " - MEMC_SETS   = " << memc_sets << std::endl;
-    std::cout << " - RAM_LATENCY = " << xram_latency << std::endl;
-
-    std::cout << std::endl;
+   using namespace sc_core;
+   using namespace soclib::caba;
+   using namespace soclib::common;
+
+
+   char     soft_name[256] = BOOT_SOFT_NAME;       // pathname to binary code
+   size_t   ncycles        = 1000000000;         // simulated cycles
+   size_t   xmax           = MESH_XMAX;       // number of clusters in a row
+   size_t   ymax           = MESH_YMAX;          // number of clusters in a column
+   size_t   nprocs         = NPROCS;         // number of processors per cluster
+   size_t   xfb            = FBUF_X_SIZE;     // frameBuffer column number
+   size_t   yfb            = FBUF_Y_SIZE;        // frameBuffer lines number
+   size_t   memc_ways      = MEMC_WAYS;
+   size_t   memc_sets      = MEMC_SETS;
+   size_t   l1_d_ways      = L1_DWAYS;
+   size_t   l1_d_sets      = L1_DSETS;
+   size_t   l1_i_ways      = L1_IWAYS;
+   size_t   l1_i_sets      = L1_ISETS;
+   char     disk_name[256] = BDEV_IMAGE_NAME;    // pathname to the disk image
+   size_t   blk_size       = BDEV_SECTOR_SIZE;   // block size (in bytes)
+   size_t   xram_latency   = XRAM_LATENCY;     // external RAM latency
+   bool     trace_ok       = false;              // trace activated
+   size_t   trace_period   = 1;                  // trace period
+   uint32_t from_cycle     = 0;                  // debug start cycle
+   uint32_t frozen_cycles  = MAX_FROZEN_CYCLES;  // monitoring frozen processor
+
+   ////////////// command line arguments //////////////////////
+   if (argc > 1){
+      for (int n = 1; n < argc; n = n + 2){
+         if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)){
+            ncycles = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc)){
+            nprocs = atoi(argv[n+1]);
+            assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) &&
+                  "NPROCS must be equal to 1, 2, or 4");
+         }
+         else if ((strcmp(argv[n],"-XMAX") == 0) && (n+1<argc)){
+            xmax = atoi(argv[n+1]);
+            assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) 
+                  && "The XMAX parameter must be 2, 4, 8, or 16" );
+         }
+
+         else if ((strcmp(argv[n],"-YMAX") == 0) && (n+1<argc)){
+            ymax = atoi(argv[n+1]);
+            assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) 
+                  && "The YMAX parameter must be 2, 4, 8, or 16" );
+         }
+         else if ((strcmp(argv[n],"-XFB") == 0) && (n+1<argc)){
+            xfb = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-YFB") == 0) && (n+1<argc) ){
+            yfb = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ){
+            strcpy(soft_name, argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ){
+            strcpy(disk_name, argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) ){
+            trace_ok = true;
+            from_cycle = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc)){
+            memc_ways = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc)){
+            memc_sets = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc)){
+            xram_latency = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)){
+            frozen_cycles = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)){
+            trace_period = atoi(argv[n+1]);
+         }
+         else
+         {
+            std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+            std::cout << "   The order is not important." << std::endl;
+            std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+            std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+            std::cout << "     -DISK pathname_for_disk_image" << std::endl;
+            std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+            std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+            std::cout << "     -XMAX number_of_clusters_in_a_row" << std::endl;
+            std::cout << "     -YMAX number_of_clusters_in_a_column" << std::endl;
+            std::cout << "     -TRACE debug_start_cycle" << std::endl;
+            std::cout << "     -MCWAYS memory_cache_number_of_ways" << std::endl;
+            std::cout << "     -MCSETS memory_cache_number_of_sets" << std::endl;
+            std::cout << "     -XLATENCY external_ram_latency_value" << std::endl;
+            std::cout << "     -XFB fram_buffer_number_of_pixels" << std::endl;
+            std::cout << "     -YFB fram_buffer_number_of_lines" << std::endl;
+            std::cout << "     -FROZEN max_number_of_lines" << std::endl;
+            std::cout << "     -PERIOD number_of_cycles between trace" << std::endl;
+            exit(0);
+         }
+      }
+   }
+
+   std::cout << std::endl;
+   std::cout << " - NPROCS      = " << nprocs <<  std::endl;
+   std::cout << " - NCLUSTERS   = " << xmax*ymax << std::endl;
+   std::cout << " - MAX FROZEN  = " << frozen_cycles << std::endl;
+   std::cout << " - MEMC_WAYS   = " << memc_ways << std::endl;
+   std::cout << " - MEMC_SETS   = " << memc_sets << std::endl;
+   std::cout << " - RAM_LATENCY = " << xram_latency << std::endl;
+
+   std::cout << std::endl;
 
 #if USE_OPENMP
-        omp_set_dynamic(false);
-        omp_set_num_threads(threads_nr);
-        std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+   omp_set_dynamic(false);
+   omp_set_num_threads(threads_nr);
+   std::cerr << "Built with openmp version " << _OPENMP << std::endl;
 #endif
 
-    // Define VCI parameters
-    typedef soclib::caba::VciParams<cell_width,
-                                    plen_width,
-                                    address_width,
-                                    error_width,                                   
-                                    clen_width,
-                                    rflag_width,
-                                    srcid_width,
-                                    pktid_width,
-                                    trdid_width,
-                                    wrplen_width> vci_param;
-
-    size_t	cluster_io_index;
-    size_t	x_width;
-    size_t	y_width;
-
-    if      (xmax == 1) x_width = 0;
-    else if (xmax == 2) x_width = 1;
-    else if (xmax <= 4) x_width = 2;
-    else if (xmax <= 8) x_width = 3;
-    else                x_width = 4;
-
-    if      (ymax == 1) y_width = 0;
-    else if (ymax == 2) y_width = 1;
-    else if (ymax <= 4) y_width = 2;
-    else if (ymax <= 8) y_width = 3;
-    else                y_width = 4;
-
-    cluster_io_index = 0xBF >> (8 - x_width - y_width);
-    
-    /////////////////////
-    //  Mapping Tables
-    /////////////////////
-
-    // direct network
-    MappingTable maptabd(address_width, 
-                         IntTab(x_width + y_width, 16 - x_width - y_width), 
-                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
-                         0x00FF0000);
-
-    for ( size_t x = 0 ; x < xmax ; x++)
-    {
-        for ( size_t y = 0 ; y < ymax ; y++)
-        {
-            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
-
-            std::ostringstream 	sh;
-            sh << "d_seg_memc_" << x << "_" << y;
-            maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
-
-            std::ostringstream 	si;
-            si << "d_seg_xicu_" << x << "_" << y;
-            maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
-
-            std::ostringstream 	sd;
-            sd << "d_seg_mdma_" << x << "_" << y;
-            maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
-
-            if ( cluster(x,y) == cluster_io_index )
-            {
-	      maptabd.add(Segment("d_seg_mtty    ", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
-	      maptabd.add(Segment("d_seg_fbuf    ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
-	      maptabd.add(Segment("d_seg_bdev    ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
-	      maptabd.add(Segment("d_seg_brom    ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
-            }
-        }
-    }
-    std::cout << maptabd << std::endl;
-
-    // coherence network
-    // - tgtid_c_proc = srcid_c_proc = local procid
-    // - tgtid_c_memc = srcid_c_memc = nprocs
-    MappingTable maptabc(address_width, 
-                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
-                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
-                         0x00FF0000);
-
-    for ( size_t x = 0 ; x < xmax ; x++)
-    {
-        for ( size_t y = 0 ; y < ymax ; y++)
-        {
-            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
-
-            // cleanup requests regarding the memc segment must be routed to the memory cache
-            std::ostringstream sh;
-            sh << "c_seg_memc_" << x << "_" << y;
-            maptabc.add(
-                Segment(
-                    sh.str()
-                  , (nprocs << (address_width - srcid_width)) + offset
-                  , 0x10
-                  , IntTab(cluster(x,y), nprocs)
-                  , false
-                )
-            );
-
-            // update & invalidate requests must be routed to the proper processor
-	    for ( size_t p = 0 ; p < nprocs ; p++)
-            {
-                std::ostringstream sp;
-	        sp << "c_seg_proc_" << x << "_" << y << "_" << p;
-	        maptabc.add(
-                    Segment(
-                        sp.str()
-                      , (p << (address_width - srcid_width)) + offset
-                      , 0x10
-                      , IntTab(cluster(x,y), p)
-                      , false
-                    )
-                ); 
-            }
-        }
-    }
-    std::cout << maptabc << std::endl;
-
-    // external network
-    MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
-
-    for ( size_t x = 0 ; x < xmax ; x++)
-    {
-        for ( size_t y = 0 ; y < ymax ; y++)
-        { 
-            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
-            std::ostringstream sh;
-            sh << "x_seg_memc_" << x << "_" << y;
-            maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false));
-        }
-    }
-    std::cout << maptabx << std::endl;
-
-    ////////////////////
-    // Signals
-    ///////////////////
-
-    sc_clock		signal_clk("clk");
-    sc_signal<bool> 	signal_resetn("resetn");
-
-    // Horizontal inter-clusters DSPIN signals
-    DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
+   // Define VCI parameters
+   typedef soclib::caba::VciParams<cell_width,
+           plen_width,
+           address_width,
+           error_width,                                   
+           clen_width,
+           rflag_width,
+           srcid_width,
+           pktid_width,
+           trdid_width,
+           wrplen_width> vci_param;
+
+   size_t   cluster_io_index;
+   size_t   x_width;
+   size_t   y_width;
+
+   if      (xmax == 1) x_width = 0;
+   else if (xmax == 2) x_width = 1;
+   else if (xmax <= 4) x_width = 2;
+   else if (xmax <= 8) x_width = 3;
+   else                x_width = 4;
+
+   if      (ymax == 1) y_width = 0;
+   else if (ymax == 2) y_width = 1;
+   else if (ymax <= 4) y_width = 2;
+   else if (ymax <= 8) y_width = 3;
+   else                y_width = 4;
+
+   cluster_io_index = 0xBF >> (8 - x_width - y_width);
+
+   /////////////////////
+   //  Mapping Tables
+   /////////////////////
+
+   // direct network
+   MappingTable maptabd(address_width, 
+         IntTab(x_width + y_width, 16 - x_width - y_width), 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         0x00FF0000);
+
+   for (size_t x = 0; x < xmax; x++){
+      for (size_t y = 0; y < ymax; y++){
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+         std::ostringstream    sh;
+         sh << "d_seg_memc_" << x << "_" << y;
+         maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+
+         std::ostringstream    si;
+         si << "d_seg_xicu_" << x << "_" << y;
+         maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
+
+         std::ostringstream    sd;
+         sd << "d_seg_mdma_" << x << "_" << y;
+         maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
+
+         if ( cluster(x,y) == cluster_io_index )
+         {
+            maptabd.add(Segment("d_seg_mtty    ", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
+            maptabd.add(Segment("d_seg_fbuf    ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
+            maptabd.add(Segment("d_seg_bdev    ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
+            maptabd.add(Segment("d_seg_brom    ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
+         }
+      }
+   }
+   std::cout << maptabd << std::endl;
+
+   // coherence network
+   // - tgtid_c_proc = srcid_c_proc = local procid
+   // - tgtid_c_memc = srcid_c_memc = nprocs
+   MappingTable maptabc(address_width, 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         0x00FF0000);
+
+   for (size_t x = 0; x < xmax; x++){
+      for (size_t y = 0; y < ymax; y++){
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+         // cleanup requests regarding the memc segment must be routed to the memory cache
+         std::ostringstream sh;
+         sh << "c_seg_memc_" << x << "_" << y;
+         maptabc.add(Segment(sh.str(), (nprocs << (address_width - srcid_width)) + offset, 0x10, IntTab(cluster(x,y), nprocs), false));
+
+         // update & invalidate requests must be routed to the proper processor
+         for ( size_t p = 0 ; p < nprocs ; p++) {
+            std::ostringstream sp;
+            sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+            maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 0x10 , IntTab(cluster(x,y), p) , false)); 
+         }
+      }
+   }
+   std::cout << maptabc << std::endl;
+
+   // external network
+   MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
+
+   for (size_t x = 0; x < xmax; x++){
+      for (size_t y = 0; y < ymax ; y++){ 
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+         std::ostringstream sh;
+         sh << "x_seg_memc_" << x << "_" << y;
+         maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false));
+      }
+   }
+   std::cout << maptabx << std::endl;
+
+   ////////////////////
+   // Signals
+   ///////////////////
+
+   sc_clock      signal_clk("clk");
+   sc_signal<bool>    signal_resetn("resetn");
+
+   // Horizontal inter-clusters DSPIN signals
+   DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
       alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2);
-    DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
+   DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
       alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2);
-    DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
+   DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
       alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2);
-    DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
+   DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
       alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2);
 
-    // Vertical inter-clusters DSPIN signals
-    DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
-        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);
-    DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
-        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);
-    DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
-        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);
-    DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
-        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);
-
-    // Mesh boundaries DSPIN signals
-    DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
-        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4);
-    DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
-        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4);
-    DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
-        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4);
-    DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
-        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4);
-
-
-    ////////////////////////////
-    //      Components
-    ////////////////////////////
+   // Vertical inter-clusters DSPIN signals
+   DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);
+   DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);
+   DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);
+   DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);
+
+   // Mesh boundaries DSPIN signals
+   DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4);
+   DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4);
+   DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4);
+   DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4);
+
+
+   ////////////////////////////
+   //      Components
+   ////////////////////////////
 
 #if USE_ALMOS
-    soclib::common::Loader loader(almos_bootloader_pathname,
-				  almos_archinfo_pathname,
-				  almos_kernel_pathname);
+   soclib::common::Loader loader(almos_bootloader_pathname,
+         almos_archinfo_pathname,
+         almos_kernel_pathname);
 #else
-    soclib::common::Loader loader(soft_name);
+   soclib::common::Loader loader(soft_name);
 #endif
 
-    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
-    proc_iss::set_loader(loader);
-
-    TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax];
+   typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+   proc_iss::set_loader(loader);
+
+   TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax];
 
 #if USE_OPENMP
 
 #pragma omp parallel
-{
+   {
 #pragma omp for
-    for( size_t i = 0 ; i  < (xmax * ymax); i++)
-    {
-        size_t x = i / ymax;
-        size_t y = i % ymax;
+      for(size_t i = 0; i  < (xmax * ymax); i++){
+         size_t x = i / ymax;
+         size_t y = i % ymax;
 
 #pragma omp critical
-	std::ostringstream sc;
-	sc << "cluster_" << x << "_" << y;
-	clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>
-	    (sc.str().c_str(),
+         std::ostringstream sc;
+         sc << "cluster_" << x << "_" << y;
+         clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>
+            (sc.str().c_str(),
              nprocs,
-	     x,
-	     y,
-	     cluster(x,y),
-	     maptabd,
-	     maptabc,
-	     maptabx,
-	     x_width,
-	     y_width,
-	     MEMC_TGTID,
-	     XICU_TGTID,
-	     FBUF_TGTID,
-	     MTTY_TGTID,
-	     BROM_TGTID,
-	     BDEV_TGTID,
-	     CDMA_TGTID,
+             x,
+             y,
+             cluster(x,y),
+             maptabd,
+             maptabc,
+             maptabx,
+             x_width,
+             y_width,
+             MEMC_TGTID,
+             XICU_TGTID,
+             FBUF_TGTID,
+             MTTY_TGTID,
+             BROM_TGTID,
+             BDEV_TGTID,
+             CDMA_TGTID,
              memc_ways,
              memc_sets,
@@ -544,44 +504,43 @@
              l1_d_sets,
              xram_latency,
-	     (cluster(x,y) == cluster_io_index),
-	     xfb,
-	     yfb,
-	     disk_name,
-	     blk_size,
-	     loader,
+             (cluster(x,y) == cluster_io_index),
+             xfb,
+             yfb,
+             disk_name,
+             blk_size,
+             loader,
              frozen_cycles,
              from_cycle,
              trace_ok and (cluster_io_index == cluster(x,y)) );
-	}
+      }
+   }
 
 #else  // NO OPENMP
 
-    for( size_t x = 0 ; x  < xmax ; x++)
-    {
-        for( size_t y = 0 ; y < ymax ; y++ )
-        {
-
-std::cout << "building cluster_" << x << "_" << y << std::endl;
-
-	    std::ostringstream sc;
-	    sc << "cluster_" << x << "_" << y;
-	    clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>
-	    (sc.str().c_str(),
+   for (size_t x = 0; x  < xmax; x++){
+      for (size_t y = 0; y < ymax; y++){
+
+         std::cout << "building cluster_" << x << "_" << y << std::endl;
+
+         std::ostringstream sc;
+         sc << "cluster_" << x << "_" << y;
+         clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>
+            (sc.str().c_str(),
              nprocs,
-	     x,
-	     y,
-	     cluster(x,y),
-	     maptabd,
-	     maptabc,
-	     maptabx,
-	     x_width,
-	     y_width,
-	     MEMC_TGTID,
-	     XICU_TGTID,
-	     FBUF_TGTID,
-	     MTTY_TGTID,
-	     BROM_TGTID,
-	     BDEV_TGTID,
-	     CDMA_TGTID,
+             x,
+             y,
+             cluster(x,y),
+             maptabd,
+             maptabc,
+             maptabx,
+             x_width,
+             y_width,
+             MEMC_TGTID,
+             XICU_TGTID,
+             FBUF_TGTID,
+             MTTY_TGTID,
+             BROM_TGTID,
+             BDEV_TGTID,
+             CDMA_TGTID,
              memc_ways,
              memc_sets,
@@ -591,222 +550,216 @@
              l1_d_sets,
              xram_latency,
-	     (cluster(x,y) == cluster_io_index),
-	     xfb,
-	     yfb,
-	     disk_name,
-	     blk_size,
-	     loader,
+             (cluster(x,y) == cluster_io_index),
+             xfb,
+             yfb,
+             disk_name,
+             blk_size,
+             loader,
              frozen_cycles,
              from_cycle,
              trace_ok and (cluster_io_index == cluster(x,y)) );
 
-std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
-
-	}
-    }
-    
-#endif	// USE_OPENMP
-
-    ///////////////////////////////////////////////////////////////
-    //     Net-list 
-    ///////////////////////////////////////////////////////////////
-
-    // Clock & RESET
-    for ( size_t x = 0 ; x < (xmax) ; x++ )
-    {
-        for ( size_t y = 0 ; y < ymax ; y++ )
-        {
-            clusters[x][y]->p_clk			(signal_clk);
-            clusters[x][y]->p_resetn			(signal_resetn);
-        }
-    }
-
-    // Inter Clusters horizontal connections
-    if ( xmax > 1 )
-    {
-        for ( size_t x = 0 ; x < (xmax-1) ; x++ )
-        {
-            for ( size_t y = 0 ; y < ymax ; y++ )
-            {
-                for ( size_t k = 0 ; k < 2 ; k++ )
-                {
-		clusters[x][y]->p_cmd_out[k][EAST]      (signal_dspin_h_cmd_inc[x][y][k]);
-                clusters[x+1][y]->p_cmd_in[k][WEST]     (signal_dspin_h_cmd_inc[x][y][k]);
-                clusters[x][y]->p_cmd_in[k][EAST]       (signal_dspin_h_cmd_dec[x][y][k]);
-                clusters[x+1][y]->p_cmd_out[k][WEST]    (signal_dspin_h_cmd_dec[x][y][k]);
-                clusters[x][y]->p_rsp_out[k][EAST]      (signal_dspin_h_rsp_inc[x][y][k]);
-                clusters[x+1][y]->p_rsp_in[k][WEST]     (signal_dspin_h_rsp_inc[x][y][k]);
-                clusters[x][y]->p_rsp_in[k][EAST]       (signal_dspin_h_rsp_dec[x][y][k]);
-                clusters[x+1][y]->p_rsp_out[k][WEST]    (signal_dspin_h_rsp_dec[x][y][k]);
-                }
+         std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
+
+      }
+   }
+
+#endif   // USE_OPENMP
+
+   ///////////////////////////////////////////////////////////////
+   //     Net-list 
+   ///////////////////////////////////////////////////////////////
+
+   // Clock & RESET
+   for (size_t x = 0; x < (xmax); x++){
+      for (size_t y = 0; y < ymax; y++){
+         clusters[x][y]->p_clk     (signal_clk);
+         clusters[x][y]->p_resetn  (signal_resetn);
+      }
+   }
+
+   // Inter Clusters horizontal connections
+   if (xmax > 1){
+      for (size_t x = 0; x < (xmax-1); x++){
+         for (size_t y = 0; y < ymax; y++){
+            for (size_t k = 0; k < 2; k++){
+               clusters[x][y]->p_cmd_out[k][EAST]      (signal_dspin_h_cmd_inc[x][y][k]);
+               clusters[x+1][y]->p_cmd_in[k][WEST]     (signal_dspin_h_cmd_inc[x][y][k]);
+               clusters[x][y]->p_cmd_in[k][EAST]       (signal_dspin_h_cmd_dec[x][y][k]);
+               clusters[x+1][y]->p_cmd_out[k][WEST]    (signal_dspin_h_cmd_dec[x][y][k]);
+               clusters[x][y]->p_rsp_out[k][EAST]      (signal_dspin_h_rsp_inc[x][y][k]);
+               clusters[x+1][y]->p_rsp_in[k][WEST]     (signal_dspin_h_rsp_inc[x][y][k]);
+               clusters[x][y]->p_rsp_in[k][EAST]       (signal_dspin_h_rsp_dec[x][y][k]);
+               clusters[x+1][y]->p_rsp_out[k][WEST]    (signal_dspin_h_rsp_dec[x][y][k]);
             }
-        }
-    }
-    std::cout << "Horizontal connections established" << std::endl;	
-
-    // Inter Clusters vertical connections
-    if ( ymax > 1 )
-    {
-        for ( size_t y = 0 ; y < (ymax-1) ; y++ )
-        {
-            for ( size_t x = 0 ; x < xmax ; x++ )
-            {
-                for ( size_t k = 0 ; k < 2 ; k++ )
-                {
-                clusters[x][y]->p_cmd_out[k][NORTH]     (signal_dspin_v_cmd_inc[x][y][k]);
-                clusters[x][y+1]->p_cmd_in[k][SOUTH]    (signal_dspin_v_cmd_inc[x][y][k]);
-                clusters[x][y]->p_cmd_in[k][NORTH]      (signal_dspin_v_cmd_dec[x][y][k]);
-                clusters[x][y+1]->p_cmd_out[k][SOUTH]   (signal_dspin_v_cmd_dec[x][y][k]);
-                clusters[x][y]->p_rsp_out[k][NORTH]     (signal_dspin_v_rsp_inc[x][y][k]);
-                clusters[x][y+1]->p_rsp_in[k][SOUTH]    (signal_dspin_v_rsp_inc[x][y][k]);
-                clusters[x][y]->p_rsp_in[k][NORTH]      (signal_dspin_v_rsp_dec[x][y][k]);
-                clusters[x][y+1]->p_rsp_out[k][SOUTH]   (signal_dspin_v_rsp_dec[x][y][k]);
-                }
+         }
+      }
+   }
+   std::cout << "Horizontal connections established" << std::endl;   
+
+   // Inter Clusters vertical connections
+   if (ymax > 1) {
+      for (size_t y = 0; y < (ymax-1); y++){
+         for (size_t x = 0; x < xmax; x++){
+            for (size_t k = 0; k < 2; k++){
+               clusters[x][y]->p_cmd_out[k][NORTH]     (signal_dspin_v_cmd_inc[x][y][k]);
+               clusters[x][y+1]->p_cmd_in[k][SOUTH]    (signal_dspin_v_cmd_inc[x][y][k]);
+               clusters[x][y]->p_cmd_in[k][NORTH]      (signal_dspin_v_cmd_dec[x][y][k]);
+               clusters[x][y+1]->p_cmd_out[k][SOUTH]   (signal_dspin_v_cmd_dec[x][y][k]);
+               clusters[x][y]->p_rsp_out[k][NORTH]     (signal_dspin_v_rsp_inc[x][y][k]);
+               clusters[x][y+1]->p_rsp_in[k][SOUTH]    (signal_dspin_v_rsp_inc[x][y][k]);
+               clusters[x][y]->p_rsp_in[k][NORTH]      (signal_dspin_v_rsp_dec[x][y][k]);
+               clusters[x][y+1]->p_rsp_out[k][SOUTH]   (signal_dspin_v_rsp_dec[x][y][k]);
             }
-        }
-    }
-    std::cout << "Vertical connections established" << std::endl;
-
-    // East & West boundary cluster connections
-    for ( size_t y = 0 ; y < ymax ; y++ )
-    {
-        for ( size_t k = 0 ; k < 2 ; k++ )
-        {
-	    clusters[0][y]->p_cmd_in[k][WEST]       	(signal_dspin_false_cmd_in[0][y][k][WEST]);
-	    clusters[0][y]->p_cmd_out[k][WEST]      	(signal_dspin_false_cmd_out[0][y][k][WEST]);
-	    clusters[0][y]->p_rsp_in[k][WEST]       	(signal_dspin_false_rsp_in[0][y][k][WEST]);
-	    clusters[0][y]->p_rsp_out[k][WEST]      	(signal_dspin_false_rsp_out[0][y][k][WEST]);
-	  
-	    clusters[xmax-1][y]->p_cmd_in[k][EAST]  	(signal_dspin_false_cmd_in[xmax-1][y][k][EAST]);
-	    clusters[xmax-1][y]->p_cmd_out[k][EAST] 	(signal_dspin_false_cmd_out[xmax-1][y][k][EAST]);
-	    clusters[xmax-1][y]->p_rsp_in[k][EAST]  	(signal_dspin_false_rsp_in[xmax-1][y][k][EAST]);
-	    clusters[xmax-1][y]->p_rsp_out[k][EAST] 	(signal_dspin_false_rsp_out[xmax-1][y][k][EAST]);
-	}
-    }
-    
-    // North & South boundary clusters connections
-    for ( size_t x = 0 ; x < xmax ; x++ )
-    {
-        for ( size_t k = 0 ; k < 2 ; k++ )
-        {
-	    clusters[x][0]->p_cmd_in[k][SOUTH]      	(signal_dspin_false_cmd_in[x][0][k][SOUTH]);
-	    clusters[x][0]->p_cmd_out[k][SOUTH]     	(signal_dspin_false_cmd_out[x][0][k][SOUTH]);
-	    clusters[x][0]->p_rsp_in[k][SOUTH]      	(signal_dspin_false_rsp_in[x][0][k][SOUTH]);
-	    clusters[x][0]->p_rsp_out[k][SOUTH]     	(signal_dspin_false_rsp_out[x][0][k][SOUTH]);
-	    
-	    clusters[x][ymax-1]->p_cmd_in[k][NORTH] 	(signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]);
-	    clusters[x][ymax-1]->p_cmd_out[k][NORTH]	(signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]);
-	    clusters[x][ymax-1]->p_rsp_in[k][NORTH] 	(signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]);
-	    clusters[x][ymax-1]->p_rsp_out[k][NORTH]	(signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]);
-	}
-    }
-      
-
-    ////////////////////////////////////////////////////////
-    //   Simulation
-    ///////////////////////////////////////////////////////
-
-    sc_start(sc_core::sc_time(0, SC_NS));
-    signal_resetn = false;
-
-    // network boundaries signals
-    for(size_t x=0; x<xmax ; x++)
-    {
-        for(size_t y=0 ; y<ymax ; y++)
-        {
-            for (size_t k=0; k<2; k++)
-            {
-                for(size_t a=0; a<4; a++)
-                {
-		        signal_dspin_false_cmd_in[x][y][k][a].write = false;
-		        signal_dspin_false_cmd_in[x][y][k][a].read = true;
-                        signal_dspin_false_cmd_out[x][y][k][a].write = false;
-                        signal_dspin_false_cmd_out[x][y][k][a].read = true;
-
-                        signal_dspin_false_rsp_in[x][y][k][a].write = false;
-                        signal_dspin_false_rsp_in[x][y][k][a].read = true;
-                        signal_dspin_false_rsp_out[x][y][k][a].write = false;
-                        signal_dspin_false_rsp_out[x][y][k][a].read = true;
-		}
+         }
+      }
+   }
+   std::cout << "Vertical connections established" << std::endl;
+
+   // East & West boundary cluster connections
+   for (size_t y = 0; y < ymax; y++){
+      for (size_t k = 0; k < 2; k++){
+         clusters[0][y]->p_cmd_in[k][WEST]          (signal_dspin_false_cmd_in[0][y][k][WEST]);
+         clusters[0][y]->p_cmd_out[k][WEST]         (signal_dspin_false_cmd_out[0][y][k][WEST]);
+         clusters[0][y]->p_rsp_in[k][WEST]          (signal_dspin_false_rsp_in[0][y][k][WEST]);
+         clusters[0][y]->p_rsp_out[k][WEST]         (signal_dspin_false_rsp_out[0][y][k][WEST]);
+
+         clusters[xmax-1][y]->p_cmd_in[k][EAST]     (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]);
+         clusters[xmax-1][y]->p_cmd_out[k][EAST]    (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]);
+         clusters[xmax-1][y]->p_rsp_in[k][EAST]     (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]);
+         clusters[xmax-1][y]->p_rsp_out[k][EAST]    (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]);
+      }
+   }
+
+   // North & South boundary clusters connections
+   for (size_t x = 0; x < xmax; x++){
+      for (size_t k = 0; k < 2; k++){
+         clusters[x][0]->p_cmd_in[k][SOUTH]         (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
+         clusters[x][0]->p_cmd_out[k][SOUTH]        (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
+         clusters[x][0]->p_rsp_in[k][SOUTH]         (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
+         clusters[x][0]->p_rsp_out[k][SOUTH]        (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
+
+         clusters[x][ymax-1]->p_cmd_in[k][NORTH]    (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]);
+         clusters[x][ymax-1]->p_cmd_out[k][NORTH]   (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]);
+         clusters[x][ymax-1]->p_rsp_in[k][NORTH]    (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]);
+         clusters[x][ymax-1]->p_rsp_out[k][NORTH]   (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]);
+      }
+   }
+
+
+   ////////////////////////////////////////////////////////
+   //   Simulation
+   ///////////////////////////////////////////////////////
+
+   sc_start(sc_core::sc_time(0, SC_NS));
+   signal_resetn = false;
+
+   // network boundaries signals
+   for (size_t x = 0; x < xmax ; x++){
+      for (size_t y = 0; y < ymax ; y++){
+         for (size_t k = 0; k < 2; k++){
+            for (size_t a = 0; a < 4; a++){
+               signal_dspin_false_cmd_in[x][y][k][a].write = false;
+               signal_dspin_false_cmd_in[x][y][k][a].read = true;
+               signal_dspin_false_cmd_out[x][y][k][a].write = false;
+               signal_dspin_false_cmd_out[x][y][k][a].read = true;
+
+               signal_dspin_false_rsp_in[x][y][k][a].write = false;
+               signal_dspin_false_rsp_in[x][y][k][a].read = true;
+               signal_dspin_false_rsp_out[x][y][k][a].write = false;
+               signal_dspin_false_rsp_out[x][y][k][a].read = true;
             }
-        }
-    }
-
-    sc_start(sc_core::sc_time(1, SC_NS));
-    signal_resetn = true;
-
-    for ( size_t n=1 ; n<ncycles ; n++)
-    {
-        if ( trace_ok and (n > from_cycle) and (n%trace_period == 0) )
-        {
-            std::cout << "****************** cycle " << std::dec << n ;
-            std::cout << " ************************************************" << std::endl;
-
-            // components cluster 00 /////////////////////
-//            clusters[0][0]->proc[0]->print_trace();
-//            clusters[0][0]->memc->print_trace();
-
-            // signals cluster 00 ////////////////////////
-//            clusters[0][0]->signal_vci_ini_d_proc[0].print_trace("proc_0_0_0_ini_d");
-//            clusters[0][0]->signal_vci_ini_c_proc[0].print_trace("proc_0_0_0_ini_c");
-//            clusters[0][0]->signal_vci_tgt_c_proc[0].print_trace("proc_0_0_0_tgt_c");
-//            clusters[0][0]->signal_vci_xram.print_trace("memc_0_0_xram");
-
-            // components cluster 01 /////////////////////
-//            clusters[0][1]->proc[0]->print_trace();
-//            clusters[0][1]->memc->print_trace();
-
-            // signals cluster 01 ///////////////////////
-//            clusters[0][1]->signal_vci_ini_d_proc[0].print_trace("proc_0_1_0_ini_d");
-//            clusters[0][1]->signal_vci_ini_c_proc[0].print_trace("proc_0_1_0_ini_c");
-//            clusters[0][1]->signal_vci_tgt_c_proc[0].print_trace("proc_0_1_0_tgt_c");
-//            clusters[0][1]->signal_vci_xram.print_trace("memc_0_1_xram");
-
-            // components cluster 10 ////////////////////
-            clusters[1][0]->proc[0]->print_trace(1);
-            clusters[1][0]->memc->print_trace();
-//            clusters[1][0]->bdev->print_trace();
-//            clusters[1][0]->mdma->print_trace();
-
-            // signals cluster 10 ///////////////////////
-            clusters[1][0]->signal_vci_ini_d_proc[0].print_trace("proc_1_0_0_ini_d");
-//            clusters[1][0]->signal_vci_ini_c_proc[0].print_trace("proc_1_0_0_ini_c");
-//            clusters[1][0]->signal_vci_tgt_c_proc[0].print_trace("proc_1_0_0_tgt_c");
-            clusters[1][0]->signal_vci_tgt_d_memc.print_trace("memc_1_0_tgt_d  ");
-//            clusters[1][0]->signal_vci_ini_c_memc.print_trace("memc_1_0_ini_c  ");
-//            clusters[1][0]->signal_vci_tgt_c_memc.print_trace("memc_1_0_tgt_c  ");
-//            clusters[1][0]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d  ");
-//            clusters[1][0]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d  ");
-//            clusters[1][0]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d  ");
-//            clusters[1][0]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d  ");
-            clusters[1][0]->signal_vci_tgt_d_mtty.print_trace("mtty_1_0_tgt_d  ");
-            clusters[1][0]->signal_vci_xram.print_trace("memc_1_0_xram");
-  
-            // components cluster 11 /////////////////////
-//            clusters[1][1]->proc[0]->print_trace();
-//            clusters[1][1]->memc->print_trace();
-            
-            // signals cluster 11 ////////////////////////
-//            clusters[1][1]->signal_vci_ini_d_proc[0].print_trace("proc_1_1_0_ini_d");
-//            clusters[1][1]->signal_vci_ini_c_proc[0].print_trace("proc_1_1_0_ini_c");
-//            clusters[1][1]->signal_vci_tgt_c_proc[0].print_trace("proc_1_1_0_tgt_c");
-//            clusters[1][1]->signal_vci_xram.print_trace("memc_1_1_xram");
-        }
-
-        sc_start(sc_core::sc_time(1, SC_NS));
-    }
-    return EXIT_SUCCESS;
+         }
+      }
+   }
+
+   sc_start(sc_core::sc_time(1, SC_NS));
+   signal_resetn = true;
+
+   for (size_t n = 1; n < ncycles; n++){
+      if (trace_ok and (n > from_cycle) and (n % trace_period == 0)){
+         std::cout << "****************** cycle " << std::dec << n ;
+         std::cout << " ************************************************" << std::endl;
+
+         // components cluster 00 /////////////////////
+         //            clusters[0][0]->proc[0]->print_trace();
+         //            clusters[0][0]->memc->print_trace();
+
+         // signals cluster 00 ////////////////////////
+         //            clusters[0][0]->signal_vci_ini_d_proc[0].print_trace("proc_0_0_0_ini_d");
+         //            clusters[0][0]->signal_vci_ini_c_proc[0].print_trace("proc_0_0_0_ini_c");
+         //            clusters[0][0]->signal_vci_tgt_c_proc[0].print_trace("proc_0_0_0_tgt_c");
+         //            clusters[0][0]->signal_vci_xram.print_trace("memc_0_0_xram");
+
+         // components cluster 01 /////////////////////
+         //            clusters[0][1]->proc[0]->print_trace();
+         //            clusters[0][1]->memc->print_trace();
+
+         // signals cluster 01 ///////////////////////
+         //            clusters[0][1]->signal_vci_ini_d_proc[0].print_trace("proc_0_1_0_ini_d");
+         //            clusters[0][1]->signal_vci_ini_c_proc[0].print_trace("proc_0_1_0_ini_c");
+         //            clusters[0][1]->signal_vci_tgt_c_proc[0].print_trace("proc_0_1_0_tgt_c");
+         //            clusters[0][1]->signal_vci_xram.print_trace("memc_0_1_xram");
+
+         // components cluster 10 ////////////////////
+         clusters[1][0]->proc[0]->print_trace(1);
+         clusters[1][0]->memc->print_trace();
+         //            clusters[1][0]->bdev->print_trace();
+         //            clusters[1][0]->mdma->print_trace();
+
+         // signals cluster 10 ///////////////////////
+         clusters[1][0]->signal_vci_ini_d_proc[0].print_trace("proc_1_0_0_ini_d");
+         //            clusters[1][0]->signal_vci_ini_c_proc[0].print_trace("proc_1_0_0_ini_c");
+         //            clusters[1][0]->signal_vci_tgt_c_proc[0].print_trace("proc_1_0_0_tgt_c");
+         clusters[1][0]->signal_vci_tgt_d_memc.print_trace("memc_1_0_tgt_d  ");
+         //            clusters[1][0]->signal_vci_ini_c_memc.print_trace("memc_1_0_ini_c  ");
+         //            clusters[1][0]->signal_vci_tgt_c_memc.print_trace("memc_1_0_tgt_c  ");
+         //            clusters[1][0]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d  ");
+         //            clusters[1][0]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d  ");
+         //            clusters[1][0]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d  ");
+         //            clusters[1][0]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d  ");
+         clusters[1][0]->signal_vci_tgt_d_mtty.print_trace("mtty_1_0_tgt_d  ");
+         clusters[1][0]->signal_vci_xram.print_trace("memc_1_0_xram");
+
+         // components cluster 11 /////////////////////
+         //            clusters[1][1]->proc[0]->print_trace();
+         //            clusters[1][1]->memc->print_trace();
+
+         // signals cluster 11 ////////////////////////
+         //            clusters[1][1]->signal_vci_ini_d_proc[0].print_trace("proc_1_1_0_ini_d");
+         //            clusters[1][1]->signal_vci_ini_c_proc[0].print_trace("proc_1_1_0_ini_c");
+         //            clusters[1][1]->signal_vci_tgt_c_proc[0].print_trace("proc_1_1_0_tgt_c");
+         //            clusters[1][1]->signal_vci_xram.print_trace("memc_1_1_xram");
+      }
+
+      sc_start(sc_core::sc_time(1, SC_NS));
+   }
+   return EXIT_SUCCESS;
 }
 
 int sc_main (int argc, char *argv[])
 {
-	try {
-		return _main(argc, argv);
-	} catch (std::exception &e) {
-		std::cout << e.what() << std::endl;
-	} catch (...) {
-		std::cout << "Unknown exception occured" << std::endl;
-		throw;
-	}
-	return 1;
+   try {
+      return _main(argc, argv);
+   } catch (std::exception &e) {
+      std::cout << e.what() << std::endl;
+   } catch (...) {
+      std::cout << "Unknown exception occured" << std::endl;
+      throw;
+   }
+   return 1;
 }
+
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+
+
+
+
Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
===================================================================
--- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp	(revision 247)
+++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp	(revision 249)
@@ -8,482 +8,470 @@
 //////////////////////////////////////////////////////////////////////////
 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
-TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu(
-                        sc_module_name  insname,
-                        size_t          nprocs,
-                        size_t          x_id,
-                        size_t          y_id,
-                        size_t          cluster_id,
-                        const           soclib::common::MappingTable &mtd,
-                        const           soclib::common::MappingTable &mtc, 
-                        const           soclib::common::MappingTable &mtx, 
-                        size_t          x_width,
-                        size_t          y_width,
-                        size_t          tgtid_memc,
-                        size_t          tgtid_xicu,
-                        size_t          tgtid_fbuf,
-                        size_t          tgtid_mtty,
-                        size_t          tgtid_brom,
-                        size_t          tgtid_bdev,
-                        size_t          tgtid_mdma,
-                        size_t          memc_ways,
-                        size_t          memc_sets,
-                        size_t          l1_i_ways,
-                        size_t          l1_i_sets,
-                        size_t          l1_d_ways,
-                        size_t          l1_d_sets,
-                        size_t          xram_latency,
-                        bool            io,
-                        size_t          xfb,
-                        size_t          yfb,
-                        char*           disk_name,
-                        size_t          block_size,
-                        const Loader   &loader,
-                        uint32_t        frozen_cycles,
-                        uint32_t        debug_start_cycle,
-                        bool            debug_ok)
-      : soclib::caba::BaseModule(insname),
-        p_clk("clk"),
-        p_resetn("resetn"),
-
-        signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"),
-        signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"),
-        signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"),
-        signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"),
-        signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"),
-        signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"),
-        signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"),
-        signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"),
-
-        signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"),
-        signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"),
-
-        signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"),
-        signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"),
-        signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"),
-        signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"),
-        signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"),
-        signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"),
-        signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"),
-
-        signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 
-        signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"),
-
-        signal_vci_xram("signal_vci_xram")
-
-{
-        // Vectors of ports definition
-
-        p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
-        p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
-        p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
-        p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
-
-        // Components definition 
-
-        // on direct network : local srcid[proc] in [0...nprocs-1]
-        // on direct network : local srcid[mdma] = nprocs
-        // on direct network : local srcid[bdev] = nprocs + 1
-
-        // on coherence network : local srcid[proc] in [0...nprocs-1]
-        // on coherence network : local srcid[memc] = nprocs
-
-std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
-
-        for ( size_t p=0 ; p<nprocs ; p++ )
-        { 
-            std::ostringstream sproc;
-            sproc << "proc_" << x_id << "_" << y_id << "_" << p;
-            proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>(
-                sproc.str().c_str(),
-                cluster_id*nprocs + p,
-                mtd,                            // Mapping Table Direct
-                mtc,                            // Mapping Table Coherence
-                IntTab(cluster_id,p),           // SRCID_D
-                IntTab(cluster_id,p),           // SRCID_C
-                IntTab(cluster_id,p),           // TGTID_C
-                8,                              // ITLB ways
-                8,                              // ITLB sets
-                8,                              // DTLB ways
-                8,                              // DTLB sets
-                l1_i_ways,l1_i_sets,16,         // ICACHE size
-                l1_d_ways,l1_d_sets,16,         // DCACHE size
-                4,                              // WBUF width
-                4,                              // WBUF depth
-                x_width,                        // X Width
-                y_width,                        // Y Width
-                nprocs,                         // Memory Cache Local Id (coherence)
-                frozen_cycles,                  // max frozen cycles
-                debug_start_cycle,
-                debug_ok);
-        }
-
-std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
-
-        std::ostringstream smemc;
-        smemc << "memc_" << x_id << "_" << y_id;
-        memc = new VciMemCacheV4<vci_param>(
-                   smemc.str().c_str(),
-                   mtd, mtc, mtx,
-                   IntTab(cluster_id),                  // SRCID_X
-                   IntTab(cluster_id, nprocs),          // SRCID_C
-                   IntTab(cluster_id, tgtid_memc),      // TGTID_D
-                   IntTab(cluster_id, nprocs),          // TGTID_C
-                   memc_ways, memc_sets, 16,            // CACHE SIZE
-                   4096,                                // HEAP SIZE
-                   8,                                   // TRANSACTION TABLE DEPTH
-                   8,                                   // UPDATE TABLE DEPTH
-                   debug_start_cycle,
-                   debug_ok);
-
-        
-std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
-
-        std::ostringstream sxram;
-        sxram << "xram_" << x_id << "_" << y_id;
-        xram = new VciSimpleRam<vci_param>(
-                   sxram.str().c_str(),
-                   IntTab(cluster_id),
-                   mtx,
-                   loader,
-                   xram_latency);
-
-std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
-
-        size_t  nhwi = 4;                               // always 4 (or 9) ports, even if 
-        if( io == true ) nhwi = 9;                      // there if less than 4 processors
-        std::ostringstream sicu;
-        sicu << "xicu_" << x_id << "_" << y_id;
-        xicu = new VciXicu<vci_param>(
-                  sicu.str().c_str(),
-                  mtd,                                  // mapping table
-                  IntTab(cluster_id, tgtid_xicu),       // TGTID_D
-                  0,                                    // number of timer IRQs
-                  nhwi,                                 // number of hard IRQs
-                  0,                                    // number of soft IRQs
-                  nprocs);                              // number of output IRQs
-
-std::cout << "  - building dma_" << x_id << "_" << y_id << std::endl;
-
-        // dma multi-canaux
-        std::ostringstream sdma;
-        sdma << "dma_" << x_id << "_" << y_id;
-        mdma = new VciMultiDma<vci_param>(
-                   sdma.str().c_str(),
-                   mtd,
-                   IntTab(cluster_id, nprocs),          // SRCID
-                   IntTab(cluster_id, tgtid_mdma),      // TGTID
-                   64,                                  // burst size
-                   nprocs);                             // number of IRQs
-
-std::cout << "  - building xbard_" << x_id << "_" << y_id << std::endl;
-
-        // direct local crossbar
-        size_t nb_direct_initiators      = nprocs + 1;
-        size_t nb_direct_targets         = 3;
-        if( io == true )
-        {
-            nb_direct_initiators         = nprocs + 2;
-            nb_direct_targets            = 7;
-        }
-        std::ostringstream sd;
-        sd << "xbard_" << x_id << "_" << y_id;
-        xbard = new VciLocalCrossbar<vci_param>(
-                    sd.str().c_str(),
-                    mtd,
-                    IntTab(cluster_id),                 // cluster initiator index
-                    IntTab(cluster_id),                 // cluster target index
-                    nb_direct_initiators,               // number of initiators
-                    nb_direct_targets);                 // number of targets      
-        
-std::cout << "  - building xbarc_" << x_id << "_" << y_id << std::endl;
-
-        // coherence local crossbar
-        std::ostringstream sc;
-        sc << "xbarc_" << x_id << "_" << y_id;
-        xbarc = new VciLocalCrossbar<vci_param>(
-                    sc.str().c_str(),
-                    mtc,
-                    IntTab(cluster_id),                 // cluster initiator index
-                    IntTab(cluster_id),                 // cluster target index
-                    nprocs + 1,                         // number of initiators
-                    nprocs + 1);                        // number of targets
-        
-std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
-
-        // direct initiator wrapper
-        std::ostringstream wid;
-        wid << "iniwrapperd_" << x_id << "_" << y_id;
-        iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
-                          wid.str().c_str(),
-                          4,                            // cmd fifo depth
-                          4);                           // rsp fifo depth
-
-        // direct target wrapper
-        std::ostringstream wtd;
-        wtd << "tgtwrapperd_" << x_id << "_" << y_id;
-        tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
-                          wtd.str().c_str(),
-                          4,                            // cmd fifo depth
-                          4);                           // rsp fifo depth
-
-        // coherence initiator wrapper
-        std::ostringstream wic;
-        wic << "iniwrapperc_" << x_id << "_" << y_id;
-        iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
-                          wic.str().c_str(),
-                          4,                            // cmd fifo depth
-                          4);                           // rsp fifo depth
-
-        // coherence target wrapper
-        std::ostringstream wtc;
-        wtc << "tgtwrapperc_" << x_id << "_" << y_id;
-        tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
-                          wtc.str().c_str(),
-                          4,                            // cmd fifo depth
-                          4);                           // rsp fifo depth
-
-std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
-
-        // CMD router
-        std::ostringstream scmd;
-        scmd << "cmdrouter_" << x_id << "_" << y_id;
-        cmdrouter = new VirtualDspinRouter<cmd_width>(
-                        scmd.str().c_str(),
-                        x_id,y_id,                    // coordinate in the mesh
-                        x_width, y_width,             // x & y fields width
-                        4,4);                         // input & output fifo depths
-        
-std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
-
-        // RSP router
-        std::ostringstream srsp;
-        srsp << "rsprouter_" << x_id << "_" << y_id;
-        rsprouter = new VirtualDspinRouter<rsp_width>(
-                        srsp.str().c_str(),
-                        x_id,y_id,                    // coordinates in mesh
-                        x_width, y_width,             // x & y fields width
-                        4,4);                         // input & output fifo depths
-        
-        // IO cluster components
-        if ( io == true )
-        {
-            brom = new VciSimpleRam<vci_param>(
-                       "brom",
-                       IntTab(cluster_id, tgtid_brom),
-                       mtd,
-                       loader);
-
-            fbuf = new VciFrameBuffer<vci_param>(
-                       "fbuf",
-                       IntTab(cluster_id, tgtid_fbuf),
-                       mtd,
-                       xfb, yfb); 
-
-            bdev = new VciBlockDeviceTsarV4<vci_param>(
-                       "bdev",
-                       mtd,
-                       IntTab(cluster_id, nprocs+1),
-                       IntTab(cluster_id, tgtid_bdev),
-                       disk_name,
-                       block_size);
-
-            mtty = new VciMultiTty<vci_param>(
-                       "mtty",
-                       IntTab(cluster_id, tgtid_mtty),
-                       mtd, 
-                       "tty0", "tty1", "tty2", "tty3", NULL);
-        }
-
-std::cout << "  - all components constructed" << std::endl;
-
-        ////////////////////////////////////
-        // Connections are defined here
-        ////////////////////////////////////
-
-        // CMDROUTER and RSPROUTER
-        cmdrouter->p_clk                        (this->p_clk);
-        cmdrouter->p_resetn                     (this->p_resetn);
-        rsprouter->p_clk                        (this->p_clk);
-        rsprouter->p_resetn                     (this->p_resetn);
-        for(int x = 0; x < 2; x++)
-        {
-          for(int y = 0; y < 4; y++)
-          {
-            cmdrouter->p_out[x][y]              (this->p_cmd_out[x][y]);
-            cmdrouter->p_in[x][y]               (this->p_cmd_in[x][y]);
-            rsprouter->p_out[x][y]              (this->p_rsp_out[x][y]);
-            rsprouter->p_in[x][y]               (this->p_rsp_in[x][y]);
-          }
-        }
-        
-        cmdrouter->p_out[0][4]                  (signal_dspin_cmd_g2l_d);
-        cmdrouter->p_out[1][4]                  (signal_dspin_cmd_g2l_c);
-        cmdrouter->p_in[0][4]                   (signal_dspin_cmd_l2g_d);
-        cmdrouter->p_in[1][4]                   (signal_dspin_cmd_l2g_c);
-
-        rsprouter->p_out[0][4]                  (signal_dspin_rsp_g2l_d);
-        rsprouter->p_out[1][4]                  (signal_dspin_rsp_g2l_c);
-        rsprouter->p_in[0][4]                   (signal_dspin_rsp_l2g_d);
-        rsprouter->p_in[1][4]                   (signal_dspin_rsp_l2g_c);
-
-        // VCI/DSPIN WRAPPERS
-        iniwrapperd->p_clk                      (this->p_clk);
-        iniwrapperd->p_resetn                   (this->p_resetn);
-        iniwrapperd->p_vci                      (signal_vci_l2g_d);
-        iniwrapperd->p_dspin_out                (signal_dspin_cmd_l2g_d);
-        iniwrapperd->p_dspin_in                 (signal_dspin_rsp_g2l_d);
-
-        tgtwrapperd->p_clk                      (this->p_clk);
-        tgtwrapperd->p_resetn                   (this->p_resetn);
-        tgtwrapperd->p_vci                      (signal_vci_g2l_d);
-        tgtwrapperd->p_dspin_out                (signal_dspin_rsp_l2g_d);
-        tgtwrapperd->p_dspin_in                 (signal_dspin_cmd_g2l_d);
-
-        iniwrapperc->p_clk                      (this->p_clk);
-        iniwrapperc->p_resetn                   (this->p_resetn);
-        iniwrapperc->p_vci                      (signal_vci_l2g_c);
-        iniwrapperc->p_dspin_out                (signal_dspin_cmd_l2g_c);
-        iniwrapperc->p_dspin_in                 (signal_dspin_rsp_g2l_c);
-
-        tgtwrapperc->p_clk                      (this->p_clk);
-        tgtwrapperc->p_resetn                   (this->p_resetn);
-        tgtwrapperc->p_vci                      (signal_vci_g2l_c);
-        tgtwrapperc->p_dspin_out                (signal_dspin_rsp_l2g_c);
-        tgtwrapperc->p_dspin_in                 (signal_dspin_cmd_g2l_c);
-
-        // CROSSBAR direct
-        xbard->p_clk                            (this->p_clk);
-        xbard->p_resetn                         (this->p_resetn);
-        xbard->p_initiator_to_up                (signal_vci_l2g_d);
-        xbard->p_target_to_up                   (signal_vci_g2l_d);
-          
-        xbard->p_to_target[tgtid_memc]          (signal_vci_tgt_d_memc);
-        xbard->p_to_target[tgtid_xicu]          (signal_vci_tgt_d_xicu);
-        xbard->p_to_target[tgtid_mdma]          (signal_vci_tgt_d_mdma);
-          
-        xbard->p_to_initiator[nprocs]           (signal_vci_ini_d_mdma);
-
-        for ( size_t p=0 ; p<nprocs ; p++)
-        {
-            xbard->p_to_initiator[p]            (signal_vci_ini_d_proc[p]);
-        }
-
-        if ( io == true )
-        {
-            xbard->p_to_target[tgtid_mtty]      (signal_vci_tgt_d_mtty);
-            xbard->p_to_target[tgtid_brom]      (signal_vci_tgt_d_brom);
-            xbard->p_to_target[tgtid_bdev]      (signal_vci_tgt_d_bdev);
-            xbard->p_to_target[tgtid_fbuf]      (signal_vci_tgt_d_fbuf);
-            
-            xbard->p_to_initiator[nprocs+1]     (signal_vci_ini_d_bdev);
-        }
-        
-        // CROSSBAR coherence
-        xbarc->p_clk                            (this->p_clk);
-        xbarc->p_resetn                         (this->p_resetn);
-        xbarc->p_initiator_to_up                (signal_vci_l2g_c);
-        xbarc->p_target_to_up                   (signal_vci_g2l_c);
-        xbarc->p_to_initiator[nprocs]           (signal_vci_ini_c_memc);
-        xbarc->p_to_target[nprocs]              (signal_vci_tgt_c_memc);
-        for ( size_t p=0 ; p<nprocs ; p++)
-        {
-            xbarc->p_to_target[p]               (signal_vci_tgt_c_proc[p]);
-            xbarc->p_to_initiator[p]            (signal_vci_ini_c_proc[p]);
-        }
-
-        // Processors
-        for ( size_t p=0 ; p<nprocs ; p++)
-        {
-            proc[p]->p_clk                      (this->p_clk);
-            proc[p]->p_resetn                   (this->p_resetn);
-            proc[p]->p_vci_ini_d                (signal_vci_ini_d_proc[p]);
-            proc[p]->p_vci_ini_c                (signal_vci_ini_c_proc[p]);
-            proc[p]->p_vci_tgt_c                (signal_vci_tgt_c_proc[p]);
-            proc[p]->p_irq[0]                   (signal_proc_it[p]);
-            for ( size_t j = 1 ; j < 6 ; j++ )
+   TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu(
+         sc_module_name  insname,
+         size_t          nprocs,
+         size_t          x_id,
+         size_t          y_id,
+         size_t          cluster_id,
+         const           soclib::common::MappingTable &mtd,
+         const           soclib::common::MappingTable &mtc, 
+         const           soclib::common::MappingTable &mtx, 
+         size_t          x_width,
+         size_t          y_width,
+         size_t          tgtid_memc,
+         size_t          tgtid_xicu,
+         size_t          tgtid_fbuf,
+         size_t          tgtid_mtty,
+         size_t          tgtid_brom,
+         size_t          tgtid_bdev,
+         size_t          tgtid_mdma,
+         size_t          memc_ways,
+         size_t          memc_sets,
+         size_t          l1_i_ways,
+         size_t          l1_i_sets,
+         size_t          l1_d_ways,
+         size_t          l1_d_sets,
+         size_t          xram_latency,
+         bool            io,
+         size_t          xfb,
+         size_t          yfb,
+         char*           disk_name,
+         size_t          block_size,
+         const Loader   &loader,
+         uint32_t        frozen_cycles,
+         uint32_t        debug_start_cycle,
+         bool            debug_ok)
+            : soclib::caba::BaseModule(insname),
+            p_clk("clk"),
+            p_resetn("resetn"),
+
+            signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"),
+            signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"),
+            signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"),
+            signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"),
+            signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"),
+            signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"),
+            signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"),
+            signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"),
+
+            signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"),
+            signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"),
+
+            signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"),
+            signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"),
+            signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"),
+            signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"),
+            signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"),
+            signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"),
+            signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"),
+
+            signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 
+            signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"),
+
+            signal_vci_xram("signal_vci_xram")
+
             {
-                proc[p]->p_irq[j]               (signal_false);
-            }
-        }
-        
-        // XICU
-        xicu->p_clk                             (this->p_clk);
-        xicu->p_resetn                          (this->p_resetn);
-        xicu->p_vci                             (signal_vci_tgt_d_xicu);
-        for ( size_t p=0 ; p<nprocs ; p++)
-        {
-            xicu->p_irq[p]                      (signal_proc_it[p]);
-        }
-        for ( size_t p=0 ; p<nprocs ; p++)
-        {
-            xicu->p_hwi[p]                      (signal_irq_mdma[p]);
-        }
-        for ( size_t x=nprocs ; x<4 ; x++)
-        {
-            xicu->p_hwi[x]                      (signal_false);
-        }
-        if ( io == true )
-        {
-            xicu->p_hwi[4]                      (signal_irq_tty0);
-            xicu->p_hwi[5]                      (signal_irq_tty1);
-            xicu->p_hwi[6]                      (signal_irq_tty2);
-            xicu->p_hwi[7]                      (signal_irq_tty3);
-            xicu->p_hwi[8]                      (signal_irq_bdev);
-        }
-
-        // MEMC
-        memc->p_clk                             (this->p_clk);
-        memc->p_resetn                          (this->p_resetn);
-        memc->p_vci_ixr                         (signal_vci_xram);
-        memc->p_vci_tgt                         (signal_vci_tgt_d_memc);
-        memc->p_vci_ini                         (signal_vci_ini_c_memc);
-        memc->p_vci_tgt_cleanup                 (signal_vci_tgt_c_memc);
-
-        // XRAM
-        xram->p_clk                             (this->p_clk);
-        xram->p_resetn                          (this->p_resetn);
-        xram->p_vci                             (signal_vci_xram);
-
-        // CDMA
-        mdma->p_clk                             (this->p_clk);
-        mdma->p_resetn                          (this->p_resetn);
-        mdma->p_vci_target                      (signal_vci_tgt_d_mdma);
-        mdma->p_vci_initiator                   (signal_vci_ini_d_mdma);
-        for (size_t p=0 ; p<nprocs ; p++)
-        {
-            mdma->p_irq[p]                       (signal_irq_mdma[p]);
-        }
-
-        // Components in IO cluster
-
-        if ( io == true )
-        {
-            // BDEV            
-            bdev->p_clk                         (this->p_clk);
-            bdev->p_resetn                      (this->p_resetn);
-            bdev->p_irq                         (signal_irq_bdev);
-            bdev->p_vci_target                  (signal_vci_tgt_d_bdev);
-            bdev->p_vci_initiator               (signal_vci_ini_d_bdev);
-
-            // FBUF
-            fbuf->p_clk                         (this->p_clk);
-            fbuf->p_resetn                      (this->p_resetn);
-            fbuf->p_vci                         (signal_vci_tgt_d_fbuf);
-
-            // BROM
-            brom->p_clk                         (this->p_clk);
-            brom->p_resetn                      (this->p_resetn);
-            brom->p_vci                         (signal_vci_tgt_d_brom);
-
-            // MTTY
-            mtty->p_clk                         (this->p_clk);
-            mtty->p_resetn                      (this->p_resetn);
-            mtty->p_vci                         (signal_vci_tgt_d_mtty);
-            mtty->p_irq[0]                      (signal_irq_tty0);
-            mtty->p_irq[1]                      (signal_irq_tty1);
-            mtty->p_irq[2]                      (signal_irq_tty2);
-            mtty->p_irq[3]                      (signal_irq_tty3);
-        }
-} // end constructor
+               // Vectors of ports definition
+
+               p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
+               p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
+               p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
+               p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
+
+               // Components definition 
+
+               // on direct network : local srcid[proc] in [0...nprocs-1]
+               // on direct network : local srcid[mdma] = nprocs
+               // on direct network : local srcid[bdev] = nprocs + 1
+
+               // on coherence network : local srcid[proc] in [0...nprocs-1]
+               // on coherence network : local srcid[memc] = nprocs
+
+               std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
+
+               for (size_t p = 0; p < nprocs; p++){ 
+                  std::ostringstream sproc;
+                  sproc << "proc_" << x_id << "_" << y_id << "_" << p;
+                  proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>(
+                        sproc.str().c_str(),
+                        cluster_id*nprocs + p,
+                        mtd,                            // Mapping Table Direct
+                        mtc,                            // Mapping Table Coherence
+                        IntTab(cluster_id,p),           // SRCID_D
+                        IntTab(cluster_id,p),           // SRCID_C
+                        IntTab(cluster_id,p),           // TGTID_C
+                        8,                              // ITLB ways
+                        8,                              // ITLB sets
+                        8,                              // DTLB ways
+                        8,                              // DTLB sets
+                        l1_i_ways,l1_i_sets,16,         // ICACHE size
+                        l1_d_ways,l1_d_sets,16,         // DCACHE size
+                        4,                              // WBUF width
+                        4,                              // WBUF depth
+                        x_width,                        // X Width
+                        y_width,                        // Y Width
+                        nprocs,                         // Memory Cache Local Id (coherence)
+                        frozen_cycles,                  // max frozen cycles
+                        debug_start_cycle,
+                        debug_ok);
+               }
+
+               std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
+
+               std::ostringstream smemc;
+               smemc << "memc_" << x_id << "_" << y_id;
+               memc = new VciMemCacheV4<vci_param>(
+                     smemc.str().c_str(),
+                     mtd, mtc, mtx,
+                     IntTab(cluster_id),                  // SRCID_X
+                     IntTab(cluster_id, nprocs),          // SRCID_C
+                     IntTab(cluster_id, tgtid_memc),      // TGTID_D
+                     IntTab(cluster_id, nprocs),          // TGTID_C
+                     memc_ways, memc_sets, 16,            // CACHE SIZE
+                     4096,                                // HEAP SIZE
+                     8,                                   // TRANSACTION TABLE DEPTH
+                     8,                                   // UPDATE TABLE DEPTH
+                     debug_start_cycle,
+                     debug_ok);
+
+
+               std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
+
+               std::ostringstream sxram;
+               sxram << "xram_" << x_id << "_" << y_id;
+               xram = new VciSimpleRam<vci_param>(
+                     sxram.str().c_str(),
+                     IntTab(cluster_id),
+                     mtx,
+                     loader,
+                     xram_latency);
+
+               std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
+
+               size_t  nhwi = 4;                               // always 4 (or 9) ports, even if 
+               if (io){
+                  nhwi = 9;                      // there if less than 4 processors
+               }
+               std::ostringstream sicu;
+               sicu << "xicu_" << x_id << "_" << y_id;
+               xicu = new VciXicu<vci_param>(
+                     sicu.str().c_str(),
+                     mtd,                                  // mapping table
+                     IntTab(cluster_id, tgtid_xicu),       // TGTID_D
+                     0,                                    // number of timer IRQs
+                     nhwi,                                 // number of hard IRQs
+                     0,                                    // number of soft IRQs
+                     nprocs);                              // number of output IRQs
+
+               std::cout << "  - building dma_" << x_id << "_" << y_id << std::endl;
+
+               // dma multi-canaux
+               std::ostringstream sdma;
+               sdma << "dma_" << x_id << "_" << y_id;
+               mdma = new VciMultiDma<vci_param>(
+                     sdma.str().c_str(),
+                     mtd,
+                     IntTab(cluster_id, nprocs),          // SRCID
+                     IntTab(cluster_id, tgtid_mdma),      // TGTID
+                     64,                                  // burst size
+                     nprocs);                             // number of IRQs
+
+               std::cout << "  - building xbard_" << x_id << "_" << y_id << std::endl;
+
+               // direct local crossbar
+               size_t nb_direct_initiators      = nprocs + 1;
+               size_t nb_direct_targets         = 3;
+               if (io){
+                  nb_direct_initiators         = nprocs + 2;
+                  nb_direct_targets            = 7;
+               }
+               std::ostringstream sd;
+               sd << "xbard_" << x_id << "_" << y_id;
+               xbard = new VciLocalCrossbar<vci_param>(
+                     sd.str().c_str(),
+                     mtd,
+                     IntTab(cluster_id),                 // cluster initiator index
+                     IntTab(cluster_id),                 // cluster target index
+                     nb_direct_initiators,               // number of initiators
+                     nb_direct_targets);                 // number of targets      
+
+               std::cout << "  - building xbarc_" << x_id << "_" << y_id << std::endl;
+
+               // coherence local crossbar
+               std::ostringstream sc;
+               sc << "xbarc_" << x_id << "_" << y_id;
+               xbarc = new VciLocalCrossbar<vci_param>(
+                     sc.str().c_str(),
+                     mtc,
+                     IntTab(cluster_id),                 // cluster initiator index
+                     IntTab(cluster_id),                 // cluster target index
+                     nprocs + 1,                         // number of initiators
+                     nprocs + 1);                        // number of targets
+
+               std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
+
+               // direct initiator wrapper
+               std::ostringstream wid;
+               wid << "iniwrapperd_" << x_id << "_" << y_id;
+               iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                     wid.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+               // direct target wrapper
+               std::ostringstream wtd;
+               wtd << "tgtwrapperd_" << x_id << "_" << y_id;
+               tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+                     wtd.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+               // coherence initiator wrapper
+               std::ostringstream wic;
+               wic << "iniwrapperc_" << x_id << "_" << y_id;
+               iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                     wic.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+               // coherence target wrapper
+               std::ostringstream wtc;
+               wtc << "tgtwrapperc_" << x_id << "_" << y_id;
+               tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+                     wtc.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+               std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
+
+               // CMD router
+               std::ostringstream scmd;
+               scmd << "cmdrouter_" << x_id << "_" << y_id;
+               cmdrouter = new VirtualDspinRouter<cmd_width>(
+                     scmd.str().c_str(),
+                     x_id,y_id,                    // coordinate in the mesh
+                     x_width, y_width,             // x & y fields width
+                     4,4);                         // input & output fifo depths
+
+               std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
+
+               // RSP router
+               std::ostringstream srsp;
+               srsp << "rsprouter_" << x_id << "_" << y_id;
+               rsprouter = new VirtualDspinRouter<rsp_width>(
+                     srsp.str().c_str(),
+                     x_id,y_id,                    // coordinates in mesh
+                     x_width, y_width,             // x & y fields width
+                     4,4);                         // input & output fifo depths
+
+               // IO cluster components
+               if (io){
+                  brom = new VciSimpleRam<vci_param>(
+                        "brom",
+                        IntTab(cluster_id, tgtid_brom),
+                        mtd,
+                        loader);
+
+                  fbuf = new VciFrameBuffer<vci_param>(
+                        "fbuf",
+                        IntTab(cluster_id, tgtid_fbuf),
+                        mtd,
+                        xfb, yfb); 
+
+                  bdev = new VciBlockDeviceTsarV4<vci_param>(
+                        "bdev",
+                        mtd,
+                        IntTab(cluster_id, nprocs+1),
+                        IntTab(cluster_id, tgtid_bdev),
+                        disk_name,
+                        block_size);
+
+                  mtty = new VciMultiTty<vci_param>(
+                        "mtty",
+                        IntTab(cluster_id, tgtid_mtty),
+                        mtd, 
+                        "tty0", "tty1", "tty2", "tty3", NULL);
+               }
+
+               std::cout << "  - all components constructed" << std::endl;
+
+               ////////////////////////////////////
+               // Connections are defined here
+               ////////////////////////////////////
+
+               // CMDROUTER and RSPROUTER
+               cmdrouter->p_clk                        (this->p_clk);
+               cmdrouter->p_resetn                     (this->p_resetn);
+               rsprouter->p_clk                        (this->p_clk);
+               rsprouter->p_resetn                     (this->p_resetn);
+               for (int x = 0; x < 2; x++){
+                  for(int y = 0; y < 4; y++){
+                     cmdrouter->p_out[x][y]            (this->p_cmd_out[x][y]);
+                     cmdrouter->p_in[x][y]             (this->p_cmd_in[x][y]);
+                     rsprouter->p_out[x][y]            (this->p_rsp_out[x][y]);
+                     rsprouter->p_in[x][y]             (this->p_rsp_in[x][y]);
+                  }
+               }
+
+               cmdrouter->p_out[0][4]                  (signal_dspin_cmd_g2l_d);
+               cmdrouter->p_out[1][4]                  (signal_dspin_cmd_g2l_c);
+               cmdrouter->p_in[0][4]                   (signal_dspin_cmd_l2g_d);
+               cmdrouter->p_in[1][4]                   (signal_dspin_cmd_l2g_c);
+
+               rsprouter->p_out[0][4]                  (signal_dspin_rsp_g2l_d);
+               rsprouter->p_out[1][4]                  (signal_dspin_rsp_g2l_c);
+               rsprouter->p_in[0][4]                   (signal_dspin_rsp_l2g_d);
+               rsprouter->p_in[1][4]                   (signal_dspin_rsp_l2g_c);
+
+               // VCI/DSPIN WRAPPERS
+               iniwrapperd->p_clk                      (this->p_clk);
+               iniwrapperd->p_resetn                   (this->p_resetn);
+               iniwrapperd->p_vci                      (signal_vci_l2g_d);
+               iniwrapperd->p_dspin_out                (signal_dspin_cmd_l2g_d);
+               iniwrapperd->p_dspin_in                 (signal_dspin_rsp_g2l_d);
+
+               tgtwrapperd->p_clk                      (this->p_clk);
+               tgtwrapperd->p_resetn                   (this->p_resetn);
+               tgtwrapperd->p_vci                      (signal_vci_g2l_d);
+               tgtwrapperd->p_dspin_out                (signal_dspin_rsp_l2g_d);
+               tgtwrapperd->p_dspin_in                 (signal_dspin_cmd_g2l_d);
+
+               iniwrapperc->p_clk                      (this->p_clk);
+               iniwrapperc->p_resetn                   (this->p_resetn);
+               iniwrapperc->p_vci                      (signal_vci_l2g_c);
+               iniwrapperc->p_dspin_out                (signal_dspin_cmd_l2g_c);
+               iniwrapperc->p_dspin_in                 (signal_dspin_rsp_g2l_c);
+
+               tgtwrapperc->p_clk                      (this->p_clk);
+               tgtwrapperc->p_resetn                   (this->p_resetn);
+               tgtwrapperc->p_vci                      (signal_vci_g2l_c);
+               tgtwrapperc->p_dspin_out                (signal_dspin_rsp_l2g_c);
+               tgtwrapperc->p_dspin_in                 (signal_dspin_cmd_g2l_c);
+
+               // CROSSBAR direct
+               xbard->p_clk                            (this->p_clk);
+               xbard->p_resetn                         (this->p_resetn);
+               xbard->p_initiator_to_up                (signal_vci_l2g_d);
+               xbard->p_target_to_up                   (signal_vci_g2l_d);
+
+               xbard->p_to_target[tgtid_memc]          (signal_vci_tgt_d_memc);
+               xbard->p_to_target[tgtid_xicu]          (signal_vci_tgt_d_xicu);
+               xbard->p_to_target[tgtid_mdma]          (signal_vci_tgt_d_mdma);
+
+               xbard->p_to_initiator[nprocs]           (signal_vci_ini_d_mdma);
+
+               for (size_t p = 0; p < nprocs; p++){
+                  xbard->p_to_initiator[p]            (signal_vci_ini_d_proc[p]);
+               }
+
+               if (io){
+                  xbard->p_to_target[tgtid_mtty]      (signal_vci_tgt_d_mtty);
+                  xbard->p_to_target[tgtid_brom]      (signal_vci_tgt_d_brom);
+                  xbard->p_to_target[tgtid_bdev]      (signal_vci_tgt_d_bdev);
+                  xbard->p_to_target[tgtid_fbuf]      (signal_vci_tgt_d_fbuf);
+
+                  xbard->p_to_initiator[nprocs+1]     (signal_vci_ini_d_bdev);
+               }
+
+               // CROSSBAR coherence
+               xbarc->p_clk                            (this->p_clk);
+               xbarc->p_resetn                         (this->p_resetn);
+               xbarc->p_initiator_to_up                (signal_vci_l2g_c);
+               xbarc->p_target_to_up                   (signal_vci_g2l_c);
+               xbarc->p_to_initiator[nprocs]           (signal_vci_ini_c_memc);
+               xbarc->p_to_target[nprocs]              (signal_vci_tgt_c_memc);
+               for (size_t p = 0; p < nprocs; p++) {
+                  xbarc->p_to_target[p]                (signal_vci_tgt_c_proc[p]);
+                  xbarc->p_to_initiator[p]             (signal_vci_ini_c_proc[p]);
+               }
+
+               // Processors
+               for (size_t p = 0; p < nprocs; p++){
+                  proc[p]->p_clk                       (this->p_clk);
+                  proc[p]->p_resetn                    (this->p_resetn);
+                  proc[p]->p_vci_ini_d                 (signal_vci_ini_d_proc[p]);
+                  proc[p]->p_vci_ini_c                 (signal_vci_ini_c_proc[p]);
+                  proc[p]->p_vci_tgt_c                 (signal_vci_tgt_c_proc[p]);
+                  proc[p]->p_irq[0]                    (signal_proc_it[p]);
+                  for ( size_t j = 1 ; j < 6 ; j++){
+                     proc[p]->p_irq[j]                 (signal_false);
+                  }
+               }
+
+               // XICU
+               xicu->p_clk                             (this->p_clk);
+               xicu->p_resetn                          (this->p_resetn);
+               xicu->p_vci                             (signal_vci_tgt_d_xicu);
+               for (size_t p = 0; p < nprocs; p++){
+                  xicu->p_irq[p] (signal_proc_it[p]);
+               }
+               for (size_t p = 0; p < nprocs; p++){
+                  xicu->p_hwi[p] (signal_irq_mdma[p]);
+               }
+               for (size_t x = nprocs; x < 4; x++){
+                  xicu->p_hwi[x] (signal_false);
+               }
+
+               if (io){
+                  xicu->p_hwi[4]         (signal_irq_tty0);
+                  xicu->p_hwi[5]         (signal_irq_tty1);
+                  xicu->p_hwi[6]         (signal_irq_tty2);
+                  xicu->p_hwi[7]         (signal_irq_tty3);
+
+                  xicu->p_hwi[8]         (signal_irq_bdev);
+               }
+
+               // MEMC
+               memc->p_clk                             (this->p_clk);
+               memc->p_resetn                          (this->p_resetn);
+               memc->p_vci_ixr                         (signal_vci_xram);
+               memc->p_vci_tgt                         (signal_vci_tgt_d_memc);
+               memc->p_vci_ini                         (signal_vci_ini_c_memc);
+               memc->p_vci_tgt_cleanup                 (signal_vci_tgt_c_memc);
+
+               // XRAM
+               xram->p_clk                             (this->p_clk);
+               xram->p_resetn                          (this->p_resetn);
+               xram->p_vci                             (signal_vci_xram);
+
+               // CDMA
+               mdma->p_clk                             (this->p_clk);
+               mdma->p_resetn                          (this->p_resetn);
+               mdma->p_vci_target                      (signal_vci_tgt_d_mdma);
+               mdma->p_vci_initiator                   (signal_vci_ini_d_mdma);
+               for (size_t p = 0; p < nprocs; p++){
+                  mdma->p_irq[p]                       (signal_irq_mdma[p]);
+               }
+
+               // Components in IO cluster
+
+               if (io){
+                  // BDEV            
+                  bdev->p_clk                         (this->p_clk);
+                  bdev->p_resetn                      (this->p_resetn);
+                  bdev->p_irq                         (signal_irq_bdev);
+                  bdev->p_vci_target                  (signal_vci_tgt_d_bdev);
+                  bdev->p_vci_initiator               (signal_vci_ini_d_bdev);
+
+                  // FBUF
+                  fbuf->p_clk                         (this->p_clk);
+                  fbuf->p_resetn                      (this->p_resetn);
+                  fbuf->p_vci                         (signal_vci_tgt_d_fbuf);
+
+                  // BROM
+                  brom->p_clk                         (this->p_clk);
+                  brom->p_resetn                      (this->p_resetn);
+                  brom->p_vci                         (signal_vci_tgt_d_brom);
+
+                  // MTTY
+                  mtty->p_clk                         (this->p_clk);
+                  mtty->p_resetn                      (this->p_resetn);
+                  mtty->p_vci                         (signal_vci_tgt_d_mtty);
+                  mtty->p_irq[0]                      (signal_irq_tty0);
+                  mtty->p_irq[1]                      (signal_irq_tty1);
+                  mtty->p_irq[2]                      (signal_irq_tty2);
+                  mtty->p_irq[3]                      (signal_irq_tty3);
+               }
+            } // end constructor
 
 ///////////////////////////////////////////////////////////////////////////
@@ -491,5 +479,19 @@
 ///////////////////////////////////////////////////////////////////////////
 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
-TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {}
-
-}}
+   TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {}
+
+}
+}
+
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+
+
+