Index: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 251)
+++ trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 253)
@@ -2042,5 +2042,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> Cache update in P2 stage" << std::dec
               << " / WAY = " << way 
               << " / SET = " << set 
@@ -2490,5 +2490,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
 }
 #endif
@@ -2506,5 +2506,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
 }
 #endif
@@ -2555,5 +2555,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_IDLE> Speculative access miss" << std::endl;
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> Speculative access miss" << std::endl;
 }
 #endif
@@ -2589,5 +2589,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_IDLE> HIT in dcache" << std::endl;
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dcache" << std::endl;
 }
 #endif
@@ -2777,9 +2777,9 @@
     if ( r_dcache_tlb_ins.read() ) 
     {
-        std::cout << "  <PROC.DCACHE_TLB_MISS> ITLB miss";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
     }
     else
     {                           
-        std::cout << "  <PROC.DCACHE_TLB_MISS> DTLB miss";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
     }
     std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
@@ -2831,5 +2831,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -2866,5 +2866,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -2887,5 +2887,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -2907,5 +2907,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
               << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
 }
@@ -2948,7 +2948,7 @@
 {
     if ( r_dcache_tlb_ins.read() ) 
-        std::cout << "  <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
     else                           
-        std::cout << "  <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
         std::cout << " way = " << std::dec << way
                   << " / set = " << set << std::endl;
@@ -3033,5 +3033,5 @@
     if ( r_dcache_tlb_ins.read() ) 
     {
-        std::cout << "  <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
         std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
                   << " / way = " << r_dcache_tlb_way.read() << std::endl;
@@ -3040,5 +3040,5 @@
     else                           
     {
-        std::cout << "  <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
         std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
                   << " / way = " << r_dcache_tlb_way.read() << std::endl;
@@ -3092,5 +3092,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
               << " PTE_FLAGS = " << std::hex << pte_flags 
               << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
@@ -3111,5 +3111,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
               << " PTE_FLAGS = " << std::hex << pte_flags 
               << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
@@ -3128,5 +3128,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> MISS in dcache:"
               << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
 }
@@ -3166,7 +3166,7 @@
 {
     if ( r_dcache_tlb_ins.read() ) 
-        std::cout << "  <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
     else                           
-        std::cout << "  <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
         std::cout << " way = " << std::dec << way
                   << " / set = " << set << std::endl;
@@ -3252,5 +3252,5 @@
     if ( r_dcache_tlb_ins.read() ) 
     {
-        std::cout << "  <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
         std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
                   << " / way = " << r_dcache_tlb_way.read() << std::endl;
@@ -3259,5 +3259,5 @@
     else                           
     {
-        std::cout << "  <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
         std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
                   << " / way = " << r_dcache_tlb_way.read() << std::endl;
@@ -3278,5 +3278,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
 }
 #endif
@@ -3323,5 +3323,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
 }
 #endif
@@ -3337,5 +3337,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
 }
 #endif
@@ -3492,5 +3492,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
+    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
               << " / VADDR = " << r_dcache_p0_wdata.read()
               << " / PADDR = " << paddr << std::endl;
@@ -3533,5 +3533,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
+    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
               << " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
               << " / HIT = " << hit
@@ -3589,5 +3589,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
+    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
               << " / NLINE = " << nline << std::endl;
 }
@@ -3638,5 +3638,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::dec
+    std::cout << "  <PROC " << name() << ".DCACHE_MISS_VICTIM> Select a slot:" << std::dec
               << " / WAY = "   << way 
               << " / SET = "   << set
@@ -3666,5 +3666,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_MISS_INVAL> inval line:" << std::dec
+    std::cout << "  <PROC " << name() << ".DCACHE_MISS_INVAL> inval line:" << std::dec
               << " / way = "   << way 
               << " / set = "   << set
@@ -3844,10 +3844,10 @@
         if ( r_dcache_miss_word.read() < m_dcache_words-1 ) 
         {
-            std::cout << "  <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
+            std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:"
                       << "  pop the FIFO, don't update the cache" << std::endl;
         }
         else
         {
-            std::cout << "  <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
+            std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:"
                       << " last word : send a cleanup request " << std::endl;
         }
@@ -3855,5 +3855,5 @@
     else
     {
-        std::cout << "  <PROC.DCACHE_MISS_UPDT> Write one word:"
+        std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Write one word:"
                   << " address = " << std::hex << r_dcache_vci_paddr.read() 
                   << " / data = "  << r_vci_rsp_fifo_dcache.read()
@@ -3977,5 +3977,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
+    std::cout << "  <PROC " << name() << ".DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
               << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() 
               << " / PTE_VALUE = " << pte << std::dec 
@@ -4016,5 +4016,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
+    std::cout << "  <PROC " << name() << ".DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
               << std::endl;
 }
@@ -4027,5 +4027,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
+    std::cout << "  <PROC " << name() << ".DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
               << std::endl;
 }
@@ -4093,5 +4093,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
+    std::cout << "  <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request matching a pending miss:"
               << " address = " << std::hex << paddr << std::endl;
 }
@@ -4138,5 +4138,5 @@
 {
     
-    std::cout << "  <PROC.DCACHE_CC_CHECK> Coherence request received :"
+    std::cout << "  <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request received :"
               << " address = " << std::hex << paddr << std::dec;
     if ( hit ) 
@@ -4189,5 +4189,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec
+    std::cout << "  <PROC " << name() << ".DCACHE_CC_INVAL> Invalidate cache line" << std::dec
 	      << " / WAY = " << way
 	      << " / SET = " << set << std::endl;
@@ -4238,5 +4238,5 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC.DCACHE_CC_UPDT> Update one word" << std::dec
+    std::cout << "  <PROC " << name() << ".DCACHE_CC_UPDT> Update one word" << std::dec
 	      << " / WAY = " << way
 	      << " / SET = " << set 
@@ -4283,5 +4283,5 @@
 if ( m_debug_dcache_fsm and ok )
 {
-    std::cout << "  <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex 
+    std::cout << "  <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex 
               << " line = " << line << std::dec
               << " / set = " << set 
@@ -4296,5 +4296,5 @@
 if ( m_debug_dcache_fsm and ok )
 {
-    std::cout << "  <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex 
+    std::cout << "  <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex 
               << " line = " << line << std::dec
               << " / set = " << set 
@@ -4328,6 +4328,6 @@
             std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
                       << " stop at cycle " << m_cpt_total_cycles << std::endl
-                      << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles 
-                      << std::endl;
+                      << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles << std::endl;
+                      r_iss.dump();
             exit(1);
         }
@@ -4767,5 +4767,5 @@
 if ( m_debug_cleanup_fsm )
 {
-    std::cout << "  <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
+    std::cout << "  <PROC " << name() << ".CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
               << " address = " << (r_dcache_cleanup_line.read()*m_dcache_words*4)
               << " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
@@ -4786,5 +4786,5 @@
 if ( m_debug_cleanup_fsm )
 {
-    std::cout << "  <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
+    std::cout << "  <PROC " << name() << ".CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
               << " address = " << (r_icache_cleanup_line.read()*m_icache_words*4)
               << " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
