Changeset 253 for trunk/modules/vci_mem_cache_v4/caba/source
- Timestamp:
- Aug 16, 2012, 2:41:27 PM (12 years ago)
- Location:
- trunk/modules/vci_mem_cache_v4/caba/source
- Files:
-
- 2 edited
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include/xram_transaction_v4.h (modified) (3 diffs)
-
src/vci_mem_cache_v4.cpp (modified) (101 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h
r184 r253 1 1 #ifndef XRAM_TRANSACTION_V4_H_ 2 2 #define XRAM_TRANSACTION_V4_H_ 3 3 4 4 #include <inttypes.h> 5 5 #include <systemc> … … 14 14 15 15 class TransactionTabEntry { 16 typedef uint32_t size_t;17 typedef uint32_t data_t;18 typedef sc_dt::sc_uint<40> addr_t;19 typedef uint32_t be_t;20 21 public:22 boolvalid; // entry valid23 boolxram_read; // read request to XRAM24 addr_tnline; // index (zy) of the requested line25 size_t srcid; // processor requesting the transaction26 size_t trdid; // processor requesting the transaction27 size_t pktid; // processor requesting the transaction28 boolproc_read; // read request from processor29 size_t read_length; // length of the read (for the response)30 size_t word_index; // index of the first read word (for the response)31 std::vector<data_t>wdata; // write buffer (one cache line)32 std::vector<be_t>wdata_be; // be for each data in the write buffer33 boolrerror; // error returned by xram34 35 /////////////////////////////////////////////////////////////////////36 // The init() function initializes the entry37 /////////////////////////////////////////////////////////////////////38 void init()39 {40 valid = false;41 rerror = false;42 }43 44 /////////////////////////////////////////////////////////////////////45 // The alloc() function initializes the vectors of an entry46 // Its arguments are :47 // - n_words : number of words per line in the cache48 /////////////////////////////////////////////////////////////////////49 void alloc(size_t n_words)50 {51 wdata_be.reserve( (int)n_words );52 wdata.reserve( (int)n_words );53 for(size_t i=0; i<n_words; i++)54 {55 wdata_be.push_back(0);56 wdata.push_back(0);57 }58 }59 60 ////////////////////////////////////////////////////////////////////61 // The copy() function copies an existing entry62 // Its arguments are :63 // - source : the transaction tab entry to copy64 ////////////////////////////////////////////////////////////////////65 void copy(const TransactionTabEntry &source)66 {67 valid = source.valid;68 xram_read = source.xram_read;69 nline = source.nline;70 srcid = source.srcid;71 trdid = source.trdid;72 pktid = source.pktid;73 proc_read = source.proc_read;74 read_length = source.read_length;75 word_index = source.word_index;76 wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());77 wdata.assign(source.wdata.begin(),source.wdata.end());78 rerror = source.rerror;79 }80 81 ////////////////////////////////////////////////////////////////////82 // The print() function prints the entry83 ////////////////////////////////////////////////////////////////////84 void print(){85 std::cout << "valid = " << valid << std::endl;86 std::cout << "xram_read = " << xram_read << std::endl;87 std::cout << "nline = " << std::hex << nline << std::endl;88 std::cout << "srcid = " << srcid << std::endl;89 std::cout << "trdid = " << trdid << std::endl;90 std::cout << "pktid = " << pktid << std::endl;91 std::cout << "proc_read = " << proc_read << std::endl;92 std::cout << "read_length = " << read_length << std::endl;93 std::cout << "word_index = " << word_index << std::endl;94 for(size_t i=0; i<wdata_be.size() ; i++){95 std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;96 }97 for(size_t i=0; i<wdata.size() ; i++){98 std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;99 }100 std::cout << std::endl;101 std::cout << "rerror = " << rerror << std::endl;102 }103 104 /////////////////////////////////////////////////////////////////////105 // Constructors106 /////////////////////////////////////////////////////////////////////107 108 TransactionTabEntry()109 { 110 wdata_be.clear();111 wdata.clear();112 valid=false;113 rerror=false;114 } 115 116 TransactionTabEntry(const TransactionTabEntry &source){117 valid = source.valid;118 xram_read = source.xram_read;119 nline = source.nline;120 srcid = source.srcid;121 trdid = source.trdid;122 pktid = source.pktid;123 proc_read = source.proc_read;124 read_length = source.read_length;125 word_index = source.word_index;126 wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());127 wdata.assign(source.wdata.begin(),source.wdata.end());128 rerror = source.rerror;129 }16 typedef uint32_t size_t; 17 typedef uint32_t data_t; 18 typedef sc_dt::sc_uint<40> addr_t; 19 typedef uint32_t be_t; 20 21 public: 22 bool valid; // entry valid 23 bool xram_read; // read request to XRAM 24 addr_t nline; // index (zy) of the requested line 25 size_t srcid; // processor requesting the transaction 26 size_t trdid; // processor requesting the transaction 27 size_t pktid; // processor requesting the transaction 28 bool proc_read; // read request from processor 29 size_t read_length; // length of the read (for the response) 30 size_t word_index; // index of the first read word (for the response) 31 std::vector<data_t> wdata; // write buffer (one cache line) 32 std::vector<be_t> wdata_be; // be for each data in the write buffer 33 bool rerror; // error returned by xram 34 35 ///////////////////////////////////////////////////////////////////// 36 // The init() function initializes the entry 37 ///////////////////////////////////////////////////////////////////// 38 void init() 39 { 40 valid = false; 41 rerror = false; 42 } 43 44 ///////////////////////////////////////////////////////////////////// 45 // The alloc() function initializes the vectors of an entry 46 // Its arguments are : 47 // - n_words : number of words per line in the cache 48 ///////////////////////////////////////////////////////////////////// 49 void alloc(size_t n_words) 50 { 51 wdata_be.reserve( (int)n_words ); 52 wdata.reserve( (int)n_words ); 53 for(size_t i=0; i<n_words; i++) 54 { 55 wdata_be.push_back(0); 56 wdata.push_back(0); 57 } 58 } 59 60 //////////////////////////////////////////////////////////////////// 61 // The copy() function copies an existing entry 62 // Its arguments are : 63 // - source : the transaction tab entry to copy 64 //////////////////////////////////////////////////////////////////// 65 void copy(const TransactionTabEntry &source) 66 { 67 valid = source.valid; 68 xram_read = source.xram_read; 69 nline = source.nline; 70 srcid = source.srcid; 71 trdid = source.trdid; 72 pktid = source.pktid; 73 proc_read = source.proc_read; 74 read_length = source.read_length; 75 word_index = source.word_index; 76 wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end()); 77 wdata.assign(source.wdata.begin(),source.wdata.end()); 78 rerror = source.rerror; 79 } 80 81 //////////////////////////////////////////////////////////////////// 82 // The print() function prints the entry 83 //////////////////////////////////////////////////////////////////// 84 void print(){ 85 std::cout << "valid = " << valid << std::endl; 86 std::cout << "xram_read = " << xram_read << std::endl; 87 std::cout << "nline = " << std::hex << nline << std::endl; 88 std::cout << "srcid = " << srcid << std::endl; 89 std::cout << "trdid = " << trdid << std::endl; 90 std::cout << "pktid = " << pktid << std::endl; 91 std::cout << "proc_read = " << proc_read << std::endl; 92 std::cout << "read_length = " << read_length << std::endl; 93 std::cout << "word_index = " << word_index << std::endl; 94 for(size_t i=0; i<wdata_be.size() ; i++){ 95 std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl; 96 } 97 for(size_t i=0; i<wdata.size() ; i++){ 98 std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl; 99 } 100 std::cout << std::endl; 101 std::cout << "rerror = " << rerror << std::endl; 102 } 103 104 ///////////////////////////////////////////////////////////////////// 105 // Constructors 106 ///////////////////////////////////////////////////////////////////// 107 108 TransactionTabEntry() 109 { 110 wdata_be.clear(); 111 wdata.clear(); 112 valid=false; 113 rerror=false; 114 } 115 116 TransactionTabEntry(const TransactionTabEntry &source){ 117 valid = source.valid; 118 xram_read = source.xram_read; 119 nline = source.nline; 120 srcid = source.srcid; 121 trdid = source.trdid; 122 pktid = source.pktid; 123 proc_read = source.proc_read; 124 read_length = source.read_length; 125 word_index = source.word_index; 126 wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end()); 127 wdata.assign(source.wdata.begin(),source.wdata.end()); 128 rerror = source.rerror; 129 } 130 130 131 131 }; // end class TransactionTabEntry … … 135 135 //////////////////////////////////////////////////////////////////////// 136 136 class TransactionTab{ 137 typedef uint32_t size_t;138 typedef uint32_t data_t;139 typedef sc_dt::sc_uint<40> addr_t;140 typedef uint32_t be_t;141 142 private:143 size_t size_tab; // The size of the tab144 145 data_t be_to_mask(be_t be)146 {147 data_t ret = 0;148 if ( be&0x1 ) {149 ret = ret | 0x000000FF;150 }151 if ( be&0x2 ) {152 ret = ret | 0x0000FF00;153 }154 if ( be&0x4 ) {155 ret = ret | 0x00FF0000;156 }157 if ( be&0x8 ) {158 ret = ret | 0xFF000000;159 }160 return ret;161 }162 163 public:164 TransactionTabEntry *tab; // The transaction tab165 166 ////////////////////////////////////////////////////////////////////167 // Constructors168 ////////////////////////////////////////////////////////////////////169 TransactionTab()170 { 171 size_tab=0;172 tab=NULL;173 } 174 175 TransactionTab(size_t n_entries, size_t n_words)176 { 177 size_tab = n_entries;178 tab = new TransactionTabEntry[size_tab];179 for ( size_t i=0; i<size_tab; i++) {180 181 }182 } 183 184 ~TransactionTab()185 { 186 delete [] tab;187 } 188 189 /////////////////////////////////////////////////////////////////////190 // The size() function returns the size of the tab191 /////////////////////////////////////////////////////////////////////192 size_t size()193 {194 return size_tab;195 }196 197 /////////////////////////////////////////////////////////////////////198 // The init() function initializes the transaction tab entries199 /////////////////////////////////////////////////////////////////////200 void init()201 {202 for ( size_t i=0; i<size_tab; i++) {203 tab[i].init();204 }205 }206 207 /////////////////////////////////////////////////////////////////////208 // The print() function prints a transaction tab entry209 // Arguments :210 // - index : the index of the entry to print211 /////////////////////////////////////////////////////////////////////212 void print(const size_t index)213 {214 assert( (index < size_tab)215 216 tab[index].print();217 return;218 }219 220 /////////////////////////////////////////////////////////////////////221 // The read() function returns a transaction tab entry.222 // Arguments :223 // - index : the index of the entry to read224 /////////////////////////////////////////////////////////////////////225 TransactionTabEntry read(const size_t index)226 {227 assert( (index < size_tab)228 229 return tab[index];230 }231 232 /////////////////////////////////////////////////////////////////////233 // The full() function returns the state of the transaction tab234 // Arguments :235 // - index : (return argument) the index of an empty entry236 // The function returns true if the transaction tab is full237 /////////////////////////////////////////////////////////////////////238 bool full(size_t &index)239 {240 for(size_t i=0; i<size_tab; i++){241 if(!tab[i].valid){242 243 244 }245 }246 return true;247 }248 249 /////////////////////////////////////////////////////////////////////250 // The hit_read() function checks if an XRAM read transaction exists251 // for a given cache line.252 // Arguments :253 // - index : (return argument) the index of the hit entry, if there is254 // - nline : the index (zy) of the requested line255 // The function returns true if a read request has already been sent256 //////////////////////////////////////////////////////////////////////257 bool hit_read(const addr_t nline,size_t &index)258 {259 for(size_t i=0; i<size_tab; i++){260 if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {261 262 263 }264 }265 return false;266 }267 268 ///////////////////////////////////////////////////////////////////////269 // The hit_write() function looks if an XRAM write transaction exists270 // for a given line.271 // Arguments :272 // - nline : the index (zy) of the requested line273 // The function returns true if a write request has already been sent274 ///////////////////////////////////////////////////////////////////////275 bool hit_write(const addr_t nline)276 {277 for(size_t i=0; i<size_tab; i++){278 if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {279 280 }281 }282 return false;283 }284 285 /////////////////////////////////////////////////////////////////////286 // The write_data_mask() function writes a vector of data (a line).287 // The data is written only if the corresponding bits are set288 // in the be vector.289 // Arguments :290 // - index : the index of the request in the transaction tab291 // - be : vector of be292 // - data : vector of data293 /////////////////////////////////////////////////////////////////////294 void write_data_mask(const size_t index,295 296 297 {298 assert( (index < size_tab)299 300 assert(be.size()==tab[index].wdata_be.size()301 302 assert(data.size()==tab[index].wdata.size()303 304 305 for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {306 tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];307 data_t mask = be_to_mask(be[i]);308 tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);309 }310 }311 312 /////////////////////////////////////////////////////////////////////313 // The set() function registers a transaction (read or write)314 // to the XRAM in the transaction tab.315 // Arguments :316 // - index : index in the transaction tab317 // - xram_read : transaction type (read or write a cache line)318 // - nline : the index (zy) of the cache line319 // - srcid : srcid of the initiator that caused the transaction320 // - trdid : trdid of the initiator that caused the transaction321 // - pktid : pktid of the initiator that caused the transaction322 // - proc_read : does the initiator want a copy323 // - read_length : length of read (in case of processor read)324 // - word_index : index in the line (in case of single word read)325 // - data : the data to write (in case of write)326 // - data_be : the mask of the data to write (in case of write)327 /////////////////////////////////////////////////////////////////////328 void set(const size_t index,329 330 331 332 333 334 335 336 337 338 339 {340 assert( (index < size_tab)341 342 assert(data_be.size()==tab[index].wdata_be.size()343 344 assert(data.size()==tab[index].wdata.size()345 346 347 tab[index].valid = true;348 tab[index].xram_read = xram_read;349 tab[index].nline = nline;350 tab[index].srcid = srcid;351 tab[index].trdid = trdid;352 tab[index].pktid = pktid;353 tab[index].proc_read = proc_read;354 tab[index].read_length = read_length;355 tab[index].word_index = word_index;356 for(size_t i=0; i<tab[index].wdata.size(); i++)357 {358 tab[index].wdata_be[i] = data_be[i];359 tab[index].wdata[i] = data[i];360 }361 }362 363 /////////////////////////////////////////////////////////////////////364 // The write_rsp() function writes a word of the response to an365 // XRAM read transaction.366 // The BE field in TRT is taken into account.367 // Arguments :368 // - index : the index of the transaction in the transaction tab369 // - word_index : the index of the data in the line370 // - data : the data to write371 // - error : invalid data372 /////////////////////////////////////////////////////////////////////373 void write_rsp(const size_t index,374 375 376 377 {378 assert( (index < size_tab)379 380 assert( (word <= tab[index].wdata_be.size())381 382 assert( tab[index].valid383 384 assert( tab[index].xram_read385 386 387 data_t mask = be_to_mask(tab[index].wdata_be[word]);388 tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);389 tab[index].rerror |= rerror;390 }391 392 /////////////////////////////////////////////////////////////////////393 // The erase() function erases an entry in the transaction tab.394 // Arguments :395 // - index : the index of the request in the transaction tab396 /////////////////////////////////////////////////////////////////////397 void erase(const size_t index)398 {399 assert( (index < size_tab)400 401 tab[index].valid = false;402 tab[index].rerror = false;403 }137 typedef uint32_t size_t; 138 typedef uint32_t data_t; 139 typedef sc_dt::sc_uint<40> addr_t; 140 typedef uint32_t be_t; 141 142 private: 143 size_t size_tab; // The size of the tab 144 145 data_t be_to_mask(be_t be) 146 { 147 data_t ret = 0; 148 if ( be&0x1 ) { 149 ret = ret | 0x000000FF; 150 } 151 if ( be&0x2 ) { 152 ret = ret | 0x0000FF00; 153 } 154 if ( be&0x4 ) { 155 ret = ret | 0x00FF0000; 156 } 157 if ( be&0x8 ) { 158 ret = ret | 0xFF000000; 159 } 160 return ret; 161 } 162 163 public: 164 TransactionTabEntry *tab; // The transaction tab 165 166 //////////////////////////////////////////////////////////////////// 167 // Constructors 168 //////////////////////////////////////////////////////////////////// 169 TransactionTab() 170 { 171 size_tab=0; 172 tab=NULL; 173 } 174 175 TransactionTab(size_t n_entries, size_t n_words) 176 { 177 size_tab = n_entries; 178 tab = new TransactionTabEntry[size_tab]; 179 for ( size_t i=0; i<size_tab; i++) { 180 tab[i].alloc(n_words); 181 } 182 } 183 184 ~TransactionTab() 185 { 186 delete [] tab; 187 } 188 189 ///////////////////////////////////////////////////////////////////// 190 // The size() function returns the size of the tab 191 ///////////////////////////////////////////////////////////////////// 192 size_t size() 193 { 194 return size_tab; 195 } 196 197 ///////////////////////////////////////////////////////////////////// 198 // The init() function initializes the transaction tab entries 199 ///////////////////////////////////////////////////////////////////// 200 void init() 201 { 202 for ( size_t i=0; i<size_tab; i++) { 203 tab[i].init(); 204 } 205 } 206 207 ///////////////////////////////////////////////////////////////////// 208 // The print() function prints a transaction tab entry 209 // Arguments : 210 // - index : the index of the entry to print 211 ///////////////////////////////////////////////////////////////////// 212 void print(const size_t index) 213 { 214 assert( (index < size_tab) 215 && "Invalid Transaction Tab Entry"); 216 tab[index].print(); 217 return; 218 } 219 220 ///////////////////////////////////////////////////////////////////// 221 // The read() function returns a transaction tab entry. 222 // Arguments : 223 // - index : the index of the entry to read 224 ///////////////////////////////////////////////////////////////////// 225 TransactionTabEntry read(const size_t index) 226 { 227 assert( (index < size_tab) 228 && "Invalid Transaction Tab Entry"); 229 return tab[index]; 230 } 231 232 ///////////////////////////////////////////////////////////////////// 233 // The full() function returns the state of the transaction tab 234 // Arguments : 235 // - index : (return argument) the index of an empty entry 236 // The function returns true if the transaction tab is full 237 ///////////////////////////////////////////////////////////////////// 238 bool full(size_t &index) 239 { 240 for(size_t i=0; i<size_tab; i++){ 241 if(!tab[i].valid){ 242 index=i; 243 return false; 244 } 245 } 246 return true; 247 } 248 249 ///////////////////////////////////////////////////////////////////// 250 // The hit_read() function checks if an XRAM read transaction exists 251 // for a given cache line. 252 // Arguments : 253 // - index : (return argument) the index of the hit entry, if there is 254 // - nline : the index (zy) of the requested line 255 // The function returns true if a read request has already been sent 256 ////////////////////////////////////////////////////////////////////// 257 bool hit_read(const addr_t nline,size_t &index) 258 { 259 for(size_t i=0; i<size_tab; i++){ 260 if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) { 261 index=i; 262 return true; 263 } 264 } 265 return false; 266 } 267 268 /////////////////////////////////////////////////////////////////////// 269 // The hit_write() function looks if an XRAM write transaction exists 270 // for a given line. 271 // Arguments : 272 // - nline : the index (zy) of the requested line 273 // The function returns true if a write request has already been sent 274 /////////////////////////////////////////////////////////////////////// 275 bool hit_write(const addr_t nline) 276 { 277 for(size_t i=0; i<size_tab; i++){ 278 if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) { 279 return true; 280 } 281 } 282 return false; 283 } 284 285 ///////////////////////////////////////////////////////////////////// 286 // The write_data_mask() function writes a vector of data (a line). 287 // The data is written only if the corresponding bits are set 288 // in the be vector. 289 // Arguments : 290 // - index : the index of the request in the transaction tab 291 // - be : vector of be 292 // - data : vector of data 293 ///////////////////////////////////////////////////////////////////// 294 void write_data_mask(const size_t index, 295 const std::vector<be_t> &be, 296 const std::vector<data_t> &data) 297 { 298 assert( (index < size_tab) 299 && "Invalid Transaction Tab Entry"); 300 assert(be.size()==tab[index].wdata_be.size() 301 && "Bad data mask in write_data_mask in TransactionTab"); 302 assert(data.size()==tab[index].wdata.size() 303 && "Bad data in write_data_mask in TransactionTab"); 304 305 for(size_t i=0; i<tab[index].wdata_be.size() ; i++) { 306 tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i]; 307 data_t mask = be_to_mask(be[i]); 308 tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask); 309 } 310 } 311 312 ///////////////////////////////////////////////////////////////////// 313 // The set() function registers a transaction (read or write) 314 // to the XRAM in the transaction tab. 315 // Arguments : 316 // - index : index in the transaction tab 317 // - xram_read : transaction type (read or write a cache line) 318 // - nline : the index (zy) of the cache line 319 // - srcid : srcid of the initiator that caused the transaction 320 // - trdid : trdid of the initiator that caused the transaction 321 // - pktid : pktid of the initiator that caused the transaction 322 // - proc_read : does the initiator want a copy 323 // - read_length : length of read (in case of processor read) 324 // - word_index : index in the line (in case of single word read) 325 // - data : the data to write (in case of write) 326 // - data_be : the mask of the data to write (in case of write) 327 ///////////////////////////////////////////////////////////////////// 328 void set(const size_t index, 329 const bool xram_read, 330 const addr_t nline, 331 const size_t srcid, 332 const size_t trdid, 333 const size_t pktid, 334 const bool proc_read, 335 const size_t read_length, 336 const size_t word_index, 337 const std::vector<be_t> &data_be, 338 const std::vector<data_t> &data) 339 { 340 assert( (index < size_tab) 341 && "The selected entry is out of range in set() Transaction Tab"); 342 assert(data_be.size()==tab[index].wdata_be.size() 343 && "Bad data_be argument in set() TransactionTab"); 344 assert(data.size()==tab[index].wdata.size() 345 && "Bad data argument in set() TransactionTab"); 346 347 tab[index].valid = true; 348 tab[index].xram_read = xram_read; 349 tab[index].nline = nline; 350 tab[index].srcid = srcid; 351 tab[index].trdid = trdid; 352 tab[index].pktid = pktid; 353 tab[index].proc_read = proc_read; 354 tab[index].read_length = read_length; 355 tab[index].word_index = word_index; 356 for(size_t i=0; i<tab[index].wdata.size(); i++) 357 { 358 tab[index].wdata_be[i] = data_be[i]; 359 tab[index].wdata[i] = data[i]; 360 } 361 } 362 363 ///////////////////////////////////////////////////////////////////// 364 // The write_rsp() function writes a word of the response to an 365 // XRAM read transaction. 366 // The BE field in TRT is taken into account. 367 // Arguments : 368 // - index : the index of the transaction in the transaction tab 369 // - word_index : the index of the data in the line 370 // - data : the data to write 371 // - error : invalid data 372 ///////////////////////////////////////////////////////////////////// 373 void write_rsp(const size_t index, 374 const size_t word, 375 const data_t data, 376 const bool rerror) 377 { 378 assert( (index < size_tab) 379 && "Selected entry out of range in write_rsp() Transaction Tab"); 380 assert( (word <= tab[index].wdata_be.size()) 381 && "Bad word_index in write_rsp() in TransactionTab"); 382 assert( tab[index].valid 383 && "Transaction Tab Entry invalid in write_rsp()"); 384 assert( tab[index].xram_read 385 && "Selected entry is not an XRAM read transaction in write_rsp()"); 386 387 data_t mask = be_to_mask(tab[index].wdata_be[word]); 388 tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask); 389 tab[index].rerror |= rerror; 390 } 391 392 ///////////////////////////////////////////////////////////////////// 393 // The erase() function erases an entry in the transaction tab. 394 // Arguments : 395 // - index : the index of the request in the transaction tab 396 ///////////////////////////////////////////////////////////////////// 397 void erase(const size_t index) 398 { 399 assert( (index < size_tab) 400 && "The selected entry is out of range in erase() Transaction Tab"); 401 tab[index].valid = false; 402 tab[index].rerror = false; 403 } 404 404 }; // end class TransactionTab 405 405 -
trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r247 r253 802 802 if( m_debug_tgt_cmd_fsm ) 803 803 { 804 std::cout << " <MEMC .TGT_CMD_IDLE> Receive command from srcid " << std::dec << p_vci_tgt.srcid.read()804 std::cout << " <MEMC " << name() << ".TGT_CMD_IDLE> Receive command from srcid " << std::dec << p_vci_tgt.srcid.read() 805 805 << " / for address " << std::hex << p_vci_tgt.address.read() << std::endl; 806 806 } … … 821 821 { 822 822 std::cout << "VCI_MEM_CACHE ERROR " << name() << std::endl; 823 std::cout << "Out of segment VCI address in TGT_CMD_IDLE state " << std::endl;823 std::cout << "Out of segment VCI address in TGT_CMD_IDLE state (address = " << std::hex << address << ", srcid = " << p_vci_tgt.srcid.read() << std::dec << ", cycle = " << m_cpt_cycles << ")" << std::endl; 824 824 exit(0); 825 825 } … … 869 869 if( m_debug_tgt_cmd_fsm ) 870 870 { 871 std::cout << " <MEMC .TGT_CMD_READ> Push into read_fifo:"871 std::cout << " <MEMC " << name() << ".TGT_CMD_READ> Push into read_fifo:" 872 872 << " address = " << std::hex << p_vci_tgt.address.read() 873 873 << " srcid = " << std::dec << p_vci_tgt.srcid.read() … … 891 891 if( m_debug_tgt_cmd_fsm ) 892 892 { 893 std::cout << " <MEMC .TGT_CMD_WRITE> Push into write_fifo:"893 std::cout << " <MEMC " << name() << ".TGT_CMD_WRITE> Push into write_fifo:" 894 894 << " address = " << std::hex << p_vci_tgt.address.read() 895 895 << " srcid = " << std::dec << p_vci_tgt.srcid.read() … … 921 921 if( m_debug_tgt_cmd_fsm ) 922 922 { 923 std::cout << " <MEMC .TGT_CMD_ATOMIC> Pushing command into cmd_sc_fifo:"923 std::cout << " <MEMC " << name() << ".TGT_CMD_ATOMIC> Pushing command into cmd_sc_fifo:" 924 924 << " address = " << std::hex << p_vci_tgt.address.read() 925 925 << " srcid = " << std::dec << p_vci_tgt.srcid.read() … … 969 969 if( m_debug_init_rsp_fsm ) 970 970 { 971 std::cout << " <MEMC .INIT_RSP_IDLE> Response for UPT entry "971 std::cout << " <MEMC " << name() << ".INIT_RSP_IDLE> Response for UPT entry " 972 972 << p_vci_ini.rtrdid.read() << std::endl; 973 973 } … … 1012 1012 if( m_debug_init_rsp_fsm ) 1013 1013 { 1014 std::cout << " <MEMC .INIT_RSP_UPT_LOCK> Decrement the responses counter for UPT:"1014 std::cout << " <MEMC " << name() << ".INIT_RSP_UPT_LOCK> Decrement the responses counter for UPT:" 1015 1015 << " entry = " << r_init_rsp_upt_index.read() 1016 1016 << " / rsp_count = " << std::dec << count << std::endl; … … 1049 1049 if ( m_debug_init_rsp_fsm ) 1050 1050 { 1051 std::cout << " <MEMC .INIT_RSP_UPT_CLEAR> Clear UPT entry "1051 std::cout << " <MEMC " << name() << ".INIT_RSP_UPT_CLEAR> Clear UPT entry " 1052 1052 << r_init_rsp_upt_index.read() << std::endl; 1053 1053 } … … 1070 1070 if ( m_debug_init_rsp_fsm ) 1071 1071 { 1072 std::cout << " <MEMC .INIT_RSP_END> Request TGT_RSP FSM to send a response to srcid "1072 std::cout << " <MEMC " << name() << ".INIT_RSP_END> Request TGT_RSP FSM to send a response to srcid " 1073 1073 << r_init_rsp_srcid.read() << std::endl; 1074 1074 } … … 1113 1113 if( m_debug_read_fsm ) 1114 1114 { 1115 std::cout << " <MEMC .READ_IDLE> Read request:"1115 std::cout << " <MEMC " << name() << ".READ_IDLE> Read request:" 1116 1116 << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1117 1117 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() … … 1162 1162 if( m_debug_read_fsm ) 1163 1163 { 1164 std::cout << " <MEMC .READ_DIR_LOCK> Accessing directory: "1164 std::cout << " <MEMC " << name() << ".READ_DIR_LOCK> Accessing directory: " 1165 1165 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1166 1166 << " / hit = " << std::dec << entry.valid … … 1233 1233 if( m_debug_read_fsm ) 1234 1234 { 1235 std::cout << " <MEMC .READ_DIR_HIT> Update directory entry:"1235 std::cout << " <MEMC " << name() << ".READ_DIR_HIT> Update directory entry:" 1236 1236 << " set = " << std::dec << set 1237 1237 << " / way = " << way … … 1329 1329 if( m_debug_read_fsm ) 1330 1330 { 1331 std::cout << " <MEMC .READ_HEAP_LOCK> Update directory:"1331 std::cout << " <MEMC " << name() << ".READ_HEAP_LOCK> Update directory:" 1332 1332 << " tag = " << std::hex << entry.tag 1333 1333 << " set = " << std::dec << set … … 1369 1369 if( m_debug_read_fsm ) 1370 1370 { 1371 std::cout << " <MEMC .READ_HEAP_WRITE> Add an entry in the heap:"1371 std::cout << " <MEMC " << name() << ".READ_HEAP_WRITE> Add an entry in the heap:" 1372 1372 << " owner_id = " << heap_entry.owner.srcid 1373 1373 << " owner_ins = " << heap_entry.owner.inst << std::endl; … … 1460 1460 if( m_debug_read_fsm ) 1461 1461 { 1462 std::cout << " <MEMC .READ_RSP> Request the TGT_RSP FSM to return data:"1462 std::cout << " <MEMC " << name() << ".READ_RSP> Request the TGT_RSP FSM to return data:" 1463 1463 << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1464 1464 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() … … 1496 1496 if( m_debug_read_fsm ) 1497 1497 { 1498 std::cout << " <MEMC .READ_TRT_LOCK> Check TRT:"1498 std::cout << " <MEMC " << name() << ".READ_TRT_LOCK> Check TRT:" 1499 1499 << " hit_read = " << hit_read 1500 1500 << " / hit_write = " << hit_write … … 1524 1524 if( m_debug_read_fsm ) 1525 1525 { 1526 std::cout << " <MEMC .READ_TRT_SET> Write in Transaction Table: " << std::hex1526 std::cout << " <MEMC " << name() << ".READ_TRT_SET> Write in Transaction Table: " << std::hex 1527 1527 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1528 1528 << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() … … 1549 1549 if( m_debug_read_fsm ) 1550 1550 { 1551 std::cout << " <MEMC .READ_TRT_REQ> Request GET transaction for address "1551 std::cout << " <MEMC " << name() << ".READ_TRT_REQ> Request GET transaction for address " 1552 1552 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; 1553 1553 } … … 1629 1629 if( m_debug_write_fsm ) 1630 1630 { 1631 std::cout << " <MEMC .WRITE_IDLE> Write request "1631 std::cout << " <MEMC " << name() << ".WRITE_IDLE> Write request " 1632 1632 << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() 1633 1633 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() … … 1647 1647 if( m_debug_write_fsm ) 1648 1648 { 1649 std::cout << " <MEMC .WRITE_NEXT> Write another word in local buffer" << std::endl;1649 std::cout << " <MEMC " << name() << ".WRITE_NEXT> Write another word in local buffer" << std::endl; 1650 1650 } 1651 1651 #endif … … 1717 1717 if( m_debug_write_fsm ) 1718 1718 { 1719 std::cout << " <MEMC .WRITE_DIR_LOCK> Check the directory: "1719 std::cout << " <MEMC " << name() << ".WRITE_DIR_LOCK> Check the directory: " 1720 1720 << " address = " << std::hex << r_write_address.read() 1721 1721 << " hit = " << std::dec << entry.valid … … 1756 1756 if( m_debug_write_fsm ) 1757 1757 { 1758 std::cout << " <MEMC .WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;1758 std::cout << " <MEMC " << name() << ".WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl; 1759 1759 } 1760 1760 #endif … … 1832 1832 if ( no_update ) 1833 1833 { 1834 std::cout << " <MEMC .WRITE_DIR_HIT> Write into cache / No coherence transaction"1834 std::cout << " <MEMC " << name() << ".WRITE_DIR_HIT> Write into cache / No coherence transaction" 1835 1835 << std::endl; 1836 1836 } 1837 1837 else 1838 1838 { 1839 std::cout << " <MEMC .WRITE_DIR_HIT> Coherence update required:"1839 std::cout << " <MEMC " << name() << ".WRITE_DIR_HIT> Coherence update required:" 1840 1840 << " is_cnt = " << r_write_is_cnt.read() 1841 1841 << " nb_copies = " << std::dec << r_write_count.read() << std::endl; … … 1895 1895 if ( wok ) 1896 1896 { 1897 std::cout << " <MEMC .WRITE_UPT_LOCK> Register the multicast update in UPT / "1897 std::cout << " <MEMC " << name() << ".WRITE_UPT_LOCK> Register the multicast update in UPT / " 1898 1898 << " nb_copies = " << r_write_count.read() << std::endl; 1899 1899 } … … 1916 1916 if( m_debug_write_fsm ) 1917 1917 { 1918 std::cout << " <MEMC .WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;1918 std::cout << " <MEMC " << name() << ".WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl; 1919 1919 } 1920 1920 #endif … … 1977 1977 if( m_debug_write_fsm ) 1978 1978 { 1979 std::cout << " <MEMC .WRITE_UPT_REQ> Post first request to INIT_CMD FSM"1979 std::cout << " <MEMC " << name() << ".WRITE_UPT_REQ> Post first request to INIT_CMD FSM" 1980 1980 << " / srcid = " << std::dec << r_write_copy.read() 1981 1981 << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; … … 2018 2018 if( m_debug_write_fsm ) 2019 2019 { 2020 std::cout << " <MEMC .WRITE_UPT_NEXT> Post another request to INIT_CMD FSM"2020 std::cout << " <MEMC " << name() << ".WRITE_UPT_NEXT> Post another request to INIT_CMD FSM" 2021 2021 << " / heap_index = " << std::dec << r_write_ptr.read() 2022 2022 << " / srcid = " << std::dec << r_write_copy.read() … … 2034 2034 if( m_debug_write_fsm ) 2035 2035 { 2036 std::cout << " <MEMC .WRITE_UPT_NEXT> Skip one entry in heap matching the writer"2036 std::cout << " <MEMC " << name() << ".WRITE_UPT_NEXT> Skip one entry in heap matching the writer" 2037 2037 << " / heap_index = " << std::dec << r_write_ptr.read() 2038 2038 << " / srcid = " << std::dec << r_write_copy.read() … … 2133 2133 if( m_debug_write_fsm ) 2134 2134 { 2135 std::cout << " <MEMC .WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "2135 std::cout << " <MEMC " << name() << ".WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = " 2136 2136 << std::dec << r_write_srcid.read() << std::endl; 2137 2137 if ( m_cmd_write_addr_fifo.rok() ) … … 2156 2156 if( m_debug_write_fsm ) 2157 2157 { 2158 std::cout << " <MEMC .WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;2158 std::cout << " <MEMC " << name() << ".WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl; 2159 2159 } 2160 2160 #endif … … 2193 2193 if( m_debug_write_fsm ) 2194 2194 { 2195 std::cout << " <MEMC .WRITE_WAIT> Releases the locks before retry" << std::endl;2195 std::cout << " <MEMC " << name() << ".WRITE_WAIT> Releases the locks before retry" << std::endl; 2196 2196 } 2197 2197 #endif … … 2229 2229 if( m_debug_write_fsm ) 2230 2230 { 2231 std::cout << " <MEMC .WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;2231 std::cout << " <MEMC " << name() << ".WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl; 2232 2232 } 2233 2233 #endif … … 2257 2257 if( m_debug_write_fsm ) 2258 2258 { 2259 std::cout << " <MEMC .WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;2259 std::cout << " <MEMC " << name() << ".WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl; 2260 2260 m_transaction_tab.print( r_write_trt_index.read() ); 2261 2261 } … … 2278 2278 if( m_debug_write_fsm ) 2279 2279 { 2280 std::cout << " <MEMC .WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;2280 std::cout << " <MEMC " << name() << ".WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl; 2281 2281 } 2282 2282 #endif … … 2304 2304 if( m_debug_write_fsm ) 2305 2305 { 2306 std::cout << " <MEMC .WRITE_BC_TRT_LOCK> Check TRT : wok = "2306 std::cout << " <MEMC " << name() << ".WRITE_BC_TRT_LOCK> Check TRT : wok = " 2307 2307 << wok << " / index = " << wok_index << std::endl; 2308 2308 } … … 2339 2339 if ( wok ) 2340 2340 { 2341 std::cout << " <MEMC .WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "2341 std::cout << " <MEMC " << name() << ".WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / " 2342 2342 << " nb_copies = " << r_write_count.read() << std::endl; 2343 2343 } … … 2398 2398 if( m_debug_write_fsm ) 2399 2399 { 2400 std::cout << " <MEMC .WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "2400 std::cout << " <MEMC " << name() << ".WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = " 2401 2401 << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; 2402 2402 } … … 2427 2427 if( m_debug_write_fsm ) 2428 2428 { 2429 std::cout << " <MEMC .WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl;2429 std::cout << " <MEMC " << name() << ".WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl; 2430 2430 } 2431 2431 #endif … … 2450 2450 if( m_debug_write_fsm ) 2451 2451 { 2452 std::cout << " <MEMC .WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;2452 std::cout << " <MEMC " << name() << ".WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl; 2453 2453 } 2454 2454 #endif … … 2514 2514 if( m_debug_ixr_cmd_fsm ) 2515 2515 { 2516 std::cout << " <MEMC .IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;2516 std::cout << " <MEMC " << name() << ".IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl; 2517 2517 } 2518 2518 #endif … … 2539 2539 if( m_debug_ixr_cmd_fsm ) 2540 2540 { 2541 std::cout << " <MEMC .IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;2541 std::cout << " <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl; 2542 2542 } 2543 2543 #endif … … 2551 2551 if( m_debug_ixr_cmd_fsm ) 2552 2552 { 2553 std::cout << " <MEMC .IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;2553 std::cout << " <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl; 2554 2554 } 2555 2555 #endif … … 2577 2577 if( m_debug_ixr_cmd_fsm ) 2578 2578 { 2579 std::cout << " <MEMC .IXR_CMD_SC_NLINE> Send a put request to xram" << std::endl;2579 std::cout << " <MEMC " << name() << ".IXR_CMD_SC_NLINE> Send a put request to xram" << std::endl; 2580 2580 } 2581 2581 #endif … … 2589 2589 if( m_debug_ixr_cmd_fsm ) 2590 2590 { 2591 std::cout << " <MEMC .IXR_CMD_SC_NLINE> Send a get request to xram" << std::endl;2591 std::cout << " <MEMC " << name() << ".IXR_CMD_SC_NLINE> Send a get request to xram" << std::endl; 2592 2592 } 2593 2593 #endif … … 2613 2613 if( m_debug_ixr_cmd_fsm ) 2614 2614 { 2615 std::cout << " <MEMC .IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;2615 std::cout << " <MEMC " << name() << ".IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl; 2616 2616 } 2617 2617 #endif … … 2656 2656 if( m_debug_ixr_rsp_fsm ) 2657 2657 { 2658 std::cout << " <MEMC .IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;2658 std::cout << " <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl; 2659 2659 } 2660 2660 #endif … … 2667 2667 if( m_debug_ixr_rsp_fsm ) 2668 2668 { 2669 std::cout << " <MEMC .IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;2669 std::cout << " <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; 2670 2670 } 2671 2671 #endif … … 2682 2682 if( m_debug_ixr_rsp_fsm ) 2683 2683 { 2684 std::cout << " <MEMC .IXR_RSP_ACK>" << std::endl;2684 std::cout << " <MEMC " << name() << ".IXR_RSP_ACK>" << std::endl; 2685 2685 } 2686 2686 #endif … … 2698 2698 if( m_debug_ixr_rsp_fsm ) 2699 2699 { 2700 std::cout << " <MEMC .IXR_RSP_TRT_ERASE> Erase TRT entry "2700 std::cout << " <MEMC " << name() << ".IXR_RSP_TRT_ERASE> Erase TRT entry " 2701 2701 << r_ixr_rsp_trt_index.read() << std::endl; 2702 2702 } … … 2730 2730 if( m_debug_ixr_rsp_fsm ) 2731 2731 { 2732 std::cout << " <MEMC .IXR_RSP_TRT_READ> Writing a word in TRT : "2732 std::cout << " <MEMC " << name() << ".IXR_RSP_TRT_READ> Writing a word in TRT : " 2733 2733 << " index = " << std::dec << index 2734 2734 << " / word = " << r_ixr_rsp_cpt.read() … … 2783 2783 if( m_debug_xram_rsp_fsm ) 2784 2784 { 2785 std::cout << " <MEMC .XRAM_RSP_IDLE> Available cache line in TRT:"2785 std::cout << " <MEMC " << name() << ".XRAM_RSP_IDLE> Available cache line in TRT:" 2786 2786 << " index = " << std::dec << index << std::endl; 2787 2787 } … … 2802 2802 if( m_debug_xram_rsp_fsm ) 2803 2803 { 2804 std::cout << " <MEMC .XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;2804 std::cout << " <MEMC " << name() << ".XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl; 2805 2805 } 2806 2806 #endif … … 2850 2850 if( m_debug_xram_rsp_fsm ) 2851 2851 { 2852 std::cout << " <MEMC .XRAM_RSP_TRT_COPY> Select a slot: "2852 std::cout << " <MEMC " << name() << ".XRAM_RSP_TRT_COPY> Select a slot: " 2853 2853 << " way = " << std::dec << way 2854 2854 << " / set = " << set … … 2872 2872 if( m_debug_xram_rsp_fsm ) 2873 2873 { 2874 std::cout << " <MEMC .XRAM_RSP_INVAL_LOCK> Get acces to UPT,"2874 std::cout << " <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT," 2875 2875 << " but an invalidation is already registered at this address" << std::endl; 2876 2876 m_update_tab.print(); … … 2886 2886 if( m_debug_xram_rsp_fsm ) 2887 2887 { 2888 std::cout << " <MEMC .XRAM_RSP_INVAL_LOCK> Get acces to UPT,"2888 std::cout << " <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT," 2889 2889 << " but the table is full" << std::endl; 2890 2890 m_update_tab.print(); … … 2899 2899 if( m_debug_xram_rsp_fsm ) 2900 2900 { 2901 std::cout << " <MEMC .XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;2901 std::cout << " <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl; 2902 2902 } 2903 2903 #endif … … 2991 2991 if( m_debug_xram_rsp_fsm ) 2992 2992 { 2993 std::cout << " <MEMC .XRAM_RSP_DIR_UPDT> Directory update: "2993 std::cout << " <MEMC " << name() << ".XRAM_RSP_DIR_UPDT> Directory update: " 2994 2994 << " way = " << std::dec << way 2995 2995 << " / set = " << set … … 3034 3034 if( m_debug_xram_rsp_fsm ) 3035 3035 { 3036 std::cout << " <MEMC .XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"3036 std::cout << " <MEMC " << name() << ".XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:" 3037 3037 << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3038 3038 } … … 3066 3066 if( m_debug_xram_rsp_fsm ) 3067 3067 { 3068 std::cout << " <MEMC .XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:"3068 std::cout << " <MEMC " << name() << ".XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:" 3069 3069 << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid 3070 3070 << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 … … 3104 3104 if( m_debug_xram_rsp_fsm ) 3105 3105 { 3106 std::cout << " <MEMC .XRAM_RSP_INVAL> Send an inval request to INIT_CMD FSM:"3106 std::cout << " <MEMC " << name() << ".XRAM_RSP_INVAL> Send an inval request to INIT_CMD FSM:" 3107 3107 << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3108 3108 } … … 3130 3130 if( m_debug_xram_rsp_fsm ) 3131 3131 { 3132 std::cout << " <MEMC .XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:"3132 std::cout << " <MEMC " << name() << ".XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:" 3133 3133 << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3134 3134 } … … 3171 3171 if( m_debug_xram_rsp_fsm ) 3172 3172 { 3173 std::cout << " <MEMC .XRAM_RSP_HEAP_ERASE> Erase the list of copies:"3173 std::cout << " <MEMC " << name() << ".XRAM_RSP_HEAP_ERASE> Erase the list of copies:" 3174 3174 << " srcid = " << std::dec << entry.owner.srcid 3175 3175 << " / inst = " << std::dec << entry.owner.inst << std::endl; … … 3214 3214 if( m_debug_xram_rsp_fsm ) 3215 3215 { 3216 std::cout << " <MEMC .XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;3216 std::cout << " <MEMC " << name() << ".XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl; 3217 3217 } 3218 3218 #endif … … 3231 3231 if( m_debug_xram_rsp_fsm ) 3232 3232 { 3233 std::cout << " <MEMC .XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;3233 std::cout << " <MEMC " << name() << ".XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl; 3234 3234 } 3235 3235 #endif … … 3255 3255 if( m_debug_xram_rsp_fsm ) 3256 3256 { 3257 std::cout << " <MEMC .XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"3257 std::cout << " <MEMC " << name() << ".XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:" 3258 3258 << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; 3259 3259 } … … 3309 3309 if( m_debug_cleanup_fsm ) 3310 3310 { 3311 std::cout << " <MEMC .CLEANUP_IDLE> Cleanup request:" << std::hex3312 << " line = " << line * m_words * 43311 std::cout << " <MEMC " << name() << ".CLEANUP_IDLE> Cleanup request:" << std::hex 3312 << " line addr = " << line * m_words * 4 3313 3313 << " / owner_id = " << p_vci_tgt_cleanup.srcid.read() 3314 3314 << " / owner_ins = " << (p_vci_tgt_cleanup.trdid.read()&0x1) … … 3362 3362 if( m_debug_cleanup_fsm ) 3363 3363 { 3364 std::cout << " <MEMC .CLEANUP_DIR_LOCK> Test directory status: " << std::hex3364 std::cout << " <MEMC " << name() << ".CLEANUP_DIR_LOCK> Test directory status: " << std::hex 3365 3365 << " line = " << r_cleanup_nline.read() * m_words * 4 3366 3366 << " / hit = " << entry.valid … … 3446 3446 if( m_debug_cleanup_fsm ) 3447 3447 { 3448 std::cout << " <MEMC .CLEANUP_DIR_WRITE> Update directory:" << std::hex3448 std::cout << " <MEMC " << name() << ".CLEANUP_DIR_WRITE> Update directory:" << std::hex 3449 3449 << " line = " << r_cleanup_nline.read() * m_words * 4 3450 3450 << " / dir_id = " << entry.owner.srcid … … 3567 3567 if( m_debug_cleanup_fsm ) 3568 3568 { 3569 std::cout << " <MEMC .CLEANUP_HEAP_LOCK> Checks matching:"3569 std::cout << " <MEMC " << name() << ".CLEANUP_HEAP_LOCK> Checks matching:" 3570 3570 << " line = " << r_cleanup_nline.read() * m_words * 4 3571 3571 << " / dir_id = " << r_cleanup_copy.read() … … 3605 3605 if( m_debug_cleanup_fsm ) 3606 3606 { 3607 std::cout << " <MEMC .CLEANUP_HEAP_SEARCH> Cheks matching:"3607 std::cout << " <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Cheks matching:" 3608 3608 << " line = " << r_cleanup_nline.read() * m_words * 4 3609 3609 << " / heap_id = " << heap_entry.owner.srcid … … 3642 3642 if( m_debug_cleanup_fsm ) 3643 3643 { 3644 std::cout << " <MEMC .CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"3644 std::cout << " <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Matching copy not found, search next:" 3645 3645 << " line = " << r_cleanup_nline.read() * m_words * 4 3646 3646 << " / heap_id = " << heap_entry.owner.srcid … … 3686 3686 if( m_debug_cleanup_fsm ) 3687 3687 { 3688 std::cout << " <MEMC .CLEANUP_HEAP_SEARCH> Remove the copy in the linked list" << std::endl;3688 std::cout << " <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Remove the copy in the linked list" << std::endl; 3689 3689 } 3690 3690 #endif … … 3719 3719 if( m_debug_cleanup_fsm ) 3720 3720 { 3721 std::cout << " <MEMC .CLEANUP_HEAP_SEARCH> Update the list of free entries" << std::endl;3721 std::cout << " <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Update the list of free entries" << std::endl; 3722 3722 } 3723 3723 #endif … … 3739 3739 if( m_debug_cleanup_fsm ) 3740 3740 { 3741 std::cout << " <MEMC .CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry:"3741 std::cout << " <MEMC " << name() << ".CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry:" 3742 3742 << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl; 3743 3743 } … … 3769 3769 if( m_debug_cleanup_fsm ) 3770 3770 { 3771 std::cout << " <MEMC .CLEANUP_UPT_WRITE> Decrement response counter in UPT:"3771 std::cout << " <MEMC " << name() << ".CLEANUP_UPT_WRITE> Decrement response counter in UPT:" 3772 3772 << " UPT_index = " << r_cleanup_index.read() 3773 3773 << " rsp_count = " << count << std::endl; … … 3797 3797 if( m_debug_cleanup_fsm ) 3798 3798 { 3799 std::cout << " <MEMC .CLEANUP_WRITE_RSP> Send a response to a cleanup request:"3799 std::cout << " <MEMC " << name() << ".CLEANUP_WRITE_RSP> Send a response to a cleanup request:" 3800 3800 << " rsrcid = " << std::dec << r_cleanup_write_srcid.read() 3801 3801 << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read() << std::endl; … … 3815 3815 if( m_debug_cleanup_fsm ) 3816 3816 { 3817 std::cout << " <MEMC .CLEANUP_RSP> Send the response to a cleanup request:"3817 std::cout << " <MEMC " << name() << ".CLEANUP_RSP> Send the response to a cleanup request:" 3818 3818 << " rsrcid = " << std::dec << r_cleanup_write_srcid.read() 3819 3819 << " / rtrdid = " << r_cleanup_write_trdid.read() << std::endl; … … 3861 3861 if( m_debug_sc_fsm ) 3862 3862 { 3863 std::cout << " <MEMC .SC_IDLE> SC command: " << std::hex3863 std::cout << " <MEMC " << name() << ".SC_IDLE> SC command: " << std::hex 3864 3864 << " srcid = " << std::dec << m_cmd_sc_srcid_fifo.read() 3865 3865 << " addr = " << std::hex << m_cmd_sc_addr_fifo.read() … … 3925 3925 if( m_debug_sc_fsm ) 3926 3926 { 3927 std::cout << " <MEMC .SC_DIR_LOCK> Directory acces"3927 std::cout << " <MEMC " << name() << ".SC_DIR_LOCK> Directory acces" 3928 3928 << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() 3929 3929 << " / hit = " << std::dec << entry.valid … … 3981 3981 if( m_debug_sc_fsm ) 3982 3982 { 3983 std::cout << " <MEMC .SC_DIR_HIT_READ> Test if SC success:"3983 std::cout << " <MEMC " << name() << ".SC_DIR_HIT_READ> Test if SC success:" 3984 3984 << " / expected value = " << r_sc_rdata[0].read() 3985 3985 << " / actual value = " << m_cache_data[way][set][word] … … 4036 4036 if( m_debug_sc_fsm ) 4037 4037 { 4038 std::cout << " <MEMC .SC_DIR_HIT_WRITE> Update cache:"4038 std::cout << " <MEMC " << name() << ".SC_DIR_HIT_WRITE> Update cache:" 4039 4039 << " way = " << std::dec << way 4040 4040 << " / set = " << set … … 4104 4104 if( m_debug_sc_fsm ) 4105 4105 { 4106 std::cout << " <MEMC .SC_UPT_LOCK> Register multi-update transaction in UPT"4106 std::cout << " <MEMC " << name() << ".SC_UPT_LOCK> Register multi-update transaction in UPT" 4107 4107 << " / wok = " << wok 4108 4108 << " / nline = " << std::hex << nline … … 4120 4120 if( m_debug_sc_fsm ) 4121 4121 { 4122 std::cout << " <MEMC .SC_WAIT> Release all locks" << std::endl;4122 std::cout << " <MEMC " << name() << ".SC_WAIT> Release all locks" << std::endl; 4123 4123 } 4124 4124 #endif … … 4135 4135 if( m_debug_sc_fsm ) 4136 4136 { 4137 std::cout << " <MEMC .SC_UPT_HEAP_LOCK> Get access to the heap" << std::endl;4137 std::cout << " <MEMC " << name() << ".SC_UPT_HEAP_LOCK> Get access to the heap" << std::endl; 4138 4138 } 4139 4139 #endif … … 4190 4190 if( m_debug_sc_fsm ) 4191 4191 { 4192 std::cout << " <MEMC .SC_UPT_REQ> Send the first update request to INIT_CMD FSM "4192 std::cout << " <MEMC " << name() << ".SC_UPT_REQ> Send the first update request to INIT_CMD FSM " 4193 4193 << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() 4194 4194 << " / wdata = " << std::hex << r_sc_wdata.read() … … 4230 4230 if( m_debug_sc_fsm ) 4231 4231 { 4232 std::cout << " <MEMC .SC_UPT_NEXT> Send the next update request to INIT_CMD FSM "4232 std::cout << " <MEMC " << name() << ".SC_UPT_NEXT> Send the next update request to INIT_CMD FSM " 4233 4233 << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() 4234 4234 << " / wdata = " << std::hex << r_sc_wdata.read() … … 4335 4335 if( m_debug_sc_fsm ) 4336 4336 { 4337 std::cout << " <MEMC .SC_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"4337 std::cout << " <MEMC " << name() << ".SC_BC_UPT_LOCK> Register a broadcast inval transaction in UPT" 4338 4338 << " / nline = " << nline 4339 4339 << " / count = " << nb_copies … … 4392 4392 if( m_debug_sc_fsm ) 4393 4393 { 4394 std::cout << " <MEMC .SC_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"4394 std::cout << " <MEMC " << name() << ".SC_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry" 4395 4395 << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())] 4396 4396 << " / set = " << std::dec << set << " / way = " << way << std::endl; … … 4437 4437 if( m_debug_sc_fsm ) 4438 4438 { 4439 std::cout << " <MEMC .SC_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex4439 std::cout << " <MEMC " << name() << ".SC_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex 4440 4440 << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] 4441 4441 << " / trt_index = " << r_sc_trt_index.read() << std::endl; … … 4467 4467 if( m_debug_sc_fsm ) 4468 4468 { 4469 std::cout << " <MEMC .SC_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;4469 std::cout << " <MEMC " << name() << ".SC_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl; 4470 4470 } 4471 4471 #endif … … 4490 4490 if( m_debug_sc_fsm ) 4491 4491 { 4492 std::cout << " <MEMC .SC_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;4492 std::cout << " <MEMC " << name() << ".SC_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl; 4493 4493 } 4494 4494 #endif … … 4511 4511 if( m_debug_sc_fsm ) 4512 4512 { 4513 std::cout << " <MEMC .SC_MISS_TRT_LOCK> Check TRT state"4513 std::cout << " <MEMC " << name() << ".SC_MISS_TRT_LOCK> Check TRT state" 4514 4514 << " / hit_read = " << hit_read 4515 4515 << " / hit_write = " << hit_write … … 4562 4562 if( m_debug_sc_fsm ) 4563 4563 { 4564 std::cout << " <MEMC .SC_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex4564 std::cout << " <MEMC " << name() << ".SC_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex 4565 4565 << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] 4566 4566 << " / trt_index = " << r_sc_trt_index.read() << std::endl; … … 4584 4584 if( m_debug_sc_fsm ) 4585 4585 { 4586 std::cout << " <MEMC .SC_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex4586 std::cout << " <MEMC " << name() << ".SC_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex 4587 4587 << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] 4588 4588 << " / trt_index = " << r_sc_trt_index.read() << std::endl; … … 4773 4773 if( m_debug_init_cmd_fsm ) 4774 4774 { 4775 std::cout << " <MEMC .INIT_CMD_WRITE_BRDCAST> Broadcast-Inval for line "4775 std::cout << " <MEMC " << name() << ".INIT_CMD_WRITE_BRDCAST> Broadcast-Inval for line " 4776 4776 << r_write_to_init_cmd_nline.read() << std::endl; 4777 4777 } … … 5031 5031 if( m_debug_tgt_rsp_fsm ) 5032 5032 { 5033 std::cout << " <MEMC .TGT_RSP_READ> Read response"5033 std::cout << " <MEMC " << name() << ".TGT_RSP_READ> Read response" 5034 5034 << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read() 5035 5035 << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() … … 5059 5059 if( m_debug_tgt_rsp_fsm ) 5060 5060 { 5061 std::cout << " <MEMC .TGT_RSP_WRITE> Write response"5061 std::cout << " <MEMC " << name() << ".TGT_RSP_WRITE> Write response" 5062 5062 << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read() 5063 5063 << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() << std::endl; … … 5078 5078 if( m_debug_tgt_rsp_fsm ) 5079 5079 { 5080 std::cout << " <MEMC .TGT_RSP_CLEANUP> Cleanup response"5080 std::cout << " <MEMC " << name() << ".TGT_RSP_CLEANUP> Cleanup response" 5081 5081 << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read() 5082 5082 << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() << std::endl; … … 5097 5097 if( m_debug_tgt_rsp_fsm ) 5098 5098 { 5099 std::cout << " <MEMC .TGT_RSP_SC> SC response"5099 std::cout << " <MEMC " << name() << ".TGT_RSP_SC> SC response" 5100 5100 << " / rsrcid = " << std::dec << r_sc_to_tgt_rsp_srcid.read() 5101 5101 << " / rtrdid = " << r_sc_to_tgt_rsp_trdid.read() << std::endl; … … 5117 5117 if( m_debug_tgt_rsp_fsm ) 5118 5118 { 5119 std::cout << " <MEMC .TGT_RSP_XRAM> Response following XRAM access"5119 std::cout << " <MEMC " << name() << ".TGT_RSP_XRAM> Response following XRAM access" 5120 5120 << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read() 5121 5121 << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() … … 5147 5147 if( m_debug_tgt_rsp_fsm ) 5148 5148 { 5149 std::cout << " <MEMC .TGT_RSP_INIT> Write response after coherence transaction"5149 std::cout << " <MEMC " << name() << ".TGT_RSP_INIT> Write response after coherence transaction" 5150 5150 << " / rsrcid = " << std::dec << r_init_rsp_to_tgt_rsp_srcid.read() 5151 5151 << " / rtrdid = " << r_init_rsp_to_tgt_rsp_trdid.read() << std::endl;
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