Index: trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h	(revision 247)
+++ trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h	(revision 253)
@@ -1,5 +1,5 @@
 #ifndef XRAM_TRANSACTION_V4_H_
 #define XRAM_TRANSACTION_V4_H_
- 
+
 #include <inttypes.h>
 #include <systemc>
@@ -14,118 +14,118 @@
 
 class TransactionTabEntry {
-  typedef uint32_t              size_t;
-  typedef uint32_t              data_t;
-  typedef sc_dt::sc_uint<40>    addr_t;
-  typedef uint32_t              be_t;
-
- public:
-  bool 		            valid;     	    // entry valid 
-  bool 		            xram_read; 	    // read request to XRAM
-  addr_t   	            nline;    	    // index (zy) of the requested line
-  size_t 	            srcid;     	    // processor requesting the transaction
-  size_t 	            trdid;     	    // processor requesting the transaction
-  size_t 	            pktid;     	    // processor requesting the transaction
-  bool 		            proc_read;	    // read request from processor
-  size_t 	            read_length;    // length of the read (for the response)
-  size_t 	            word_index;    	// index of the first read word (for the response)
-  std::vector<data_t>   wdata;          // write buffer (one cache line)
-  std::vector<be_t>     wdata_be;    	// be for each data in the write buffer
-  bool                  rerror;         // error returned by xram
-
-  /////////////////////////////////////////////////////////////////////
-  // The init() function initializes the entry 
-  /////////////////////////////////////////////////////////////////////
-  void init()
-  {
-    valid		= false;
-    rerror      = false;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The alloc() function initializes the vectors of an entry
-  // Its arguments are :
-  // - n_words : number of words per line in the cache
-  /////////////////////////////////////////////////////////////////////
-  void alloc(size_t n_words)
-  {
-    wdata_be.reserve( (int)n_words );
-    wdata.reserve( (int)n_words );
-    for(size_t i=0; i<n_words; i++)
-    {
-      wdata_be.push_back(0);
-      wdata.push_back(0);
-    }
-  }
-
-  ////////////////////////////////////////////////////////////////////
-  // The copy() function copies an existing entry
-  // Its arguments are :
-  // - source : the transaction tab entry to copy
-  ////////////////////////////////////////////////////////////////////
-  void copy(const TransactionTabEntry &source)
-  {
-    valid	    = source.valid;
-    xram_read 	= source.xram_read;
-    nline	    = source.nline;
-    srcid	    = source.srcid;
-    trdid	    = source.trdid;
-    pktid	    = source.pktid;
-    proc_read 	= source.proc_read;
-    read_length = source.read_length;
-    word_index	= source.word_index;
-    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
-    wdata.assign(source.wdata.begin(),source.wdata.end());
-    rerror      = source.rerror;
-  }
-
-  ////////////////////////////////////////////////////////////////////
-  // The print() function prints the entry 
-  ////////////////////////////////////////////////////////////////////
-  void print(){
-    std::cout << "valid       = " << valid        << std::endl;
-    std::cout << "xram_read   = " << xram_read    << std::endl;
-    std::cout << "nline       = " << std::hex << nline << std::endl;
-    std::cout << "srcid       = " << srcid        << std::endl;
-    std::cout << "trdid       = " << trdid        << std::endl;
-    std::cout << "pktid       = " << pktid        << std::endl;
-    std::cout << "proc_read   = " << proc_read    << std::endl;
-    std::cout << "read_length = " << read_length  << std::endl;
-    std::cout << "word_index  = " << word_index   << std::endl; 
-    for(size_t i=0; i<wdata_be.size() ; i++){
-      std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
-    }
-    for(size_t i=0; i<wdata.size() ; i++){
-      std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
-    }
-    std::cout << std::endl;
-    std::cout << "rerror      = " << rerror       << std::endl;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // 		Constructors
-  /////////////////////////////////////////////////////////////////////
-
-  TransactionTabEntry()
-    {
-      wdata_be.clear();
-      wdata.clear();
-      valid=false;
-      rerror=false;
-    }
-
-  TransactionTabEntry(const TransactionTabEntry &source){
-    valid	    = source.valid;
-    xram_read	= source.xram_read;
-    nline	    = source.nline;
-    srcid	    = source.srcid;
-    trdid	    = source.trdid;
-    pktid	    = source.pktid;
-    proc_read	= source.proc_read;
-    read_length = source.read_length;
-    word_index	= source.word_index;
-    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
-    wdata.assign(source.wdata.begin(),source.wdata.end());	
-    rerror      = source.rerror;
-  }
+    typedef uint32_t              size_t;
+    typedef uint32_t              data_t;
+    typedef sc_dt::sc_uint<40>    addr_t;
+    typedef uint32_t              be_t;
+
+    public:
+    bool 		        valid;     	    // entry valid 
+    bool 		        xram_read; 	    // read request to XRAM
+    addr_t   	        nline;    	    // index (zy) of the requested line
+    size_t 	            srcid;     	    // processor requesting the transaction
+    size_t 	            trdid;     	    // processor requesting the transaction
+    size_t 	            pktid;     	    // processor requesting the transaction
+    bool 		        proc_read;	    // read request from processor
+    size_t 	            read_length;    // length of the read (for the response)
+    size_t 	            word_index;    	// index of the first read word (for the response)
+    std::vector<data_t> wdata;          // write buffer (one cache line)
+    std::vector<be_t>   wdata_be;    	// be for each data in the write buffer
+    bool                rerror;         // error returned by xram
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+        valid		= false;
+        rerror      = false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The alloc() function initializes the vectors of an entry
+    // Its arguments are :
+    // - n_words : number of words per line in the cache
+    /////////////////////////////////////////////////////////////////////
+    void alloc(size_t n_words)
+    {
+        wdata_be.reserve( (int)n_words );
+        wdata.reserve( (int)n_words );
+        for(size_t i=0; i<n_words; i++)
+        {
+            wdata_be.push_back(0);
+            wdata.push_back(0);
+        }
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing entry
+    // Its arguments are :
+    // - source : the transaction tab entry to copy
+    ////////////////////////////////////////////////////////////////////
+    void copy(const TransactionTabEntry &source)
+    {
+        valid	    = source.valid;
+        xram_read 	= source.xram_read;
+        nline	    = source.nline;
+        srcid	    = source.srcid;
+        trdid	    = source.trdid;
+        pktid	    = source.pktid;
+        proc_read 	= source.proc_read;
+        read_length = source.read_length;
+        word_index	= source.word_index;
+        wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+        wdata.assign(source.wdata.begin(),source.wdata.end());
+        rerror      = source.rerror;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print(){
+        std::cout << "valid       = " << valid        << std::endl;
+        std::cout << "xram_read   = " << xram_read    << std::endl;
+        std::cout << "nline       = " << std::hex << nline << std::endl;
+        std::cout << "srcid       = " << srcid        << std::endl;
+        std::cout << "trdid       = " << trdid        << std::endl;
+        std::cout << "pktid       = " << pktid        << std::endl;
+        std::cout << "proc_read   = " << proc_read    << std::endl;
+        std::cout << "read_length = " << read_length  << std::endl;
+        std::cout << "word_index  = " << word_index   << std::endl; 
+        for(size_t i=0; i<wdata_be.size() ; i++){
+            std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
+        }
+        for(size_t i=0; i<wdata.size() ; i++){
+            std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
+        }
+        std::cout << std::endl;
+        std::cout << "rerror      = " << rerror       << std::endl;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Constructors
+    /////////////////////////////////////////////////////////////////////
+
+    TransactionTabEntry()
+    {
+        wdata_be.clear();
+        wdata.clear();
+        valid=false;
+        rerror=false;
+    }
+
+    TransactionTabEntry(const TransactionTabEntry &source){
+        valid	    = source.valid;
+        xram_read	= source.xram_read;
+        nline	    = source.nline;
+        srcid	    = source.srcid;
+        trdid	    = source.trdid;
+        pktid	    = source.pktid;
+        proc_read	= source.proc_read;
+        read_length = source.read_length;
+        word_index	= source.word_index;
+        wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+        wdata.assign(source.wdata.begin(),source.wdata.end());	
+        rerror      = source.rerror;
+    }
 
 }; // end class TransactionTabEntry
@@ -135,271 +135,271 @@
 ////////////////////////////////////////////////////////////////////////
 class TransactionTab{
-  typedef uint32_t size_t;
-  typedef uint32_t data_t;
-  typedef sc_dt::sc_uint<40> addr_t;
-  typedef uint32_t be_t;
-
- private:
-  size_t size_tab;                // The size of the tab
-
-  data_t be_to_mask(be_t be)
-  {
-    data_t ret = 0;
-    if ( be&0x1 ) {
-      ret = ret | 0x000000FF;
-    }
-    if ( be&0x2 ) {
-      ret = ret | 0x0000FF00;
-    }
-    if ( be&0x4 ) {
-      ret = ret | 0x00FF0000;
-    }
-    if ( be&0x8 ) {
-      ret = ret | 0xFF000000;
-    }
-    return ret;
-  }
-
- public:
-  TransactionTabEntry *tab;       // The transaction tab
-
-  ////////////////////////////////////////////////////////////////////
-  //		Constructors
-  ////////////////////////////////////////////////////////////////////
-  TransactionTab()
-    {
-      size_tab=0;
-      tab=NULL;
-    }
-
-  TransactionTab(size_t n_entries, size_t n_words)
-    {
-      size_tab = n_entries;
-      tab = new TransactionTabEntry[size_tab];
-      for ( size_t i=0; i<size_tab; i++) {
-	tab[i].alloc(n_words);
-      }
-    }
-
-  ~TransactionTab()
-    {
-      delete [] tab;
-    }
-
-  /////////////////////////////////////////////////////////////////////
-  // The size() function returns the size of the tab
-  /////////////////////////////////////////////////////////////////////
-  size_t size()
-  {
-    return size_tab;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The init() function initializes the transaction tab entries
-  /////////////////////////////////////////////////////////////////////
-  void init()
-  {
-    for ( size_t i=0; i<size_tab; i++) {
-      tab[i].init();
-    }
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The print() function prints a transaction tab entry
-  // Arguments :
-  // - index : the index of the entry to print
-  /////////////////////////////////////////////////////////////////////
-  void print(const size_t index)
-  {
-    assert( (index < size_tab) 
-	    && "Invalid Transaction Tab Entry");
-    tab[index].print();
-    return;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The read() function returns a transaction tab entry.
-  // Arguments :
-  // - index : the index of the entry to read
-  /////////////////////////////////////////////////////////////////////
-  TransactionTabEntry read(const size_t index)
-  {
-    assert( (index < size_tab) 
-	    && "Invalid Transaction Tab Entry");
-    return tab[index];
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The full() function returns the state of the transaction tab
-  // Arguments :
-  // - index : (return argument) the index of an empty entry 
-  // The function returns true if the transaction tab is full
-  /////////////////////////////////////////////////////////////////////
-  bool full(size_t &index)
-  {
-    for(size_t i=0; i<size_tab; i++){
-      if(!tab[i].valid){
-	    index=i;
-	    return false;	
-      }
-    }
-    return true;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The hit_read() function checks if an XRAM read transaction exists 
-  // for a given cache line.
-  // Arguments :
-  // - index : (return argument) the index of the hit entry, if there is 
-  // - nline : the index (zy) of the requested line
-  // The function returns true if a read request has already been sent
-  //////////////////////////////////////////////////////////////////////
-  bool hit_read(const addr_t nline,size_t &index)
-  {
-    for(size_t i=0; i<size_tab; i++){
-      if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
-	    index=i;
-	    return true;	
-      }
-    }
-    return false;
-  }
-
-  ///////////////////////////////////////////////////////////////////////
-  // The hit_write() function looks if an XRAM write transaction exists 
-  // for a given line.
-  // Arguments :
-  // - nline : the index (zy) of the requested line
-  // The function returns true if a write request has already been sent
-  ///////////////////////////////////////////////////////////////////////
-  bool hit_write(const addr_t nline)
-  {
-    for(size_t i=0; i<size_tab; i++){
-      if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
-	    return true;	
-      }
-    }
-    return false;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The write_data_mask() function writes a vector of data (a line).
-  // The data is written only if the corresponding bits are set
-  // in the be vector. 
-  // Arguments :
-  // - index : the index of the request in the transaction tab
-  // - be   : vector of be 
-  // - data : vector of data
-  /////////////////////////////////////////////////////////////////////
-  void write_data_mask(const size_t index, 
-		       const std::vector<be_t> &be, 
-		       const std::vector<data_t> &data) 
-  {
-    assert( (index < size_tab) 
-	    && "Invalid Transaction Tab Entry");
-    assert(be.size()==tab[index].wdata_be.size() 
-	   && "Bad data mask in write_data_mask in TransactionTab");
-    assert(data.size()==tab[index].wdata.size() 
-	   && "Bad data in write_data_mask in TransactionTab");
-
-    for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
-      tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
-      data_t mask = be_to_mask(be[i]);
-      tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
-    }
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The set() function registers a transaction (read or write)
-  // to the XRAM in the transaction tab.
-  // Arguments :
-  // - index : index in the transaction tab
-  // - xram_read : transaction type (read or write a cache line)
-  // - nline : the index (zy) of the cache line
-  // - srcid : srcid of the initiator that caused the transaction
-  // - trdid : trdid of the initiator that caused the transaction
-  // - pktid : pktid of the initiator that caused the transaction
-  // - proc_read : does the initiator want a copy
-  // - read_length : length of read (in case of processor read)
-  // - word_index : index in the line (in case of single word read)
-  // - data : the data to write (in case of write)
-  // - data_be : the mask of the data to write (in case of write)
-  /////////////////////////////////////////////////////////////////////
-  void set(const size_t index,
-	   const bool xram_read,
-	   const addr_t nline,
-	   const size_t srcid,
-	   const size_t trdid,
-	   const size_t pktid,
-	   const bool proc_read,
-	   const size_t read_length,
-	   const size_t word_index,
-	   const std::vector<be_t> &data_be,
-	   const std::vector<data_t> &data) 
-  {
-    assert( (index < size_tab) 
-	    && "The selected entry is out of range in set() Transaction Tab");
-    assert(data_be.size()==tab[index].wdata_be.size() 
-	   && "Bad data_be argument in set() TransactionTab");
-    assert(data.size()==tab[index].wdata.size() 
-	   && "Bad data argument in set() TransactionTab");
-
-    tab[index].valid	        = true;
-    tab[index].xram_read        = xram_read;
-    tab[index].nline	        = nline;
-    tab[index].srcid	        = srcid;
-    tab[index].trdid	        = trdid;
-    tab[index].pktid	        = pktid;
-    tab[index].proc_read	    = proc_read;
-    tab[index].read_length	    = read_length;
-    tab[index].word_index	    = word_index;
-    for(size_t i=0; i<tab[index].wdata.size(); i++) 
-    {
-      tab[index].wdata_be[i]    = data_be[i];
-      tab[index].wdata[i]       = data[i];
-    }
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The write_rsp() function writes a word of the response to an 
-  // XRAM read transaction.
-  // The BE field in TRT is taken into account.
-  // Arguments :
-  // - index : the index of the transaction in the transaction tab
-  // - word_index : the index of the data in the line
-  // - data : the data to write
-  // - error : invalid data
-  /////////////////////////////////////////////////////////////////////
-  void write_rsp(const size_t index,
-                 const size_t word,
-                 const data_t data,
-                 const bool   rerror)
-  {
-    assert( (index < size_tab) 
-	    && "Selected entry  out of range in write_rsp() Transaction Tab");
-    assert( (word <= tab[index].wdata_be.size()) 
-	    && "Bad word_index in write_rsp() in TransactionTab");
-    assert( tab[index].valid 
-	    && "Transaction Tab Entry invalid in write_rsp()");
-    assert( tab[index].xram_read 
-	    && "Selected entry is not an XRAM read transaction in write_rsp()");
-
-    data_t mask = be_to_mask(tab[index].wdata_be[word]);
-    tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
-    tab[index].rerror |= rerror;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The erase() function erases an entry in the transaction tab.
-  // Arguments :
-  // - index : the index of the request in the transaction tab
-  /////////////////////////////////////////////////////////////////////
-  void erase(const size_t index)
-  {
-    assert( (index < size_tab) 
-	    && "The selected entry is out of range in erase() Transaction Tab");
-    tab[index].valid	= false;
-    tab[index].rerror   = false;
-  }
+    typedef uint32_t size_t;
+    typedef uint32_t data_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t be_t;
+
+    private:
+    size_t size_tab;                // The size of the tab
+
+    data_t be_to_mask(be_t be)
+    {
+        data_t ret = 0;
+        if ( be&0x1 ) {
+            ret = ret | 0x000000FF;
+        }
+        if ( be&0x2 ) {
+            ret = ret | 0x0000FF00;
+        }
+        if ( be&0x4 ) {
+            ret = ret | 0x00FF0000;
+        }
+        if ( be&0x8 ) {
+            ret = ret | 0xFF000000;
+        }
+        return ret;
+    }
+
+    public:
+    TransactionTabEntry *tab;       // The transaction tab
+
+    ////////////////////////////////////////////////////////////////////
+    //		Constructors
+    ////////////////////////////////////////////////////////////////////
+    TransactionTab()
+    {
+        size_tab=0;
+        tab=NULL;
+    }
+
+    TransactionTab(size_t n_entries, size_t n_words)
+    {
+        size_tab = n_entries;
+        tab = new TransactionTabEntry[size_tab];
+        for ( size_t i=0; i<size_tab; i++) {
+            tab[i].alloc(n_words);
+        }
+    }
+
+    ~TransactionTab()
+    {
+        delete [] tab;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The size() function returns the size of the tab
+    /////////////////////////////////////////////////////////////////////
+    size_t size()
+    {
+        return size_tab;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the transaction tab entries
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+        for ( size_t i=0; i<size_tab; i++) {
+            tab[i].init();
+        }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a transaction tab entry
+    // Arguments :
+    // - index : the index of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t index)
+    {
+        assert( (index < size_tab) 
+                && "Invalid Transaction Tab Entry");
+        tab[index].print();
+        return;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function returns a transaction tab entry.
+    // Arguments :
+    // - index : the index of the entry to read
+    /////////////////////////////////////////////////////////////////////
+    TransactionTabEntry read(const size_t index)
+    {
+        assert( (index < size_tab) 
+                && "Invalid Transaction Tab Entry");
+        return tab[index];
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The full() function returns the state of the transaction tab
+    // Arguments :
+    // - index : (return argument) the index of an empty entry 
+    // The function returns true if the transaction tab is full
+    /////////////////////////////////////////////////////////////////////
+    bool full(size_t &index)
+    {
+        for(size_t i=0; i<size_tab; i++){
+            if(!tab[i].valid){
+                index=i;
+                return false;	
+            }
+        }
+        return true;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The hit_read() function checks if an XRAM read transaction exists 
+    // for a given cache line.
+    // Arguments :
+    // - index : (return argument) the index of the hit entry, if there is 
+    // - nline : the index (zy) of the requested line
+    // The function returns true if a read request has already been sent
+    //////////////////////////////////////////////////////////////////////
+    bool hit_read(const addr_t nline,size_t &index)
+    {
+        for(size_t i=0; i<size_tab; i++){
+            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+                index=i;
+                return true;	
+            }
+        }
+        return false;
+    }
+
+    ///////////////////////////////////////////////////////////////////////
+    // The hit_write() function looks if an XRAM write transaction exists 
+    // for a given line.
+    // Arguments :
+    // - nline : the index (zy) of the requested line
+    // The function returns true if a write request has already been sent
+    ///////////////////////////////////////////////////////////////////////
+    bool hit_write(const addr_t nline)
+    {
+        for(size_t i=0; i<size_tab; i++){
+            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+                return true;	
+            }
+        }
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The write_data_mask() function writes a vector of data (a line).
+    // The data is written only if the corresponding bits are set
+    // in the be vector. 
+    // Arguments :
+    // - index : the index of the request in the transaction tab
+    // - be   : vector of be 
+    // - data : vector of data
+    /////////////////////////////////////////////////////////////////////
+    void write_data_mask(const size_t index, 
+            const std::vector<be_t> &be, 
+            const std::vector<data_t> &data) 
+    {
+        assert( (index < size_tab) 
+                && "Invalid Transaction Tab Entry");
+        assert(be.size()==tab[index].wdata_be.size() 
+                && "Bad data mask in write_data_mask in TransactionTab");
+        assert(data.size()==tab[index].wdata.size() 
+                && "Bad data in write_data_mask in TransactionTab");
+
+        for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+            tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
+            data_t mask = be_to_mask(be[i]);
+            tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
+        }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The set() function registers a transaction (read or write)
+    // to the XRAM in the transaction tab.
+    // Arguments :
+    // - index : index in the transaction tab
+    // - xram_read : transaction type (read or write a cache line)
+    // - nline : the index (zy) of the cache line
+    // - srcid : srcid of the initiator that caused the transaction
+    // - trdid : trdid of the initiator that caused the transaction
+    // - pktid : pktid of the initiator that caused the transaction
+    // - proc_read : does the initiator want a copy
+    // - read_length : length of read (in case of processor read)
+    // - word_index : index in the line (in case of single word read)
+    // - data : the data to write (in case of write)
+    // - data_be : the mask of the data to write (in case of write)
+    /////////////////////////////////////////////////////////////////////
+    void set(const size_t index,
+            const bool xram_read,
+            const addr_t nline,
+            const size_t srcid,
+            const size_t trdid,
+            const size_t pktid,
+            const bool proc_read,
+            const size_t read_length,
+            const size_t word_index,
+            const std::vector<be_t> &data_be,
+            const std::vector<data_t> &data) 
+    {
+        assert( (index < size_tab) 
+                && "The selected entry is out of range in set() Transaction Tab");
+        assert(data_be.size()==tab[index].wdata_be.size() 
+                && "Bad data_be argument in set() TransactionTab");
+        assert(data.size()==tab[index].wdata.size() 
+                && "Bad data argument in set() TransactionTab");
+
+        tab[index].valid	        = true;
+        tab[index].xram_read        = xram_read;
+        tab[index].nline	        = nline;
+        tab[index].srcid	        = srcid;
+        tab[index].trdid	        = trdid;
+        tab[index].pktid	        = pktid;
+        tab[index].proc_read	    = proc_read;
+        tab[index].read_length	    = read_length;
+        tab[index].word_index	    = word_index;
+        for(size_t i=0; i<tab[index].wdata.size(); i++) 
+        {
+            tab[index].wdata_be[i]    = data_be[i];
+            tab[index].wdata[i]       = data[i];
+        }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The write_rsp() function writes a word of the response to an 
+    // XRAM read transaction.
+    // The BE field in TRT is taken into account.
+    // Arguments :
+    // - index : the index of the transaction in the transaction tab
+    // - word_index : the index of the data in the line
+    // - data : the data to write
+    // - error : invalid data
+    /////////////////////////////////////////////////////////////////////
+    void write_rsp(const size_t index,
+            const size_t word,
+            const data_t data,
+            const bool   rerror)
+    {
+        assert( (index < size_tab) 
+                && "Selected entry  out of range in write_rsp() Transaction Tab");
+        assert( (word <= tab[index].wdata_be.size()) 
+                && "Bad word_index in write_rsp() in TransactionTab");
+        assert( tab[index].valid 
+                && "Transaction Tab Entry invalid in write_rsp()");
+        assert( tab[index].xram_read 
+                && "Selected entry is not an XRAM read transaction in write_rsp()");
+
+        data_t mask = be_to_mask(tab[index].wdata_be[word]);
+        tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+        tab[index].rerror |= rerror;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The erase() function erases an entry in the transaction tab.
+    // Arguments :
+    // - index : the index of the request in the transaction tab
+    /////////////////////////////////////////////////////////////////////
+    void erase(const size_t index)
+    {
+        assert( (index < size_tab) 
+                && "The selected entry is out of range in erase() Transaction Tab");
+        tab[index].valid	= false;
+        tab[index].rerror   = false;
+    }
 }; // end class TransactionTab
 
Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 247)
+++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 253)
@@ -802,5 +802,5 @@
 if( m_debug_tgt_cmd_fsm ) 
 {
-    std::cout << "  <MEMC.TGT_CMD_IDLE> Receive command from srcid " << std::dec << p_vci_tgt.srcid.read()
+    std::cout << "  <MEMC " << name() << ".TGT_CMD_IDLE> Receive command from srcid " << std::dec << p_vci_tgt.srcid.read()
               << " / for address " << std::hex << p_vci_tgt.address.read() << std::endl;
 }
@@ -821,5 +821,5 @@
                 {
                     std::cout << "VCI_MEM_CACHE ERROR " << name() << std::endl;
-                    std::cout << "Out of segment VCI address in TGT_CMD_IDLE state" << std::endl;
+                    std::cout << "Out of segment VCI address in TGT_CMD_IDLE state (address = " << std::hex << address << ", srcid = " << p_vci_tgt.srcid.read() << std::dec << ", cycle = " << m_cpt_cycles << ")" << std::endl;
                     exit(0);
                 }
@@ -869,5 +869,5 @@
 if( m_debug_tgt_cmd_fsm ) 
 {
-    std::cout << "  <MEMC.TGT_CMD_READ> Push into read_fifo:" 
+    std::cout << "  <MEMC " << name() << ".TGT_CMD_READ> Push into read_fifo:" 
               << " address = " << std::hex << p_vci_tgt.address.read()
               << " srcid = " << std::dec << p_vci_tgt.srcid.read()
@@ -891,5 +891,5 @@
 if( m_debug_tgt_cmd_fsm ) 
 {
-    std::cout << "  <MEMC.TGT_CMD_WRITE> Push into write_fifo:" 
+    std::cout << "  <MEMC " << name() << ".TGT_CMD_WRITE> Push into write_fifo:" 
               << " address = " << std::hex << p_vci_tgt.address.read()
               << " srcid = " << std::dec << p_vci_tgt.srcid.read()
@@ -921,5 +921,5 @@
 if( m_debug_tgt_cmd_fsm ) 
 {
-    std::cout << "  <MEMC.TGT_CMD_ATOMIC> Pushing command into cmd_sc_fifo:"
+    std::cout << "  <MEMC " << name() << ".TGT_CMD_ATOMIC> Pushing command into cmd_sc_fifo:"
               << " address = " << std::hex << p_vci_tgt.address.read()
               << " srcid = " << std::dec << p_vci_tgt.srcid.read()
@@ -969,5 +969,5 @@
 if( m_debug_init_rsp_fsm ) 
 {
-    std::cout <<  "  <MEMC.INIT_RSP_IDLE> Response for UPT entry " 
+    std::cout <<  "  <MEMC " << name() << ".INIT_RSP_IDLE> Response for UPT entry " 
               << p_vci_ini.rtrdid.read() << std::endl;
 }
@@ -1012,5 +1012,5 @@
 if( m_debug_init_rsp_fsm ) 
 {
-    std::cout << "  <MEMC.INIT_RSP_UPT_LOCK> Decrement the responses counter for UPT:"
+    std::cout << "  <MEMC " << name() << ".INIT_RSP_UPT_LOCK> Decrement the responses counter for UPT:"
               << " entry = " << r_init_rsp_upt_index.read() 
               << " / rsp_count = " << std::dec << count << std::endl;
@@ -1049,5 +1049,5 @@
 if ( m_debug_init_rsp_fsm )
 {
-    std::cout <<  "  <MEMC.INIT_RSP_UPT_CLEAR> Clear UPT entry "
+    std::cout <<  "  <MEMC " << name() << ".INIT_RSP_UPT_CLEAR> Clear UPT entry "
               << r_init_rsp_upt_index.read() <<  std::endl;
 }
@@ -1070,5 +1070,5 @@
 if ( m_debug_init_rsp_fsm )
 {
-    std::cout <<  "  <MEMC.INIT_RSP_END> Request TGT_RSP FSM to send a response to srcid "
+    std::cout <<  "  <MEMC " << name() << ".INIT_RSP_END> Request TGT_RSP FSM to send a response to srcid "
               << r_init_rsp_srcid.read() <<  std::endl;
 }
@@ -1113,5 +1113,5 @@
 if( m_debug_read_fsm ) 
 {
-    std::cout << "  <MEMC.READ_IDLE> Read request:"
+    std::cout << "  <MEMC " << name() << ".READ_IDLE> Read request:"
               << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
               << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
@@ -1162,5 +1162,5 @@
 if( m_debug_read_fsm ) 
 {
-    std::cout << "  <MEMC.READ_DIR_LOCK> Accessing directory: "
+    std::cout << "  <MEMC " << name() << ".READ_DIR_LOCK> Accessing directory: "
               << " address = " << std::hex << m_cmd_read_addr_fifo.read() 
               << " / hit = " << std::dec << entry.valid 
@@ -1233,5 +1233,5 @@
 if( m_debug_read_fsm )
 {
-    std::cout << "  <MEMC.READ_DIR_HIT> Update directory entry:"
+    std::cout << "  <MEMC " << name() << ".READ_DIR_HIT> Update directory entry:"
               << " set = " << std::dec << set 
               << " / way = " << way 
@@ -1329,5 +1329,5 @@
 if( m_debug_read_fsm )
 {
-    std::cout << "  <MEMC.READ_HEAP_LOCK> Update directory:"
+    std::cout << "  <MEMC " << name() << ".READ_HEAP_LOCK> Update directory:"
               << " tag = " << std::hex << entry.tag
               << " set = " << std::dec << set 
@@ -1369,5 +1369,5 @@
 if( m_debug_read_fsm )
 {
-    std::cout << "  <MEMC.READ_HEAP_WRITE> Add an entry in the heap:"
+    std::cout << "  <MEMC " << name() << ".READ_HEAP_WRITE> Add an entry in the heap:"
               << " owner_id = " << heap_entry.owner.srcid
               << " owner_ins = " << heap_entry.owner.inst << std::endl;
@@ -1460,5 +1460,5 @@
 if( m_debug_read_fsm )
 {
-    std::cout << "  <MEMC.READ_RSP> Request the TGT_RSP FSM to return data:"
+    std::cout << "  <MEMC " << name() << ".READ_RSP> Request the TGT_RSP FSM to return data:"
               << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read()
               << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
@@ -1496,5 +1496,5 @@
 if( m_debug_read_fsm )
 {
-    std::cout << "  <MEMC.READ_TRT_LOCK> Check TRT:"
+    std::cout << "  <MEMC " << name() << ".READ_TRT_LOCK> Check TRT:"
               << " hit_read = " << hit_read 
               << " / hit_write = " << hit_write 
@@ -1524,5 +1524,5 @@
 if( m_debug_read_fsm )
 {
-    std::cout << "  <MEMC.READ_TRT_SET> Write in Transaction Table: " << std::hex
+    std::cout << "  <MEMC " << name() << ".READ_TRT_SET> Write in Transaction Table: " << std::hex
               << " address = " << std::hex << m_cmd_read_addr_fifo.read() 
               << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
@@ -1549,5 +1549,5 @@
 if( m_debug_read_fsm )
 {
-    std::cout << "  <MEMC.READ_TRT_REQ> Request GET transaction for address " 
+    std::cout << "  <MEMC " << name() << ".READ_TRT_REQ> Request GET transaction for address " 
               << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
 }
@@ -1629,5 +1629,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_IDLE> Write request " 
+    std::cout << "  <MEMC " << name() << ".WRITE_IDLE> Write request " 
               << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
               << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 
@@ -1647,5 +1647,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_NEXT> Write another word in local buffer" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_NEXT> Write another word in local buffer" << std::endl;
 }
 #endif
@@ -1717,5 +1717,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_DIR_LOCK> Check the directory: "
+    std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> Check the directory: "
               << " address = " << std::hex << r_write_address.read()
               << " hit = " << std::dec << entry.valid 
@@ -1756,5 +1756,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
 }
 #endif
@@ -1832,10 +1832,10 @@
     if ( no_update )
     {
-        std::cout << "  <MEMC.WRITE_DIR_HIT> Write into cache / No coherence transaction" 
+        std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Write into cache / No coherence transaction" 
                   << std::endl;
     }
     else
     {
-        std::cout << "  <MEMC.WRITE_DIR_HIT> Coherence update required:"
+        std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Coherence update required:"
                   << " is_cnt = " << r_write_is_cnt.read() 
                   << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
@@ -1895,5 +1895,5 @@
     if ( wok )
     {
-        std::cout << "  <MEMC.WRITE_UPT_LOCK> Register the multicast update in UPT / " 
+        std::cout << "  <MEMC " << name() << ".WRITE_UPT_LOCK> Register the multicast update in UPT / " 
                   << " nb_copies = " << r_write_count.read() << std::endl;
     }
@@ -1916,5 +1916,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
 }
 #endif
@@ -1977,5 +1977,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_UPT_REQ> Post first request to INIT_CMD FSM" 
+    std::cout << "  <MEMC " << name() << ".WRITE_UPT_REQ> Post first request to INIT_CMD FSM" 
               << " / srcid = " << std::dec << r_write_copy.read() 
               << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
@@ -2018,5 +2018,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_UPT_NEXT> Post another request to INIT_CMD FSM" 
+    std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Post another request to INIT_CMD FSM" 
               << " / heap_index = " << std::dec << r_write_ptr.read()
               << " / srcid = " << std::dec << r_write_copy.read() 
@@ -2034,5 +2034,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_UPT_NEXT> Skip one entry in heap matching the writer" 
+    std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Skip one entry in heap matching the writer" 
               << " / heap_index = " << std::dec << r_write_ptr.read()
               << " / srcid = " << std::dec << r_write_copy.read() 
@@ -2133,5 +2133,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
+    std::cout << "  <MEMC " << name() << ".WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
               << std::dec << r_write_srcid.read() << std::endl;
     if ( m_cmd_write_addr_fifo.rok() ) 
@@ -2156,5 +2156,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
 }
 #endif
@@ -2193,5 +2193,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_WAIT> Releases the locks before retry" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_WAIT> Releases the locks before retry" << std::endl;
 }
 #endif
@@ -2229,5 +2229,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
 }
 #endif
@@ -2257,5 +2257,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
     m_transaction_tab.print( r_write_trt_index.read() );
 }
@@ -2278,5 +2278,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
 }
 #endif
@@ -2304,5 +2304,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_BC_TRT_LOCK> Check TRT : wok = "
+    std::cout << "  <MEMC " << name() << ".WRITE_BC_TRT_LOCK> Check TRT : wok = "
               << wok << " / index = " << wok_index << std::endl;
 }
@@ -2339,5 +2339,5 @@
     if ( wok )
     { 
-        std::cout << "  <MEMC.WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / " 
+        std::cout << "  <MEMC " << name() << ".WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / " 
                   << " nb_copies = " << r_write_count.read() << std::endl;
     }
@@ -2398,5 +2398,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
+    std::cout << "  <MEMC " << name() << ".WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
               << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
 }
@@ -2427,5 +2427,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl;
 }
 #endif
@@ -2450,5 +2450,5 @@
 if( m_debug_write_fsm )
 {
-    std::cout << "  <MEMC.WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
+    std::cout << "  <MEMC " << name() << ".WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
 }
 #endif
@@ -2514,5 +2514,5 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
 }
 #endif
@@ -2539,5 +2539,5 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
 }
 #endif
@@ -2551,5 +2551,5 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
 }
 #endif
@@ -2577,5 +2577,5 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a put request to xram" << std::endl;
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_SC_NLINE> Send a put request to xram" << std::endl;
 }
 #endif
@@ -2589,5 +2589,5 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a get request to xram" << std::endl;
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_SC_NLINE> Send a get request to xram" << std::endl;
 }
 #endif
@@ -2613,5 +2613,5 @@
 if( m_debug_ixr_cmd_fsm )
 {
-    std::cout << "  <MEMC.IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
 }
 #endif
@@ -2656,5 +2656,5 @@
 if( m_debug_ixr_rsp_fsm ) 
 {
-    std::cout << "  <MEMC.IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl; 
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl; 
 }
 #endif
@@ -2667,5 +2667,5 @@
 if( m_debug_ixr_rsp_fsm ) 
 {
-    std::cout << "  <MEMC.IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; 
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; 
 }
 #endif
@@ -2682,5 +2682,5 @@
 if( m_debug_ixr_rsp_fsm ) 
 {
-    std::cout << "  <MEMC.IXR_RSP_ACK>" << std::endl; 
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_ACK>" << std::endl; 
 }
 #endif
@@ -2698,5 +2698,5 @@
 if( m_debug_ixr_rsp_fsm )
 {
-    std::cout << "  <MEMC.IXR_RSP_TRT_ERASE> Erase TRT entry " 
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_ERASE> Erase TRT entry " 
               << r_ixr_rsp_trt_index.read() << std::endl; 
 }
@@ -2730,5 +2730,5 @@
 if( m_debug_ixr_rsp_fsm )
 {
-    std::cout << "  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT : "
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_READ> Writing a word in TRT : "
               << " index = " << std::dec << index
               << " / word = " << r_ixr_rsp_cpt.read()
@@ -2783,5 +2783,5 @@
 if( m_debug_xram_rsp_fsm )
 {	
-    std::cout << "  <MEMC.XRAM_RSP_IDLE> Available cache line in TRT:"
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_IDLE> Available cache line in TRT:"
               << " index = " << std::dec << index << std::endl;
 }
@@ -2802,5 +2802,5 @@
 if( m_debug_xram_rsp_fsm )
 {	
-    std::cout << "  <MEMC.XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
 }
 #endif
@@ -2850,5 +2850,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_TRT_COPY> Select a slot: "
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_COPY> Select a slot: "
               << " way = " << std::dec << way 
               << " / set = " << set 
@@ -2872,5 +2872,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
               << " but an invalidation is already registered at this address" << std::endl;
     m_update_tab.print();
@@ -2886,5 +2886,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
               << " but the table is full" << std::endl;
     m_update_tab.print();
@@ -2899,5 +2899,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
 }
 #endif
@@ -2991,5 +2991,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_DIR_UPDT> Directory update: "
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_UPDT> Directory update: "
               << " way = " << std::dec << way 
               << " / set = " << set 
@@ -3034,5 +3034,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
 	      << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
 }
@@ -3066,5 +3066,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:" 
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:" 
               << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid
               << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
@@ -3104,5 +3104,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_INVAL> Send an inval request to INIT_CMD FSM:" 
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL> Send an inval request to INIT_CMD FSM:" 
               << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
 }
@@ -3130,5 +3130,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:" 
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:" 
               << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
 }
@@ -3171,5 +3171,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_HEAP_ERASE> Erase the list of copies:" 
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_ERASE> Erase the list of copies:" 
               << " srcid = " << std::dec << entry.owner.srcid
               << " / inst = " << std::dec << entry.owner.inst << std::endl;
@@ -3214,5 +3214,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
 }
 #endif
@@ -3231,5 +3231,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
 }
 #endif
@@ -3255,5 +3255,5 @@
 if( m_debug_xram_rsp_fsm )
 {
-    std::cout << "  <MEMC.XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
               << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
 }
@@ -3309,6 +3309,6 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_IDLE> Cleanup request:" << std::hex
-              << " line = " << line * m_words * 4
+    std::cout << "  <MEMC " << name() << ".CLEANUP_IDLE> Cleanup request:" << std::hex
+              << " line addr = " << line * m_words * 4
               << " / owner_id = " << p_vci_tgt_cleanup.srcid.read() 
               << " / owner_ins = " << (p_vci_tgt_cleanup.trdid.read()&0x1)
@@ -3362,5 +3362,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_DIR_LOCK> Test directory status: " << std::hex
+    std::cout << "  <MEMC " << name() << ".CLEANUP_DIR_LOCK> Test directory status: " << std::hex
               << " line = " << r_cleanup_nline.read() * m_words * 4
               << " / hit = " << entry.valid
@@ -3446,5 +3446,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_DIR_WRITE> Update directory:" << std::hex
+    std::cout << "  <MEMC " << name() << ".CLEANUP_DIR_WRITE> Update directory:" << std::hex
               << " line = " << r_cleanup_nline.read() * m_words * 4
               << " / dir_id = " << entry.owner.srcid
@@ -3567,5 +3567,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_HEAP_LOCK> Checks matching:"
+    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_LOCK> Checks matching:"
               << " line = " << r_cleanup_nline.read() * m_words * 4
               << " / dir_id = " << r_cleanup_copy.read()
@@ -3605,5 +3605,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_HEAP_SEARCH> Cheks matching:"
+    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Cheks matching:"
               << " line = " << r_cleanup_nline.read() * m_words * 4
               << " / heap_id = " << heap_entry.owner.srcid
@@ -3642,5 +3642,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
+    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
               << " line = " << r_cleanup_nline.read() * m_words * 4
               << " / heap_id = " << heap_entry.owner.srcid
@@ -3686,5 +3686,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_HEAP_SEARCH> Remove the copy in the linked list" << std::endl;
+    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Remove the copy in the linked list" << std::endl;
 }
 #endif
@@ -3719,5 +3719,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_HEAP_SEARCH> Update the list of free entries" << std::endl;
+    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Update the list of free entries" << std::endl;
 }
 #endif
@@ -3739,5 +3739,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry:"
+    std::cout << "  <MEMC " << name() << ".CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry:"
               << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl;
 }
@@ -3769,5 +3769,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_UPT_WRITE> Decrement response counter in UPT:"
+    std::cout << "  <MEMC " << name() << ".CLEANUP_UPT_WRITE> Decrement response counter in UPT:"
               << " UPT_index = " << r_cleanup_index.read()
               << " rsp_count = " << count << std::endl;
@@ -3797,5 +3797,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_WRITE_RSP> Send a response to a cleanup request:"
+    std::cout << "  <MEMC " << name() << ".CLEANUP_WRITE_RSP> Send a response to a cleanup request:"
               << " rsrcid = " << std::dec << r_cleanup_write_srcid.read()
               << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read() << std::endl;
@@ -3815,5 +3815,5 @@
 if( m_debug_cleanup_fsm )
 {
-    std::cout << "  <MEMC.CLEANUP_RSP> Send the response to a cleanup request:"
+    std::cout << "  <MEMC " << name() << ".CLEANUP_RSP> Send the response to a cleanup request:"
               << " rsrcid = " << std::dec << r_cleanup_write_srcid.read()
               << " / rtrdid = " << r_cleanup_write_trdid.read() << std::endl;
@@ -3861,5 +3861,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_IDLE> SC command: " << std::hex
+    std::cout << "  <MEMC " << name() << ".SC_IDLE> SC command: " << std::hex
               << " srcid = " <<  std::dec << m_cmd_sc_srcid_fifo.read() 
               << " addr = " << std::hex << m_cmd_sc_addr_fifo.read() 
@@ -3925,5 +3925,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_DIR_LOCK> Directory acces"
+    std::cout << "  <MEMC " << name() << ".SC_DIR_LOCK> Directory acces"
               << " / address = " << std::hex << m_cmd_sc_addr_fifo.read()
               << " / hit = " << std::dec << entry.valid 
@@ -3981,5 +3981,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_DIR_HIT_READ> Test if SC success:" 
+    std::cout << "  <MEMC " << name() << ".SC_DIR_HIT_READ> Test if SC success:" 
               << " / expected value = " << r_sc_rdata[0].read()
               << " / actual value = " << m_cache_data[way][set][word]
@@ -4036,5 +4036,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_DIR_HIT_WRITE> Update cache:" 
+    std::cout << "  <MEMC " << name() << ".SC_DIR_HIT_WRITE> Update cache:" 
               << " way = " << std::dec << way
               << " / set = " << set
@@ -4104,5 +4104,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_UPT_LOCK> Register multi-update transaction in UPT"  
+    std::cout << "  <MEMC " << name() << ".SC_UPT_LOCK> Register multi-update transaction in UPT"  
               << " / wok = " << wok
               << " / nline  = " << std::hex << nline 
@@ -4120,5 +4120,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_WAIT> Release all locks" << std::endl;
+    std::cout << "  <MEMC " << name() << ".SC_WAIT> Release all locks" << std::endl;
 }
 #endif
@@ -4135,5 +4135,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
+    std::cout << "  <MEMC " << name() << ".SC_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
 }
 #endif
@@ -4190,5 +4190,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_UPT_REQ> Send the first update request to INIT_CMD FSM " 
+    std::cout << "  <MEMC " << name() << ".SC_UPT_REQ> Send the first update request to INIT_CMD FSM " 
               << " / address = " << std::hex << m_cmd_sc_addr_fifo.read()
               << " / wdata = " << std::hex << r_sc_wdata.read()
@@ -4230,5 +4230,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_UPT_NEXT> Send the next update request to INIT_CMD FSM " 
+    std::cout << "  <MEMC " << name() << ".SC_UPT_NEXT> Send the next update request to INIT_CMD FSM " 
               << " / address = " << std::hex << m_cmd_sc_addr_fifo.read()
               << " / wdata = " << std::hex << r_sc_wdata.read()
@@ -4335,5 +4335,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
+    std::cout << "  <MEMC " << name() << ".SC_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
               << " / nline = " << nline 
               << " / count = " << nb_copies 
@@ -4392,5 +4392,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
+    std::cout << "  <MEMC " << name() << ".SC_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
               << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]
               << " / set = " << std::dec << set << " / way = " << way << std::endl;
@@ -4437,5 +4437,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
+    std::cout << "  <MEMC " << name() << ".SC_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
               << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
               << " / trt_index = " << r_sc_trt_index.read() << std::endl;
@@ -4467,5 +4467,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
+    std::cout << "  <MEMC " << name() << ".SC_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
 }
 #endif
@@ -4490,5 +4490,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
+    std::cout << "  <MEMC " << name() << ".SC_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
 }
 #endif
@@ -4511,5 +4511,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_MISS_TRT_LOCK> Check TRT state" 
+    std::cout << "  <MEMC " << name() << ".SC_MISS_TRT_LOCK> Check TRT state" 
               << " / hit_read = "  << hit_read
               << " / hit_write = " << hit_write
@@ -4562,5 +4562,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
+    std::cout << "  <MEMC " << name() << ".SC_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
               << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] 
               << " / trt_index = " << r_sc_trt_index.read() << std::endl;
@@ -4584,5 +4584,5 @@
 if( m_debug_sc_fsm )
 {
-    std::cout << "  <MEMC.SC_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
+    std::cout << "  <MEMC " << name() << ".SC_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
               << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
               << " / trt_index = " << r_sc_trt_index.read() << std::endl;
@@ -4773,5 +4773,5 @@
 if( m_debug_init_cmd_fsm )
 {
-    std::cout << "  <MEMC.INIT_CMD_WRITE_BRDCAST> Broadcast-Inval for line " 
+    std::cout << "  <MEMC " << name() << ".INIT_CMD_WRITE_BRDCAST> Broadcast-Inval for line " 
               << r_write_to_init_cmd_nline.read() << std::endl;
 }
@@ -5031,5 +5031,5 @@
 if( m_debug_tgt_rsp_fsm )
 {
-    std::cout << "  <MEMC.TGT_RSP_READ> Read response"
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_READ> Read response"
               << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read()
               << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read()
@@ -5059,5 +5059,5 @@
 if( m_debug_tgt_rsp_fsm )
 {
-    std::cout << "  <MEMC.TGT_RSP_WRITE> Write response"
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_WRITE> Write response"
               << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read()
               << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() << std::endl;
@@ -5078,5 +5078,5 @@
 if( m_debug_tgt_rsp_fsm )
 {
-    std::cout << "  <MEMC.TGT_RSP_CLEANUP> Cleanup response"
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_CLEANUP> Cleanup response"
               << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read()
               << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() << std::endl;
@@ -5097,5 +5097,5 @@
 if( m_debug_tgt_rsp_fsm )
 {
-    std::cout << "  <MEMC.TGT_RSP_SC> SC response"
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_SC> SC response"
               << " / rsrcid = " << std::dec << r_sc_to_tgt_rsp_srcid.read()
               << " / rtrdid = " << r_sc_to_tgt_rsp_trdid.read() << std::endl;
@@ -5117,5 +5117,5 @@
 if( m_debug_tgt_rsp_fsm )
 {
-    std::cout << "  <MEMC.TGT_RSP_XRAM> Response following XRAM access"
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_XRAM> Response following XRAM access"
               << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read()
               << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
@@ -5147,5 +5147,5 @@
 if( m_debug_tgt_rsp_fsm )
 {
-    std::cout << "  <MEMC.TGT_RSP_INIT> Write response after coherence transaction"
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_INIT> Write response after coherence transaction"
               << " / rsrcid = " << std::dec << r_init_rsp_to_tgt_rsp_srcid.read()
               << " / rtrdid = " << r_init_rsp_to_tgt_rsp_trdid.read() << std::endl;