Index: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (revision 253) +++ trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp (revision 254) @@ -43,5 +43,5 @@ "ICACHE_XTN_CACHE_FLUSH", "ICACHE_XTN_TLB_INVAL", - "ICACHE_XTN_CACHE_INVAL_VA", + "ICACHE_XTN_CACHE_INVAL_VA", "ICACHE_XTN_CACHE_INVAL_PA", "ICACHE_XTN_CACHE_INVAL_GO", @@ -66,8 +66,8 @@ "DCACHE_TLB_MISS", "DCACHE_TLB_PTE1_GET", - "DCACHE_TLB_PTE1_SELECT", + "DCACHE_TLB_PTE1_SELECT", "DCACHE_TLB_PTE1_UPDT", "DCACHE_TLB_PTE2_GET", - "DCACHE_TLB_PTE2_SELECT", + "DCACHE_TLB_PTE2_SELECT", "DCACHE_TLB_PTE2_UPDT", "DCACHE_TLB_LR_UPDT", @@ -742,7 +742,7 @@ // Debug variables m_debug_previous_hit = false; - m_idebug_previous_hit = false; - m_debug_dcache_fsm = false; - m_debug_icache_fsm = false; + m_idebug_previous_hit = false; + m_debug_dcache_fsm = false; + m_debug_icache_fsm = false; m_debug_cleanup_fsm = false; @@ -757,7 +757,7 @@ m_cpt_icache_dir_write = 0; - m_cpt_frz_cycles = 0; - m_cpt_total_cycles = 0; - m_cpt_stop_simulation = 0; + m_cpt_frz_cycles = 0; + m_cpt_total_cycles = 0; + m_cpt_stop_simulation = 0; m_cpt_data_miss = 0; @@ -782,5 +782,5 @@ m_cost_unc_transaction = 0; m_cost_write_transaction = 0; - m_cost_icache_unc_transaction = 0; + m_cost_icache_unc_transaction = 0; m_length_write_transaction = 0; @@ -811,13 +811,13 @@ m_cost_data_tlb_inval_frz = 0; - m_cpt_cc_broadcast = 0; - - m_cost_updt_data_frz = 0; - m_cost_inval_ins_frz = 0; - m_cost_inval_data_frz = 0; - m_cost_broadcast_frz = 0; - - m_cpt_cc_cleanup_data = 0; - m_cpt_cc_cleanup_ins = 0; + m_cpt_cc_broadcast = 0; + + m_cost_updt_data_frz = 0; + m_cost_inval_ins_frz = 0; + m_cost_inval_data_frz = 0; + m_cost_broadcast_frz = 0; + + m_cpt_cc_cleanup_data = 0; + m_cpt_cc_cleanup_ins = 0; m_cpt_itlbmiss_transaction = 0; @@ -960,11 +960,14 @@ r_tgt_pktid = p_vci_tgt_c.pktid.read(); - if (sizeof(paddr_t) <= 32) { - assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr"); - r_tgt_paddr = - (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; - } else { - r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 | - (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; + if (sizeof(paddr_t) <= 32) + { + assert(p_vci_tgt_c.be.read() == 0 + && "byte enable should be 0 for 32bits paddr"); + r_tgt_paddr = (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; + } + else + { + r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 | + (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; } @@ -2027,8 +2030,8 @@ { tlb_inval_required = true; - r_dcache_tlb_inval_count = 0; - r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>> + r_dcache_tlb_inval_count = 0; + r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>> (uint32_log2(m_dcache_words<<2)); - r_dcache_in_tlb[way*m_dcache_sets+set] = false; + r_dcache_in_tlb[way*m_dcache_sets+set] = false; } else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) @@ -2036,5 +2039,5 @@ r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; } @@ -3295,11 +3298,11 @@ } //////////////////////// - case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction. - // We consume the response in rsp FIFO, - // and exit the sub-fsm, but we don't - // analyse the response, because we don't - // care if the L/R bit update is not done. - // We must take the coherence requests because - // there is a risk of dead-lock + case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction. + // We consume the response in rsp FIFO, + // and exit the sub-fsm, but we don't + // analyse the response, because we don't + // care if the L/R bit update is not done. + // We must take the coherence requests because + // there is a risk of dead-lock { @@ -3544,37 +3547,37 @@ //////////////////////////// case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line - // Blocked if previous cleanup not completed + // Blocked if previous cleanup not completed // Test if itlb or dtlb inval is required { - if ( not r_dcache_cleanup_req.read() ) - { + if ( not r_dcache_cleanup_req.read() ) + { paddr_t nline; size_t way = r_dcache_xtn_way.read(); size_t set = r_dcache_xtn_set.read(); - bool hit; + bool hit; hit = r_dcache.inval( way, set, &nline ); - assert(hit && "XTN_DC_INVAL way/set should still be in cache"); + assert(hit && "XTN_DC_INVAL way/set should still be in cache"); // request cleanup - r_dcache_cleanup_req = true; - r_dcache_cleanup_line = nline; + r_dcache_cleanup_req = true; + r_dcache_cleanup_line = nline; // possible itlb & dtlb invalidate if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) { - r_dcache_tlb_inval_line = nline; - r_dcache_tlb_inval_count = 0; + r_dcache_tlb_inval_line = nline; + r_dcache_tlb_inval_count = 0; r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - r_dcache_in_tlb[way*m_dcache_sets+set] = false; - } + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + } else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) { r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; r_dcache_fsm = DCACHE_IDLE; m_drsp.valid = true; @@ -3655,5 +3658,5 @@ size_t way = r_dcache_miss_way.read(); size_t set = r_dcache_miss_set.read(); - bool hit; + bool hit; hit = r_dcache.inval( way, @@ -3661,5 +3664,5 @@ &nline ); - assert(hit && "selected way/set line should be in dcache"); + assert(hit && "selected way/set line should be in dcache"); #if DEBUG_DCACHE @@ -3686,5 +3689,5 @@ r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; r_dcache_fsm = DCACHE_MISS_WAIT; } @@ -3937,5 +3940,5 @@ vci_rsp_fifo_dcache_get = true; m_drsp.valid = true; - m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); r_dcache_fsm = DCACHE_IDLE; } @@ -3944,8 +3947,8 @@ ////////////////////////// case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory - // before handling a processor WRITE or SC request - // Input argument is r_dcache_dirty_paddr - // In this first state, we get PTE value in dcache - // and post a SC request to CMD FSM + // before handling a processor WRITE or SC request + // Input argument is r_dcache_dirty_paddr + // In this first state, we get PTE value in dcache + // and post a SC request to CMD FSM { // get PTE in dcache @@ -4009,61 +4012,12 @@ { vci_rsp_fifo_dcache_get = true; - if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic - { - r_dcache_fsm = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; #if DEBUG_DCACHE if ( m_debug_dcache_fsm ) { - std::cout << " Dirty bit successfully set" - << std::endl; + std::cout << " SC completed" << std::endl; } #endif - } - else // invalidate the cache line TLBs - { - -#if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " PTE modified : Inval cache line & TLBs" - << std::endl; -} -#endif - paddr_t nline; - size_t way = r_dcache_dirty_way.read(); - size_t set = r_dcache_dirty_set.read(); - bool hit; - - hit = r_dcache.inval( way, - set, - &nline ); - - assert(hit && "PTE should still be in dcache"); - - // request cleanup - r_dcache_cleanup_req = true; - r_dcache_cleanup_line = nline; - - if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE - { - r_dcache_tlb_inval_line = nline; - r_dcache_tlb_inval_count = 0; - r_dcache_fsm_scan_save = DCACHE_IDLE; - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - r_dcache_in_tlb[way*m_dcache_sets+set] = false; - } - else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD - { - r_itlb.reset(); - r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; - r_dcache_fsm = DCACHE_IDLE; - } - else - { - r_dcache_fsm = DCACHE_IDLE; - } - } } break; @@ -4099,13 +4053,13 @@ } - else // no match - { - uint32_t rdata; - size_t way; - size_t set; - size_t word; - - bool hit = r_dcache.read(paddr, - &rdata, // unused + else // no match for a pending miss + { + uint32_t rdata; + size_t way; + size_t set; + size_t word; + + bool hit = r_dcache.read( paddr, + &rdata, // unused &way, &set, @@ -4155,21 +4109,21 @@ } ///////////////////// - case DCACHE_CC_INVAL: // invalidate one cache line - // and test possible copies in TLBs - { - paddr_t nline; - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - bool hit; + case DCACHE_CC_INVAL: // invalidate one cache line after + // invalidation of copies in TLBs + { + paddr_t nline; + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + bool hit; if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval { r_dcache_in_tlb[way*m_dcache_sets+set] = false; - r_dcache_tlb_inval_line = nline; + r_dcache_tlb_inval_line = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2); r_dcache_tlb_inval_count = 0; r_dcache_fsm_scan_save = r_dcache_fsm.read(); r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; } - else // actual cache line inval + else // actual cache line inval { if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush @@ -4195,5 +4149,5 @@ #endif - assert(hit && "CC_INVAL way/set should still be in dcache"); + assert(hit && "CC_INVAL way/set should be in dcache"); } break;