Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h
===================================================================
--- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h	(revision 234)
+++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h	(revision 255)
@@ -6,20 +6,4 @@
 // This program is released under the GNU public license
 //////////////////////////////////////////////////////////////////////////////
-// This file define a TSAR cluster architecture with virtual memory:
-// - It uses the virtual_dspin_router  as distributed global interconnect 
-// - It uses the vci_local_crossbar as local interconnect 
-// - It uses the vci_cc_vcache_wrapper_v4
-// - It uses the vci_mem_cache_v4
-// - It contains a private RAM with a variable latency to emulate the L3 cache
-// - It can contains 1, 2 or 4 processors
-// - Each processor has a private dma channel (vci_multi_dma)
-// - It uses the vci_xicu interrupt controller
-// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster 
-//   containing address 0xBFC00000.
-// - The Multi-TTY component controls 4 terminals. 
-// - The nprocs dma irqs are connected to IRQ_IN[0]...IRQ_IN[3]
-// - The four tty irqs are connected to IRQ_IN[4]...IRQ_IN[7]
-// - The bdev irq is connected to IRQ_IN[8]
-////////////////////////////////////////////////////////////////////////////////// 
 
 #ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H
@@ -62,19 +46,16 @@
 
 	// Ports
-    	sc_in<bool>                             		p_clk;
-    	sc_in<bool>                             		p_resetn;
+    sc_in<bool>                             		p_clk;
+    sc_in<bool>                             		p_resetn;
 	soclib::caba::DspinOutput<cmd_width>   			**p_cmd_out;
 	soclib::caba::DspinInput<cmd_width>    			**p_cmd_in;
-        soclib::caba::DspinOutput<rsp_width>                   	**p_rsp_out;
-        soclib::caba::DspinInput<rsp_width>                   	**p_rsp_in;
+    soclib::caba::DspinOutput<rsp_width>           	**p_rsp_out;
+    soclib::caba::DspinInput<rsp_width>            	**p_rsp_in;
 
-        // interrupt signals
-	sc_signal<bool>     		signal_false;
-	sc_signal<bool> 		signal_proc_it[4];
-	sc_signal<bool> 		signal_irq_mdma[4];
-	sc_signal<bool>			signal_irq_tty0;
-	sc_signal<bool>			signal_irq_tty1;
-	sc_signal<bool>			signal_irq_tty2;
-	sc_signal<bool>			signal_irq_tty3;
+    // interrupt signals
+	sc_signal<bool>     	signal_false;
+	sc_signal<bool> 		signal_proc_it[8];
+	sc_signal<bool> 		signal_irq_mdma[8];
+	sc_signal<bool>			signal_irq_mtty[23];
 	sc_signal<bool> 		signal_irq_bdev;
 	
@@ -117,57 +98,60 @@
 	VciSignals<vci_param> 		signal_vci_xram;
 	
-        // Components
+    // Components
 
-        VciCcVCacheWrapperV4<vci_param, iss_t>*                 	proc[4];
-        VciMemCacheV4<vci_param>*                               	memc;
-        VciXicu<vci_param>*                                     	xicu;
-        VciLocalCrossbar<vci_param>*        				xbard;
-        VciLocalCrossbar<vci_param>*        				xbarc;
-        VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*		tgtwrapperd;
-        VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*	iniwrapperd;
-        VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*		tgtwrapperc;
-        VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*	iniwrapperc;
-        VirtualDspinRouter<cmd_width>*   	                	cmdrouter;
-        VirtualDspinRouter<rsp_width>*	                        	rsprouter;
-        VciSimpleRam<vci_param>*                 			brom;
-        VciMultiTty<vci_param>*                  			mtty;
-        VciFrameBuffer<vci_param>*               			fbuf;
-        VciBlockDeviceTsarV4<vci_param>*         			bdev;
-        VciMultiDma<vci_param>*                 			mdma;
-        VciSimpleRam<vci_param>*					xram;
+    VciCcVCacheWrapperV4<vci_param, iss_t>*                 	proc[8];
+    VciMemCacheV4<vci_param>*                               	memc;
+    VciXicu<vci_param>*                                     	xicu;
+    VciLocalCrossbar<vci_param>*                                xbard;
+    VciLocalCrossbar<vci_param>*                                xbarc;
+    VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*      tgtwrapperd;
+    VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*   iniwrapperd;
+    VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*      tgtwrapperc;
+    VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*   iniwrapperc;
+    VirtualDspinRouter<cmd_width>*                              cmdrouter;
+    VirtualDspinRouter<rsp_width>*	                        	rsprouter;
+    VciSimpleRam<vci_param>*                                    brom;
+    VciMultiTty<vci_param>*                                     mtty;
+    VciFrameBuffer<vci_param>*                                  fbuf;
+    VciBlockDeviceTsarV4<vci_param>*                            bdev;
+    VciMultiDma<vci_param>*                                     mdma;
+    VciSimpleRam<vci_param>*                                    xram;
 
-	TsarV4ClusterMmu(sc_module_name  insname,
-                        size_t           nprocs,			    // number of processors 
-			size_t           n_x,				    // x coordinate
-			size_t           n_y,				    // y coordinate
-			size_t           n_cluster,			    // y + ymax*x
-			const            soclib::common::MappingTable &mtd, // direct mapping table
-			const            soclib::common::MappingTable &mtc, // coherence mapping table
-			const            soclib::common::MappingTable &mtx, // xram mapping table
-			size_t	         x_width,			    // x field number of bits
-			size_t	         y_width,			    // y field number of bits
-                        size_t	         tgtid_memc,
-                        size_t	         tgtid_xicu,
-                        size_t	         tgtid_fbuf,
-                        size_t           tgtid_mtty,
-                        size_t           tgtid_brom,
-                        size_t           tgtid_bdev,
-                        size_t           tgtid_mdma,
-                        size_t           memc_ways,			    // number of ways for MEMC
-                        size_t           memc_sets,			    // number of sets for MEMC
-                        size_t           l1_i_ways,			    // number of ways for L1 ICACHE
-                        size_t           l1_i_sets,			    // number of sets for L1 ICACHE
-                        size_t           l1_d_ways,			    // number of ways for L1 DCACHE
-                        size_t           l1_d_sets,			    // number of sets for L1 DCACHE
-                        size_t           xram_latency,			    // external ram latency
-			bool             io,				    // I/O cluster if true
-                        size_t           xfb,				    // frame buffer pixels
-                        size_t           yfb,				    // frame buffer lines
-                        char*            disk_name,			    // virtual disk name for BDEV
-                        size_t           block_size,			    // block size for BDEV
-			const Loader    &loader, 			    // loader for BROM
-                        uint32_t         frozen_cycles,			    // max frozen cycles
-                        uint32_t         start_debug_cycle,
-                        bool             debug_ok); 
+	TsarV4ClusterMmu(sc_module_name                     insname,
+                     size_t                             nb_procs,      // number of processors 
+                     size_t                             nb_ttys,       // number of TTY terminals 
+                     size_t                             nb_dmas,       // number of DMA channels 
+                     size_t                             x,             // x coordinate
+                     size_t                             y,             // y coordinate
+                     size_t                             cluster,       // y + ymax*x
+                     const soclib::common::MappingTable &mtd,          // direct mapping table
+                     const soclib::common::MappingTable &mtc,          // coherence mapping table
+                     const soclib::common::MappingTable &mtx,          // xram mapping table
+                     size_t	                            x_width,       // x field number of bits
+                     size_t	                            y_width,       // y field number of bits
+                     size_t	                            tgtid_memc,
+                     size_t	                            tgtid_xicu,
+                     size_t	                            tgtid_fbuf,
+                     size_t                             tgtid_mtty,
+                     size_t                             tgtid_brom,
+                     size_t                             tgtid_bdev,
+                     size_t                             tgtid_mdma,
+                     size_t                             memc_ways,
+                     size_t                             memc_sets,
+                     size_t                             l1_i_ways,
+                     size_t                             l1_i_sets, 
+                     size_t                             l1_d_ways,
+                     size_t                             l1_d_sets,	
+                     size_t                             xram_latency,  // external ram latency
+                     bool                               io,	           // I/O cluster if true
+                     size_t                             xfb,           // frame buffer pixels
+                     size_t                             yfb,           // frame buffer lines
+                     char*                              disk_name,     // virtual disk name for BDEV
+                     size_t                             block_size,    // block size for BDEV
+			         const Loader                       &loader,       // loader for BROM
+                     uint32_t                           frozen_cycles, // max frozen cycles
+                     uint32_t                           start_debug_cycle,
+                     bool                               memc_debug_ok, 
+                     bool                               proc_debug_ok); 
 
 	~TsarV4ClusterMmu();
