Index: trunk/platforms/tsarv4_generic_mmu/top.cpp =================================================================== --- trunk/platforms/tsarv4_generic_mmu/top.cpp (revision 254) +++ trunk/platforms/tsarv4_generic_mmu/top.cpp (revision 255) @@ -3,5 +3,5 @@ // Author: Alain Greiner // Copyright: UPMC/LIP6 -// Date : june 2011 +// Date : august 2012 // This program is released under the GNU public license ///////////////////////////////////////////////////////////////////////// @@ -11,24 +11,28 @@ // - It uses the vci_cc_vcache_wrapper_v4 // - It uses the vci_mem_cache_v4 -// - It uses one vci_xicu, one vci_multi_tty, -// and one vci_multi_dma controler per cluster. -// +// - It contains one vci_xicu and one vci_multi_dma per cluster. +// The peripherals BDEV, FBUF, MTTY, and the boot BROM +// are in the cluster containing address 0xBFC00000. +// // It is build with one single component implementing a cluster: // The Tsarv4ClusterMmu component is defined in files // tsarv4_cluster_mmu.* (with * = cpp, h, sd) // +// The IRQs are connected to XICUs as follow: +// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. +// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. +// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. +// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. +// // The physical address space is 32 bits. // The number of clusters cannot be larger than 256. -// The number of processors per cluster cannot be larger than 4. -// The parameters must be power of 2. -// - xmax : number of clusters in a row -// - ymax : number of clusters in a column -// - nprocs : number of processors per cluster +// The number of processors per cluster cannot be larger than 8. // -// The peripherals BDEV, FBUF, and the boot BROM -// are in the cluster containing address 0xBFC00000. -// - The nprocs TTY IRQs are connected to IRQ_IN[0] to IRQ_IN[3] -// - The nprocs DMA IRQs are connected to IRQ_IN[4] to IRQ_IN[7] -// - The IOC IRQ is connected to IRQ_IN[8] +// The hardware parameters are : +// - xmax : number of clusters in a row (power of 2) +// - ymax : number of clusters in a column (power of 2) +// - nb_procs : number of processors per cluster (power of 2) +// - nb_dmas : number of DMA channels per cluster (< 9) +// - nb_ttys : number of TTYs in I/O cluster (< 16) // // General policy for 32 bits physical address decoding: @@ -97,28 +101,34 @@ /////////////////////////////////////////////////// -#define MESH_XMAX 2 -#define MESH_YMAX 2 - -#define NPROCS 4 -#define XRAM_LATENCY 0 - -#define MEMC_WAYS 16 -#define MEMC_SETS 256 - -#define L1_IWAYS 4 -#define L1_ISETS 64 - -#define L1_DWAYS 4 -#define L1_DSETS 64 - -#define FBUF_X_SIZE 512 -#define FBUF_Y_SIZE 512 - -#define BDEV_SECTOR_SIZE 128 -#define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/couple_512.raw" - -#define BOOT_SOFT_NAME "../../softs/soft_transpose_giet/bin.soft" - -#define MAX_FROZEN_CYCLES 100000 +#define MESH_XMAX 2 +#define MESH_YMAX 2 + +#define NB_PROCS 1 +#define NB_TTYS 8 +#define NB_DMAS 1 + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 + +#define BDEV_SECTOR_SIZE 512 +#define BDEV_IMAGE_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/display/images.raw" + +#define BOOT_SOFT_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/soft.elf" + +#define MAX_FROZEN_CYCLES 10000 + +#define TRACE_MEMC_ID 1000000 +#define TRACE_PROC_ID 1000000 ///////////////////////////////////////////////////////// @@ -132,5 +142,5 @@ // There is 4 specific segments in the "IO" cluster // (containing address 0xBF000000) -// - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) +// - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) // - seg_fbuf -> FBUF / BASE = 0xBFD00000 (2 M bytes) // - seg_bdev -> BDEV / BASE = 0xBFF10000 @@ -142,19 +152,20 @@ /////////////////////////////////////////////////// -// specific segments in "IO" cluster +// specific segments in "IO" cluster : absolute physical address #define BROM_BASE 0xBFC00000 #define BROM_SIZE 0x00100000 -#define FBUF_BASE 0xBFD00000 +#define FBUF_BASE 0x80D00000 #define FBUF_SIZE 0x00200000 -#define BDEV_BASE 0xBFF10000 -#define BDEV_SIZE 0x00000020 - -#define MTTY_BASE 0xBFF20000 -#define MTTY_SIZE 0x00000040 - -// replicated segments +#define BDEV_BASE 0x80F10000 +#define BDEV_SIZE 0x00001000 + +#define MTTY_BASE 0x80F20000 +#define MTTY_SIZE 0x00001000 + +// replicated segments : physical address is incremented by an offset +// offset = cluster(x,y) << (address_width-x_width-y_width); #define MEMC_BASE 0x00000000 @@ -165,8 +176,5 @@ #define CDMA_BASE 0x00F30000 -#define CDMA_SIZE 0x00004000 - -#define PROC_BASE 0x00D00000 -#define PROC_SIZE 0x00000010 +#define CDMA_SIZE 0x00008000 //////////////////////////////////////////////////////////////////// @@ -191,10 +199,12 @@ - char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code + char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code size_t ncycles = 1000000000; // simulated cycles - size_t xmax = MESH_XMAX; // number of clusters in a row + size_t xmax = MESH_XMAX; // number of clusters in a row size_t ymax = MESH_YMAX; // number of clusters in a column - size_t nprocs = NPROCS; // number of processors per cluster - size_t xfb = FBUF_X_SIZE; // frameBuffer column number + size_t nb_procs = NB_PROCS; // number of processors per cluster + size_t nb_dmas = NB_DMAS; // number of RDMA channels per cluster + size_t nb_ttys = NB_TTYS; // number of TTY terminals in I/O cluster + size_t xfb = FBUF_X_SIZE; // frameBuffer column number size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number size_t memc_ways = MEMC_WAYS; @@ -206,22 +216,42 @@ char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) - size_t xram_latency = XRAM_LATENCY; // external RAM latency - bool trace_ok = false; // trace activated - size_t trace_period = 1; // trace period - uint32_t from_cycle = 0; // debug start cycle + size_t xram_latency = XRAM_LATENCY; // external RAM latency + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) + size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced + uint32_t debug_from = 0; // trace start cycle uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor ////////////// command line arguments ////////////////////// - if (argc > 1){ - for (int n = 1; n < argc; n = n + 2){ - if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1 offset = cluster(x,y) << (address_width-x_width-y_width); - // cleanup requests regarding the memc segment must be routed to the memory cache + // cleanup requests must be routed to the memory cache std::ostringstream sh; sh << "c_seg_memc_" << x << "_" << y; - maptabc.add(Segment(sh.str(), (nprocs << (address_width - srcid_width)) + offset, 0x10, IntTab(cluster(x,y), nprocs), false)); + maptabc.add(Segment(sh.str(), (nb_procs << (address_width - srcid_width)) + offset, + 0x10, IntTab(cluster(x,y), nb_procs), false)); // update & invalidate requests must be routed to the proper processor - for ( size_t p = 0 ; p < nprocs ; p++) { + for ( size_t p = 0 ; p < nb_procs ; p++) + { std::ostringstream sp; sp << "c_seg_proc_" << x << "_" << y << "_" << p; - maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 0x10 , IntTab(cluster(x,y), p) , false)); + maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , + 0x10 , IntTab(cluster(x,y), p) , false)); } } @@ -402,10 +469,13 @@ MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); - for (size_t x = 0; x < xmax; x++){ - for (size_t y = 0; y < ymax ; y++){ + for (size_t x = 0; x < xmax; x++) + { + for (size_t y = 0; y < ymax ; y++) + { sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); std::ostringstream sh; sh << "x_seg_memc_" << x << "_" << y; - maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false)); + maptabx.add(Segment(sh.str(), MEMC_BASE+offset, + MEMC_SIZE, IntTab(cluster(x,y)), false)); } } @@ -472,14 +542,19 @@ { #pragma omp for - for(size_t i = 0; i < (xmax * ymax); i++){ - size_t x = i / ymax; - size_t y = i % ymax; - + for(size_t i = 0; i < (xmax * ymax); i++) + { + size_t x = i / ymax; + size_t y = i % ymax; #pragma omp critical - std::ostringstream sc; - sc << "cluster_" << x << "_" << y; - clusters[x][y] = new TsarV4ClusterMmu + + std::cout << "building cluster_" << x << "_" << y << std::endl; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarV4ClusterMmu (sc.str().c_str(), - nprocs, + nb_procs, + nb_ttys, + nb_dmas, x, y, @@ -504,5 +579,5 @@ l1_d_sets, xram_latency, - (cluster(x,y) == cluster_io_index), + (cluster(x,y) == cluster_io_id), xfb, yfb, @@ -511,13 +586,19 @@ loader, frozen_cycles, - from_cycle, - trace_ok and (cluster_io_index == cluster(x,y)) ); - } + debug_from, + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id) ); + + std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; + + } } #else // NO OPENMP - for (size_t x = 0; x < xmax; x++){ - for (size_t y = 0; y < ymax; y++){ + for (size_t x = 0; x < xmax; x++) + { + for (size_t y = 0; y < ymax; y++) + { std::cout << "building cluster_" << x << "_" << y << std::endl; @@ -527,5 +608,7 @@ clusters[x][y] = new TsarV4ClusterMmu (sc.str().c_str(), - nprocs, + nb_procs, + nb_ttys, + nb_dmas, x, y, @@ -550,5 +633,5 @@ l1_d_sets, xram_latency, - (cluster(x,y) == cluster_io_index), + (cluster(x,y) == cluster_io_id), xfb, yfb, @@ -557,6 +640,7 @@ loader, frozen_cycles, - from_cycle, - trace_ok and (cluster_io_index == cluster(x,y)) ); + debug_from, + debug_ok and ( cluster(x,y) == debug_memc_id ), + debug_ok and ( cluster(x,y) == debug_proc_id ) ); std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; @@ -618,6 +702,8 @@ // East & West boundary cluster connections - for (size_t y = 0; y < ymax; y++){ - for (size_t k = 0; k < 2; k++){ + for (size_t y = 0; y < ymax; y++) + { + for (size_t k = 0; k < 2; k++) + { clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); @@ -633,6 +719,8 @@ // North & South boundary clusters connections - for (size_t x = 0; x < xmax; x++){ - for (size_t k = 0; k < 2; k++){ + for (size_t x = 0; x < xmax; x++) + { + for (size_t k = 0; k < 2; k++) + { clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); @@ -677,58 +765,65 @@ signal_resetn = true; - for (size_t n = 1; n < ncycles; n++){ - if (trace_ok and (n > from_cycle) and (n % trace_period == 0)){ + for (size_t n = 1; n < ncycles; n++) + { + + if (debug_ok and (n > debug_from) and (n % debug_period == 0)) + { std::cout << "****************** cycle " << std::dec << n ; std::cout << " ************************************************" << std::endl; - // components cluster 00 ///////////////////// - // clusters[0][0]->proc[0]->print_trace(); - // clusters[0][0]->memc->print_trace(); - - // signals cluster 00 //////////////////////// - // clusters[0][0]->signal_vci_ini_d_proc[0].print_trace("proc_0_0_0_ini_d"); - // clusters[0][0]->signal_vci_ini_c_proc[0].print_trace("proc_0_0_0_ini_c"); - // clusters[0][0]->signal_vci_tgt_c_proc[0].print_trace("proc_0_0_0_tgt_c"); - // clusters[0][0]->signal_vci_xram.print_trace("memc_0_0_xram"); - - // components cluster 01 ///////////////////// - // clusters[0][1]->proc[0]->print_trace(); - // clusters[0][1]->memc->print_trace(); - - // signals cluster 01 /////////////////////// - // clusters[0][1]->signal_vci_ini_d_proc[0].print_trace("proc_0_1_0_ini_d"); - // clusters[0][1]->signal_vci_ini_c_proc[0].print_trace("proc_0_1_0_ini_c"); - // clusters[0][1]->signal_vci_tgt_c_proc[0].print_trace("proc_0_1_0_tgt_c"); - // clusters[0][1]->signal_vci_xram.print_trace("memc_0_1_xram"); - - // components cluster 10 //////////////////// - clusters[1][0]->proc[0]->print_trace(1); - clusters[1][0]->memc->print_trace(); - // clusters[1][0]->bdev->print_trace(); - // clusters[1][0]->mdma->print_trace(); - - // signals cluster 10 /////////////////////// - clusters[1][0]->signal_vci_ini_d_proc[0].print_trace("proc_1_0_0_ini_d"); - // clusters[1][0]->signal_vci_ini_c_proc[0].print_trace("proc_1_0_0_ini_c"); - // clusters[1][0]->signal_vci_tgt_c_proc[0].print_trace("proc_1_0_0_tgt_c"); - clusters[1][0]->signal_vci_tgt_d_memc.print_trace("memc_1_0_tgt_d "); - // clusters[1][0]->signal_vci_ini_c_memc.print_trace("memc_1_0_ini_c "); - // clusters[1][0]->signal_vci_tgt_c_memc.print_trace("memc_1_0_tgt_c "); - // clusters[1][0]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); - // clusters[1][0]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); - // clusters[1][0]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); - // clusters[1][0]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); - clusters[1][0]->signal_vci_tgt_d_mtty.print_trace("mtty_1_0_tgt_d "); - clusters[1][0]->signal_vci_xram.print_trace("memc_1_0_xram"); - - // components cluster 11 ///////////////////// - // clusters[1][1]->proc[0]->print_trace(); - // clusters[1][1]->memc->print_trace(); - - // signals cluster 11 //////////////////////// - // clusters[1][1]->signal_vci_ini_d_proc[0].print_trace("proc_1_1_0_ini_d"); - // clusters[1][1]->signal_vci_ini_c_proc[0].print_trace("proc_1_1_0_ini_c"); - // clusters[1][1]->signal_vci_tgt_c_proc[0].print_trace("proc_1_1_0_tgt_c"); - // clusters[1][1]->signal_vci_xram.print_trace("memc_1_1_xram"); + // trace proc[debug_proc_id] + if ( debug_proc_id < (xmax * ymax * nb_procs) ) + { + size_t proc_x = debug_proc_id / ymax; + size_t proc_y = debug_proc_id % ymax; + + clusters[proc_x][proc_y]->proc[0]->print_trace(); + + clusters[proc_x][proc_y]->signal_vci_ini_d_proc[0].print_trace("proc_ini_d"); + clusters[proc_x][proc_y]->signal_vci_ini_c_proc[0].print_trace("proc_ini_c"); + clusters[proc_x][proc_y]->signal_vci_tgt_c_proc[0].print_trace("proc_tgt_c"); + } + + // trace memc[debug_memc_id] + if ( debug_memc_id < (xmax * ymax) ) + { + size_t memc_x = debug_memc_id / ymax; + size_t memc_y = debug_memc_id % ymax; + + clusters[memc_x][memc_y]->memc->print_trace(); + + clusters[memc_x][memc_y]->signal_vci_tgt_d_memc.print_trace("memc_tgt_d"); + clusters[memc_x][memc_y]->signal_vci_ini_c_memc.print_trace("memc_ini_c"); + clusters[memc_x][memc_y]->signal_vci_tgt_c_memc.print_trace("memc_tgt_c"); + } + + // clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0"); + // clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1"); + // clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0"); + // clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1"); + + clusters[1][1]->mdma->print_trace(); + clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("dma_tgt_1_1"); + clusters[1][1]->signal_vci_ini_d_mdma.print_trace("dma_ini_1_1"); + if ( clusters[1][1]->signal_irq_mdma[0].read() ) + std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; + if ( clusters[1][1]->signal_proc_it[0].read() ) + std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; + + // trace peripherals components + if ( false ) + { + size_t io_x = cluster_io_id / ymax; + size_t io_y = cluster_io_id % ymax; + + clusters[io_x][io_y]->bdev->print_trace(); + clusters[io_x][io_y]->mdma->print_trace(); + + clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); + clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); + clusters[io_x][io_y]->signal_vci_tgt_d_mdma.print_trace("mdma_1_0_tgt_d "); + clusters[io_x][io_y]->signal_vci_ini_d_mdma.print_trace("mdma_1_0_ini_d "); + } } Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd =================================================================== --- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd (revision 254) +++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd (revision 255) @@ -16,19 +16,19 @@ Uses('common:mapping_table'), Uses('common:iss2'), - Uses('caba:vci_cc_vcache_wrapper_v4', + Uses('caba:vci_cc_vcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'), - Uses('caba:vci_mem_cache_v4'), - Uses('caba:vci_simple_ram'), - Uses('caba:vci_xicu'), - Uses('caba:vci_local_crossbar'), - Uses('caba:virtual_dspin_router', + Uses('caba:vci_mem_cache_v4'), + Uses('caba:vci_simple_ram'), + Uses('caba:vci_xicu'), + Uses('caba:vci_local_crossbar'), + Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('cmd_width')), - Uses('caba:virtual_dspin_router', + Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('rsp_width')), - Uses('caba:vci_vdspin_target_wrapper', + Uses('caba:vci_vdspin_target_wrapper', dspin_cmd_width = parameter.Reference('cmd_width'), dspin_rsp_width = parameter.Reference('rsp_width')), - Uses('caba:vci_vdspin_initiator_wrapper', + Uses('caba:vci_vdspin_initiator_wrapper', dspin_cmd_width = parameter.Reference('cmd_width'), dspin_rsp_width = parameter.Reference('rsp_width')), @@ -39,30 +39,4 @@ Uses('common:elf_file_loader'), ], - instance_parameters = [ - parameter.Int('n_x'), - parameter.Int('n_y'), - parameter.Int('n_cluster'), - parameter.Module('mtd', 'common:mapping_table'), - parameter.Module('mtc', 'common:mapping_table'), - parameter.Module('mtx', 'common:mapping_table'), - parameter.Int('x_width'), - parameter.Int('y_width'), - parameter.Int('memc_tgtid'), - parameter.Int('xicu_tgtid'), - parameter.Int('fbuf_tgtid'), - parameter.Int('mtty_tgtid'), - parameter.Int('brom_tgtid'), - parameter.Int('bdev_tgtid'), - parameter.Int('cdma_tgtid'), - parameter.Int('memc_ways'), - parameter.Int('memc_sets'), - parameter.Int('l1_i_ways'), - parameter.Int('l1_i_sets'), - parameter.Int('l1_d_ways'), - parameter.Int('l1_d_sets'), - parameter.Int('xram_latency'), - parameter.Bool('io'), - ], - ports = [ Port('caba:bit_in', 'p_resetn', auto = 'resetn'), @@ -71,5 +45,5 @@ Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), - Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), ], ) Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h =================================================================== --- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h (revision 254) +++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h (revision 255) @@ -6,20 +6,4 @@ // This program is released under the GNU public license ////////////////////////////////////////////////////////////////////////////// -// This file define a TSAR cluster architecture with virtual memory: -// - It uses the virtual_dspin_router as distributed global interconnect -// - It uses the vci_local_crossbar as local interconnect -// - It uses the vci_cc_vcache_wrapper_v4 -// - It uses the vci_mem_cache_v4 -// - It contains a private RAM with a variable latency to emulate the L3 cache -// - It can contains 1, 2 or 4 processors -// - Each processor has a private dma channel (vci_multi_dma) -// - It uses the vci_xicu interrupt controller -// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster -// containing address 0xBFC00000. -// - The Multi-TTY component controls 4 terminals. -// - The nprocs dma irqs are connected to IRQ_IN[0]...IRQ_IN[3] -// - The four tty irqs are connected to IRQ_IN[4]...IRQ_IN[7] -// - The bdev irq is connected to IRQ_IN[8] -////////////////////////////////////////////////////////////////////////////////// #ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H @@ -62,19 +46,16 @@ // Ports - sc_in p_clk; - sc_in p_resetn; + sc_in p_clk; + sc_in p_resetn; soclib::caba::DspinOutput **p_cmd_out; soclib::caba::DspinInput **p_cmd_in; - soclib::caba::DspinOutput **p_rsp_out; - soclib::caba::DspinInput **p_rsp_in; + soclib::caba::DspinOutput **p_rsp_out; + soclib::caba::DspinInput **p_rsp_in; - // interrupt signals - sc_signal signal_false; - sc_signal signal_proc_it[4]; - sc_signal signal_irq_mdma[4]; - sc_signal signal_irq_tty0; - sc_signal signal_irq_tty1; - sc_signal signal_irq_tty2; - sc_signal signal_irq_tty3; + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_it[8]; + sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_mtty[23]; sc_signal signal_irq_bdev; @@ -117,57 +98,60 @@ VciSignals signal_vci_xram; - // Components + // Components - VciCcVCacheWrapperV4* proc[4]; - VciMemCacheV4* memc; - VciXicu* xicu; - VciLocalCrossbar* xbard; - VciLocalCrossbar* xbarc; - VciVdspinTargetWrapper* tgtwrapperd; - VciVdspinInitiatorWrapper* iniwrapperd; - VciVdspinTargetWrapper* tgtwrapperc; - VciVdspinInitiatorWrapper* iniwrapperc; - VirtualDspinRouter* cmdrouter; - VirtualDspinRouter* rsprouter; - VciSimpleRam* brom; - VciMultiTty* mtty; - VciFrameBuffer* fbuf; - VciBlockDeviceTsarV4* bdev; - VciMultiDma* mdma; - VciSimpleRam* xram; + VciCcVCacheWrapperV4* proc[8]; + VciMemCacheV4* memc; + VciXicu* xicu; + VciLocalCrossbar* xbard; + VciLocalCrossbar* xbarc; + VciVdspinTargetWrapper* tgtwrapperd; + VciVdspinInitiatorWrapper* iniwrapperd; + VciVdspinTargetWrapper* tgtwrapperc; + VciVdspinInitiatorWrapper* iniwrapperc; + VirtualDspinRouter* cmdrouter; + VirtualDspinRouter* rsprouter; + VciSimpleRam* brom; + VciMultiTty* mtty; + VciFrameBuffer* fbuf; + VciBlockDeviceTsarV4* bdev; + VciMultiDma* mdma; + VciSimpleRam* xram; - TsarV4ClusterMmu(sc_module_name insname, - size_t nprocs, // number of processors - size_t n_x, // x coordinate - size_t n_y, // y coordinate - size_t n_cluster, // y + ymax*x - const soclib::common::MappingTable &mtd, // direct mapping table - const soclib::common::MappingTable &mtc, // coherence mapping table - const soclib::common::MappingTable &mtx, // xram mapping table - size_t x_width, // x field number of bits - size_t y_width, // y field number of bits - size_t tgtid_memc, - size_t tgtid_xicu, - size_t tgtid_fbuf, - size_t tgtid_mtty, - size_t tgtid_brom, - size_t tgtid_bdev, - size_t tgtid_mdma, - size_t memc_ways, // number of ways for MEMC - size_t memc_sets, // number of sets for MEMC - size_t l1_i_ways, // number of ways for L1 ICACHE - size_t l1_i_sets, // number of sets for L1 ICACHE - size_t l1_d_ways, // number of ways for L1 DCACHE - size_t l1_d_sets, // number of sets for L1 DCACHE - size_t xram_latency, // external ram latency - bool io, // I/O cluster if true - size_t xfb, // frame buffer pixels - size_t yfb, // frame buffer lines - char* disk_name, // virtual disk name for BDEV - size_t block_size, // block size for BDEV - const Loader &loader, // loader for BROM - uint32_t frozen_cycles, // max frozen cycles - uint32_t start_debug_cycle, - bool debug_ok); + TsarV4ClusterMmu(sc_module_name insname, + size_t nb_procs, // number of processors + size_t nb_ttys, // number of TTY terminals + size_t nb_dmas, // number of DMA channels + size_t x, // x coordinate + size_t y, // y coordinate + size_t cluster, // y + ymax*x + const soclib::common::MappingTable &mtd, // direct mapping table + const soclib::common::MappingTable &mtc, // coherence mapping table + const soclib::common::MappingTable &mtx, // xram mapping table + size_t x_width, // x field number of bits + size_t y_width, // y field number of bits + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_bdev, + size_t tgtid_mdma, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, // external ram latency + bool io, // I/O cluster if true + size_t xfb, // frame buffer pixels + size_t yfb, // frame buffer lines + char* disk_name, // virtual disk name for BDEV + size_t block_size, // block size for BDEV + const Loader &loader, // loader for BROM + uint32_t frozen_cycles, // max frozen cycles + uint32_t start_debug_cycle, + bool memc_debug_ok, + bool proc_debug_ok); ~TsarV4ClusterMmu(); Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp =================================================================== --- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (revision 254) +++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (revision 255) @@ -1,2 +1,27 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsarv4_cluster_mmu.c +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2011 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// This file define a TSAR cluster architecture with virtual memory: +// - It uses the virtual_dspin_router as distributed global interconnect +// - It uses the vci_local_crossbar as local interconnect +// - It uses the vci_cc_vcache_wrapper_v4 +// - It uses the vci_mem_cache_v4 +// - It contains a private RAM with a variable latency to emulate the L3 cache +// - It can contains 1, 2 or 4 processors +// - Each processor has a private dma channel (vci_multi_dma) +// - It uses the vci_xicu interrupt controller +// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster +// containing address 0xBFC00000. +// - The Multi-TTY component controls up to 15 terminals. +// - Each Multi-DMA component controls up to 8 DMA channels. +// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15] +// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30] +// - The BDEV IRQ is connected to IRQ_IN[31] +////////////////////////////////////////////////////////////////////////////////// + #include "../include/tsarv4_cluster_mmu.h" @@ -8,137 +33,115 @@ ////////////////////////////////////////////////////////////////////////// template - TsarV4ClusterMmu::TsarV4ClusterMmu( - sc_module_name insname, - size_t nprocs, - size_t x_id, - size_t y_id, - size_t cluster_id, - const soclib::common::MappingTable &mtd, - const soclib::common::MappingTable &mtc, - const soclib::common::MappingTable &mtx, - size_t x_width, - size_t y_width, - size_t tgtid_memc, - size_t tgtid_xicu, - size_t tgtid_fbuf, - size_t tgtid_mtty, - size_t tgtid_brom, - size_t tgtid_bdev, - size_t tgtid_mdma, - size_t memc_ways, - size_t memc_sets, - size_t l1_i_ways, - size_t l1_i_sets, - size_t l1_d_ways, - size_t l1_d_sets, - size_t xram_latency, - bool io, - size_t xfb, - size_t yfb, - char* disk_name, - size_t block_size, - const Loader &loader, - uint32_t frozen_cycles, - uint32_t debug_start_cycle, - bool debug_ok) +TsarV4ClusterMmu::TsarV4ClusterMmu( + sc_module_name insname, + size_t nb_procs, + size_t nb_ttys, + size_t nb_dmas, + size_t x_id, + size_t y_id, + size_t cluster_id, + const soclib::common::MappingTable &mtd, + const soclib::common::MappingTable &mtc, + const soclib::common::MappingTable &mtx, + size_t x_width, + size_t y_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_bdev, + size_t tgtid_mdma, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + bool io, + size_t xfb, + size_t yfb, + char* disk_name, + size_t block_size, + const Loader &loader, + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok) : soclib::caba::BaseModule(insname), p_clk("clk"), - p_resetn("resetn"), - - signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"), - signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"), - signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"), - signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"), - signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"), - signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"), - signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"), - signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), - - signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), - signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), - - signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), - signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"), - signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"), - signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"), - signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"), - signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"), - signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"), - - signal_vci_ini_c_memc("signal_vci_ini_c_memc"), - signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"), - - signal_vci_xram("signal_vci_xram") - - { - // Vectors of ports definition - - p_cmd_in = alloc_elems >("p_cmd_in", 2, 4); - p_cmd_out = alloc_elems >("p_cmd_out", 2, 4); - p_rsp_in = alloc_elems >("p_rsp_in", 2, 4); - p_rsp_out = alloc_elems >("p_rsp_out", 2, 4); - - // Components definition - - // on direct network : local srcid[proc] in [0...nprocs-1] - // on direct network : local srcid[mdma] = nprocs - // on direct network : local srcid[bdev] = nprocs + 1 - - // on coherence network : local srcid[proc] in [0...nprocs-1] - // on coherence network : local srcid[memc] = nprocs - - std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; - - for (size_t p = 0; p < nprocs; p++){ - std::ostringstream sproc; - sproc << "proc_" << x_id << "_" << y_id << "_" << p; - proc[p] = new VciCcVCacheWrapperV4( - sproc.str().c_str(), - cluster_id*nprocs + p, - mtd, // Mapping Table Direct - mtc, // Mapping Table Coherence - IntTab(cluster_id,p), // SRCID_D - IntTab(cluster_id,p), // SRCID_C - IntTab(cluster_id,p), // TGTID_C - 8, // ITLB ways - 8, // ITLB sets - 8, // DTLB ways - 8, // DTLB sets - l1_i_ways,l1_i_sets,16, // ICACHE size - l1_d_ways,l1_d_sets,16, // DCACHE size - 4, // WBUF width - 4, // WBUF depth - x_width, // X Width - y_width, // Y Width - nprocs, // Memory Cache Local Id (coherence) - frozen_cycles, // max frozen cycles - debug_start_cycle, - debug_ok); - } - - std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; - - std::ostringstream smemc; - smemc << "memc_" << x_id << "_" << y_id; - memc = new VciMemCacheV4( + p_resetn("resetn") + +{ + // Vectors of ports definition + + p_cmd_in = alloc_elems >("p_cmd_in", 2, 4); + p_cmd_out = alloc_elems >("p_cmd_out", 2, 4); + p_rsp_in = alloc_elems >("p_rsp_in", 2, 4); + p_rsp_out = alloc_elems >("p_rsp_out", 2, 4); + + // Components definition + + // on direct network : local srcid[proc] in [0..nb_procs-1] + // on direct network : local srcid[mdma] = nb_procs + // on direct network : local srcid[bdev] = nb_procs + 1 + + // on coherence network : local srcid[proc] in [0...nb_procs-1] + // on coherence network : local srcid[memc] = nb_procs + + std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; + + for (size_t p = 0; p < nb_procs; p++) + { + std::ostringstream sproc; + sproc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapperV4( + sproc.str().c_str(), + cluster_id*nb_procs + p, + mtd, // Mapping Table Direct + mtc, // Mapping Table Coherence + IntTab(cluster_id,p), // SRCID_D + IntTab(cluster_id,p), // SRCID_C + IntTab(cluster_id,p), // TGTID_C + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways,l1_i_sets,16, // ICACHE size + l1_d_ways,l1_d_sets,16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + nb_procs, // MEMC local index + frozen_cycles, // max frozen cycles + debug_start_cycle, + proc_debug_ok); + } + + std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; + + std::ostringstream smemc; + smemc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCacheV4( smemc.str().c_str(), mtd, mtc, mtx, - IntTab(cluster_id), // SRCID_X - IntTab(cluster_id, nprocs), // SRCID_C - IntTab(cluster_id, tgtid_memc), // TGTID_D - IntTab(cluster_id, nprocs), // TGTID_C - memc_ways, memc_sets, 16, // CACHE SIZE - 4096, // HEAP SIZE - 8, // TRANSACTION TABLE DEPTH - 8, // UPDATE TABLE DEPTH + IntTab(cluster_id), // SRCID_X + IntTab(cluster_id, nb_procs), // SRCID_C + IntTab(cluster_id, tgtid_memc), // TGTID_D + IntTab(cluster_id, nb_procs), // TGTID_C + memc_ways, memc_sets, 16, // CACHE SIZE + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH debug_start_cycle, - debug_ok); - - - std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; - - std::ostringstream sxram; - sxram << "xram_" << x_id << "_" << y_id; - xram = new VciSimpleRam( + memc_debug_ok); + + std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sxram; + sxram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( sxram.str().c_str(), IntTab(cluster_id), @@ -147,106 +150,99 @@ xram_latency); - std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; - - size_t nhwi = 4; // always 4 (or 9) ports, even if - if (io){ - nhwi = 9; // there if less than 4 processors - } - std::ostringstream sicu; - sicu << "xicu_" << x_id << "_" << y_id; - xicu = new VciXicu( + std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sicu; + sicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( sicu.str().c_str(), - mtd, // mapping table - IntTab(cluster_id, tgtid_xicu), // TGTID_D - 0, // number of timer IRQs - nhwi, // number of hard IRQs - 0, // number of soft IRQs - nprocs); // number of output IRQs - - std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; - - // dma multi-canaux - std::ostringstream sdma; - sdma << "dma_" << x_id << "_" << y_id; - mdma = new VciMultiDma( + mtd, // mapping table + IntTab(cluster_id, tgtid_xicu), // TGTID_D + nb_procs, // number of timer IRQs + 32, // number of hard IRQs + 0, // number of soft IRQs + nb_procs); // number of output IRQs + + std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sdma; + sdma << "dma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( sdma.str().c_str(), mtd, - IntTab(cluster_id, nprocs), // SRCID + IntTab(cluster_id, nb_procs), // SRCID IntTab(cluster_id, tgtid_mdma), // TGTID 64, // burst size - nprocs); // number of IRQs - - std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; - - // direct local crossbar - size_t nb_direct_initiators = nprocs + 1; - size_t nb_direct_targets = 3; - if (io){ - nb_direct_initiators = nprocs + 2; - nb_direct_targets = 7; - } - std::ostringstream sd; - sd << "xbard_" << x_id << "_" << y_id; - xbard = new VciLocalCrossbar( + nb_procs); // number of IRQs + + std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; + + size_t nb_direct_initiators = nb_procs + 1; + size_t nb_direct_targets = 3; + if ( io ) + { + nb_direct_initiators = nb_procs + 2; + nb_direct_targets = 7; + } + std::ostringstream sd; + sd << "xbard_" << x_id << "_" << y_id; + xbard = new VciLocalCrossbar( sd.str().c_str(), mtd, - IntTab(cluster_id), // cluster initiator index - IntTab(cluster_id), // cluster target index - nb_direct_initiators, // number of initiators - nb_direct_targets); // number of targets - - std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; - - // coherence local crossbar - std::ostringstream sc; - sc << "xbarc_" << x_id << "_" << y_id; - xbarc = new VciLocalCrossbar( + IntTab(cluster_id), // cluster initiator index + IntTab(cluster_id), // cluster target index + nb_direct_initiators, // number of initiators + nb_direct_targets); // number of targets + + std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sc; + sc << "xbarc_" << x_id << "_" << y_id; + xbarc = new VciLocalCrossbar( sc.str().c_str(), mtc, - IntTab(cluster_id), // cluster initiator index - IntTab(cluster_id), // cluster target index - nprocs + 1, // number of initiators - nprocs + 1); // number of targets - - std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; - - // direct initiator wrapper - std::ostringstream wid; - wid << "iniwrapperd_" << x_id << "_" << y_id; - iniwrapperd = new VciVdspinInitiatorWrapper( + IntTab(cluster_id), // cluster initiator index + IntTab(cluster_id), // cluster target index + nb_procs + 1, // number of initiators + nb_procs + 1); // number of targets + + std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; + + // direct initiator wrapper + std::ostringstream wid; + wid << "iniwrapperd_" << x_id << "_" << y_id; + iniwrapperd = new VciVdspinInitiatorWrapper( wid.str().c_str(), 4, // cmd fifo depth 4); // rsp fifo depth - // direct target wrapper - std::ostringstream wtd; - wtd << "tgtwrapperd_" << x_id << "_" << y_id; - tgtwrapperd = new VciVdspinTargetWrapper( + // direct target wrapper + std::ostringstream wtd; + wtd << "tgtwrapperd_" << x_id << "_" << y_id; + tgtwrapperd = new VciVdspinTargetWrapper( wtd.str().c_str(), 4, // cmd fifo depth 4); // rsp fifo depth - // coherence initiator wrapper - std::ostringstream wic; - wic << "iniwrapperc_" << x_id << "_" << y_id; - iniwrapperc = new VciVdspinInitiatorWrapper( + // coherence initiator wrapper + std::ostringstream wic; + wic << "iniwrapperc_" << x_id << "_" << y_id; + iniwrapperc = new VciVdspinInitiatorWrapper( wic.str().c_str(), 4, // cmd fifo depth 4); // rsp fifo depth - // coherence target wrapper - std::ostringstream wtc; - wtc << "tgtwrapperc_" << x_id << "_" << y_id; - tgtwrapperc = new VciVdspinTargetWrapper( - wtc.str().c_str(), + // coherence target wrapper + std::ostringstream wtc; + wtc << "tgtwrapperc_" << x_id << "_" << y_id; + tgtwrapperc = new VciVdspinTargetWrapper( + wtc.str().c_str(), 4, // cmd fifo depth 4); // rsp fifo depth - std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; - - // CMD router - std::ostringstream scmd; - scmd << "cmdrouter_" << x_id << "_" << y_id; - cmdrouter = new VirtualDspinRouter( + std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; + + std::ostringstream scmd; + scmd << "cmdrouter_" << x_id << "_" << y_id; + cmdrouter = new VirtualDspinRouter( scmd.str().c_str(), x_id,y_id, // coordinate in the mesh @@ -254,10 +250,10 @@ 4,4); // input & output fifo depths - std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; - - // RSP router - std::ostringstream srsp; - srsp << "rsprouter_" << x_id << "_" << y_id; - rsprouter = new VirtualDspinRouter( + std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; + + // RSP router + std::ostringstream srsp; + srsp << "rsprouter_" << x_id << "_" << y_id; + rsprouter = new VirtualDspinRouter( srsp.str().c_str(), x_id,y_id, // coordinates in mesh @@ -265,7 +261,10 @@ 4,4); // input & output fifo depths - // IO cluster components - if (io){ - brom = new VciSimpleRam( + // IO cluster components + if ( io ) + { + std::cout << " - building brom" << std::endl; + + brom = new VciSimpleRam( "brom", IntTab(cluster_id, tgtid_brom), @@ -273,5 +272,7 @@ loader); - fbuf = new VciFrameBuffer( + std::cout << " - building fbuf" << std::endl; + + fbuf = new VciFrameBuffer( "fbuf", IntTab(cluster_id, tgtid_fbuf), @@ -279,199 +280,250 @@ xfb, yfb); - bdev = new VciBlockDeviceTsarV4( + std::cout << " - building fbuf" << std::endl; + + bdev = new VciBlockDeviceTsarV4( "bdev", mtd, - IntTab(cluster_id, nprocs+1), + IntTab(cluster_id, nb_procs+1), IntTab(cluster_id, tgtid_bdev), disk_name, - block_size); - - mtty = new VciMultiTty( + block_size, + 4); // burst size + + std::cout << " - building mtty" << std::endl; + + std::vector vect_names; + for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ ) + { + std::ostringstream term_name; + term_name << "term" << tid; + vect_names.push_back(term_name.str().c_str()); + } + mtty = new VciMultiTty( "mtty", IntTab(cluster_id, tgtid_mtty), mtd, - "tty0", "tty1", "tty2", "tty3", NULL); - } - - std::cout << " - all components constructed" << std::endl; - - //////////////////////////////////// - // Connections are defined here - //////////////////////////////////// - - // CMDROUTER and RSPROUTER - cmdrouter->p_clk (this->p_clk); - cmdrouter->p_resetn (this->p_resetn); - rsprouter->p_clk (this->p_clk); - rsprouter->p_resetn (this->p_resetn); - for (int x = 0; x < 2; x++){ - for(int y = 0; y < 4; y++){ - cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); - cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); - rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); - rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); - } - } - - cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); - cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); - cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); - cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); - - rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); - rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); - rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); - rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); - - // VCI/DSPIN WRAPPERS - iniwrapperd->p_clk (this->p_clk); - iniwrapperd->p_resetn (this->p_resetn); - iniwrapperd->p_vci (signal_vci_l2g_d); - iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); - iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); - - tgtwrapperd->p_clk (this->p_clk); - tgtwrapperd->p_resetn (this->p_resetn); - tgtwrapperd->p_vci (signal_vci_g2l_d); - tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); - tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); - - iniwrapperc->p_clk (this->p_clk); - iniwrapperc->p_resetn (this->p_resetn); - iniwrapperc->p_vci (signal_vci_l2g_c); - iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); - iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); - - tgtwrapperc->p_clk (this->p_clk); - tgtwrapperc->p_resetn (this->p_resetn); - tgtwrapperc->p_vci (signal_vci_g2l_c); - tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); - tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); - - // CROSSBAR direct - xbard->p_clk (this->p_clk); - xbard->p_resetn (this->p_resetn); - xbard->p_initiator_to_up (signal_vci_l2g_d); - xbard->p_target_to_up (signal_vci_g2l_d); - - xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); - xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); - xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); - - xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); - - for (size_t p = 0; p < nprocs; p++){ - xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); - } - - if (io){ - xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); - xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); - xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); - xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); - - xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); - } - - // CROSSBAR coherence - xbarc->p_clk (this->p_clk); - xbarc->p_resetn (this->p_resetn); - xbarc->p_initiator_to_up (signal_vci_l2g_c); - xbarc->p_target_to_up (signal_vci_g2l_c); - xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); - xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); - for (size_t p = 0; p < nprocs; p++) { - xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); - xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); - } - - // Processors - for (size_t p = 0; p < nprocs; p++){ - proc[p]->p_clk (this->p_clk); - proc[p]->p_resetn (this->p_resetn); - proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); - proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); - proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); - proc[p]->p_irq[0] (signal_proc_it[p]); - for ( size_t j = 1 ; j < 6 ; j++){ - proc[p]->p_irq[j] (signal_false); - } - } - - // XICU - xicu->p_clk (this->p_clk); - xicu->p_resetn (this->p_resetn); - xicu->p_vci (signal_vci_tgt_d_xicu); - for (size_t p = 0; p < nprocs; p++){ - xicu->p_irq[p] (signal_proc_it[p]); - } - for (size_t p = 0; p < nprocs; p++){ - xicu->p_hwi[p] (signal_irq_mdma[p]); - } - for (size_t x = nprocs; x < 4; x++){ - xicu->p_hwi[x] (signal_false); - } - - if (io){ - xicu->p_hwi[4] (signal_irq_tty0); - xicu->p_hwi[5] (signal_irq_tty1); - xicu->p_hwi[6] (signal_irq_tty2); - xicu->p_hwi[7] (signal_irq_tty3); - - xicu->p_hwi[8] (signal_irq_bdev); - } - - // MEMC - memc->p_clk (this->p_clk); - memc->p_resetn (this->p_resetn); - memc->p_vci_ixr (signal_vci_xram); - memc->p_vci_tgt (signal_vci_tgt_d_memc); - memc->p_vci_ini (signal_vci_ini_c_memc); - memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); - - // XRAM - xram->p_clk (this->p_clk); - xram->p_resetn (this->p_resetn); - xram->p_vci (signal_vci_xram); - - // CDMA - mdma->p_clk (this->p_clk); - mdma->p_resetn (this->p_resetn); - mdma->p_vci_target (signal_vci_tgt_d_mdma); - mdma->p_vci_initiator (signal_vci_ini_d_mdma); - for (size_t p = 0; p < nprocs; p++){ - mdma->p_irq[p] (signal_irq_mdma[p]); - } - - // Components in IO cluster - - if (io){ - // BDEV - bdev->p_clk (this->p_clk); - bdev->p_resetn (this->p_resetn); - bdev->p_irq (signal_irq_bdev); - bdev->p_vci_target (signal_vci_tgt_d_bdev); - bdev->p_vci_initiator (signal_vci_ini_d_bdev); - - // FBUF - fbuf->p_clk (this->p_clk); - fbuf->p_resetn (this->p_resetn); - fbuf->p_vci (signal_vci_tgt_d_fbuf); - - // BROM - brom->p_clk (this->p_clk); - brom->p_resetn (this->p_resetn); - brom->p_vci (signal_vci_tgt_d_brom); - - // MTTY - mtty->p_clk (this->p_clk); - mtty->p_resetn (this->p_resetn); - mtty->p_vci (signal_vci_tgt_d_mtty); - mtty->p_irq[0] (signal_irq_tty0); - mtty->p_irq[1] (signal_irq_tty1); - mtty->p_irq[2] (signal_irq_tty2); - mtty->p_irq[3] (signal_irq_tty3); - } - } // end constructor + vect_names); + } + + std::cout << std::endl; + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + // CMDROUTER and RSPROUTER + cmdrouter->p_clk (this->p_clk); + cmdrouter->p_resetn (this->p_resetn); + rsprouter->p_clk (this->p_clk); + rsprouter->p_resetn (this->p_resetn); + for (int x = 0; x < 2; x++) + { + for(int y = 0; y < 4; y++) + { + cmdrouter->p_out[x][y] (this->p_cmd_out[x][y]); + cmdrouter->p_in[x][y] (this->p_cmd_in[x][y]); + rsprouter->p_out[x][y] (this->p_rsp_out[x][y]); + rsprouter->p_in[x][y] (this->p_rsp_in[x][y]); + } + } + + cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); + cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); + cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); + cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); + + rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); + rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); + rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); + rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); + + std::cout << " - CMD & RSP routers connected" << std::endl; + + // VCI/DSPIN WRAPPERS + iniwrapperd->p_clk (this->p_clk); + iniwrapperd->p_resetn (this->p_resetn); + iniwrapperd->p_vci (signal_vci_l2g_d); + iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); + iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); + + tgtwrapperd->p_clk (this->p_clk); + tgtwrapperd->p_resetn (this->p_resetn); + tgtwrapperd->p_vci (signal_vci_g2l_d); + tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); + tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); + + iniwrapperc->p_clk (this->p_clk); + iniwrapperc->p_resetn (this->p_resetn); + iniwrapperc->p_vci (signal_vci_l2g_c); + iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); + iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); + + tgtwrapperc->p_clk (this->p_clk); + tgtwrapperc->p_resetn (this->p_resetn); + tgtwrapperc->p_vci (signal_vci_g2l_c); + tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); + tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); + + std::cout << " - VCI/DSPIN wrappers connected" << std::endl; + + // CROSSBAR direct + xbard->p_clk (this->p_clk); + xbard->p_resetn (this->p_resetn); + xbard->p_initiator_to_up (signal_vci_l2g_d); + xbard->p_target_to_up (signal_vci_g2l_d); + + xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); + xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); + xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); + + xbard->p_to_initiator[nb_procs] (signal_vci_ini_d_mdma); + + for (size_t p = 0; p < nb_procs; p++) + { + xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); + } + + if ( io ) + { + xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); + xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); + xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); + xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); + + xbard->p_to_initiator[nb_procs+1] (signal_vci_ini_d_bdev); + } + + std::cout << " - Direct crossbar connected" << std::endl; + + // CROSSBAR coherence + xbarc->p_clk (this->p_clk); + xbarc->p_resetn (this->p_resetn); + xbarc->p_initiator_to_up (signal_vci_l2g_c); + xbarc->p_target_to_up (signal_vci_g2l_c); + xbarc->p_to_initiator[nb_procs] (signal_vci_ini_c_memc); + xbarc->p_to_target[nb_procs] (signal_vci_tgt_c_memc); + for (size_t p = 0; p < nb_procs; p++) + { + xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); + xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); + } + + std::cout << " - Coherence crossbar connected" << std::endl; + + // Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); + proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); + proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); + proc[p]->p_irq[0] (signal_proc_it[p]); + for ( size_t j = 1 ; j < 6 ; j++) + { + proc[p]->p_irq[j] (signal_false); + } + } + + std::cout << " - Processors connected" << std::endl; + + // XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_vci_tgt_d_xicu); + for ( size_t p=0 ; pp_irq[p] (signal_proc_it[p]); + } + for ( size_t i=0 ; i<32 ; i++) + { + if ( io ) // I/O cluster + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]); + else if (i < 16) xicu->p_hwi[i] (signal_false); + else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]); + else if (i < 31) xicu->p_hwi[i] (signal_false); + else xicu->p_hwi[i] (signal_irq_bdev); + } + else // other clusters + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]); + else xicu->p_hwi[i] (signal_false); + } + } + + std::cout << " - XICU connected" << std::endl; + + // MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_vci_ixr (signal_vci_xram); + memc->p_vci_tgt (signal_vci_tgt_d_memc); + memc->p_vci_ini (signal_vci_ini_c_memc); + memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); + + std::cout << " - MEMC connected" << std::endl; + + // XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_vci_xram); + + std::cout << " - XRAM connected" << std::endl; + + // CDMA + mdma->p_clk (this->p_clk); + mdma->p_resetn (this->p_resetn); + mdma->p_vci_target (signal_vci_tgt_d_mdma); + mdma->p_vci_initiator (signal_vci_ini_d_mdma); + for (size_t i=0 ; ip_irq[i] (signal_irq_mdma[i]); + } + + std::cout << " - MDMA connected" << std::endl; + + // Components in I/O cluster + + if ( io ) + { + // BDEV + bdev->p_clk (this->p_clk); + bdev->p_resetn (this->p_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_d_bdev); + bdev->p_vci_initiator (signal_vci_ini_d_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // FBUF + fbuf->p_clk (this->p_clk); + fbuf->p_resetn (this->p_resetn); + fbuf->p_vci (signal_vci_tgt_d_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // BROM + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_vci_tgt_d_brom); + + std::cout << " - BROM connected" << std::endl; + + // MTTY + mtty->p_clk (this->p_clk); + mtty->p_resetn (this->p_resetn); + mtty->p_vci (signal_vci_tgt_d_mtty); + for ( size_t i=0 ; ip_irq[i] (signal_irq_mtty[i]); + } + + std::cout << " - MTTY connected" << std::endl; + } +} // end constructor /////////////////////////////////////////////////////////////////////////// @@ -479,5 +531,5 @@ /////////////////////////////////////////////////////////////////////////// template - TsarV4ClusterMmu::~TsarV4ClusterMmu() {} +TsarV4ClusterMmu::~TsarV4ClusterMmu() {} }