Index: /trunk/modules/vci_block_device_tsar_v4/caba/source/include/vci_block_device_tsar_v4.h =================================================================== --- /trunk/modules/vci_block_device_tsar_v4/caba/source/include/vci_block_device_tsar_v4.h (revision 259) +++ /trunk/modules/vci_block_device_tsar_v4/caba/source/include/vci_block_device_tsar_v4.h (revision 260) @@ -32,7 +32,9 @@ // This component can perform data transfers between one single file belonging // to the host system and a buffer in the memory of the virtual prototype. -// The file name is an argument of the constructor, -// as well as the block size (bytes), and the burst size (bytes). +// The file name is an argument of the constructor. // This component has a DMA capability, and is both a target and an initiator. +// The block size (bytes), and the burst size (bytes) must be power of 2. +// The burst size is typically a cache line. +// If the memory buffer is not constrained to be aligned on a burst boundary. // Both read and write transfers are supported. An IRQ is optionally // asserted when the transfer is completed. @@ -92,31 +94,35 @@ // Registers - sc_signal r_target_fsm; // target fsm state register - sc_signal r_initiator_fsm; // initiator fsm state register - sc_signal r_irq_enable; // default value is true - sc_signal r_nblocks; // number of blocks to be transfered - sc_signal r_buf_address; // memory buffer address - sc_signal r_lba; // first block index - sc_signal r_read; // requested operation - sc_signal r_flit_count; // flit counter (in a burst) - sc_signal r_burst_count; // burst counter (in a block) - sc_signal r_block_count; // block counter (in a transfer) - sc_signal r_latency_count; // latency access (for each block) - sc_signal r_go; // transmit command from T_FSM to M_FSM + sc_signal r_target_fsm; // target fsm state register + sc_signal r_initiator_fsm; // initiator fsm state register + sc_signal r_irq_enable; // default value is true + sc_signal r_nblocks; // number of blocks in transfer + sc_signal r_buf_address; // memory buffer address + sc_signal r_lba; // first block index + sc_signal r_read; // requested operation + sc_signal r_index; // flit index in local buffer + sc_signal r_latency_count; // latency counter + sc_signal r_flit_count; // flit counter (in a burst) + sc_signal r_burst_count; // burst counter (in a block) + sc_signal r_block_count; // block counter (in a transfer) + sc_signal r_burst_offset; // number of non aligned flits + sc_signal r_burst_nflits; // number of flits in a burst + sc_signal r_go; // command from T_FSM to M_FSM + sc_signal > r_srcid; // save srcid sc_signal > r_trdid; // save trdid sc_signal > r_pktid; // save pktid - uint32_t* m_local_buffer; // capacity is one block (block_size bytes) + uint32_t* r_local_buffer; // capacity is one block // structural parameters - soclib::common::Segment m_segment; // segment associated to target - uint32_t m_srcid; // initiator index - int m_fd; // File descriptor - uint64_t m_device_size; // Total number of blocks - const uint32_t m_flits_per_block; // number of flits in a block - const uint32_t m_flits_per_burst; // number of flits in a burst - const uint32_t m_bursts_per_block; // number of bursts in a block - const uint32_t m_latency; // device latency + soclib::common::Segment m_segment; // segment associated to target + uint32_t m_srcid; // initiator index + int m_fd; // File descriptor + uint64_t m_device_size; // Total number of blocks + const uint32_t m_flits_per_block; // number of flits in a block + const uint32_t m_flits_per_burst; // number of flits in a burst + const uint32_t m_bursts_per_block; // number of bursts in a block + const uint32_t m_latency; // device latency // methods @@ -127,14 +133,16 @@ enum { M_IDLE = 0, + M_READ_BLOCK = 1, - M_READ_CMD = 2, - M_READ_RSP = 3, - M_READ_TEST = 4, + M_READ_BURST = 2, + M_READ_CMD = 3, + M_READ_RSP = 4, M_READ_SUCCESS = 5, M_READ_ERROR = 6, - M_WRITE_BLOCK = 7, + + M_WRITE_BURST = 7, M_WRITE_CMD = 8, M_WRITE_RSP = 9, - M_WRITE_TEST = 10, + M_WRITE_BLOCK = 10, M_WRITE_SUCCESS = 11, M_WRITE_ERROR = 12, @@ -185,12 +193,12 @@ // Constructor VciBlockDeviceTsarV4( - sc_module_name name, + sc_module_name name, const soclib::common::MappingTable &mt, const soclib::common::IntTab &srcid, const soclib::common::IntTab &tgtid, - const std::string &filename, - const uint32_t block_size = 512, - const uint32_t burst_size = 64, - const uint32_t latency = 0); + const std::string &filename, + const uint32_t block_size = 512, + const uint32_t burst_size = 64, + const uint32_t latency = 0); }; Index: /trunk/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp =================================================================== --- /trunk/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp (revision 259) +++ /trunk/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp (revision 260) @@ -45,8 +45,8 @@ { r_initiator_fsm = M_IDLE; - r_target_fsm = T_IDLE; - r_irq_enable = true; - r_go = false; - return; + r_target_fsm = T_IDLE; + r_irq_enable = true; + r_go = false; + return; } @@ -57,4 +57,5 @@ switch(r_target_fsm) { + //////////// case T_IDLE: { @@ -64,27 +65,28 @@ r_trdid = p_vci_target.trdid.read(); r_pktid = p_vci_target.pktid.read(); - sc_dt::sc_uint address = p_vci_target.address.read(); + sc_dt::sc_uint address = p_vci_target.address.read(); bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); uint32_t cell = (uint32_t)((address & 0x1F)>>2); - if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; - else if( read && !m_segment.contains(address) ) r_target_fsm = T_READ_ERROR; - else if( !read && !p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; - else if( read && !p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; - else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; - else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; - else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; - else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; - else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; - else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; - else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; - else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; - else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; - else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; - else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; - else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; - } - break; - } + if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; + else if( read && !m_segment.contains(address) ) r_target_fsm = T_READ_ERROR; + else if( !read && !p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; + else if( read && !p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; + else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; + else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; + else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; + else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; + else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; + else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; + else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; + else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; + else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; + else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; + else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; + else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; + } + break; + } + //////////////////// case T_WRITE_BUFFER: { @@ -93,4 +95,5 @@ break; } + /////////////////// case T_WRITE_COUNT: { @@ -99,4 +102,5 @@ break; } + ///////////////// case T_WRITE_LBA: { @@ -105,4 +109,5 @@ break; } + //////////////// case T_WRITE_OP: { @@ -123,4 +128,5 @@ break; } + /////////////////// case T_WRITE_IRQEN: { @@ -129,4 +135,5 @@ break; } + /////////////////// case T_READ_BUFFER: case T_READ_COUNT: @@ -141,4 +148,5 @@ break; } + /////////////////// case T_READ_STATUS: { @@ -155,13 +163,25 @@ } // end switch target fsm - ///////////////////////////////////////////////////////////////////////// - // The initiator FSM controls the following registers : - // r_initiator_fsm, r_flit_count, r_block_count, m_local_buffer - ///////////////////////////////////////////////////////////////////////// - switch(r_initiator_fsm) { - case M_IDLE : // waiting for activation - { - if ( r_go ) - { + ////////////////////////////////////////////////////////////////////////////// + // The initiator FSM executes a loop, transfering one block per iteration. + // Each block is split in bursts, and the number of bursts depends + // on the memory buffer alignment on a burst boundary: + // - If buffer aligned, all burst have the same length (m_flits_per burst) + // and the number of bursts is (m_bursts_per_block). + // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) + // and first and last burst are shorter, because all flits in a burst + // must be contained in a single cache line. + // first burst => nflits = m_flits_per_burst - offset + // last burst => nflits = offset + // other burst => nflits = m_flits_per_burst + ////////////////////////////////////////////////////////////////////////////// + + switch( r_initiator_fsm.read() ) { + //////////// + case M_IDLE: // check buffer alignment to compute the number of bursts + { + if ( r_go.read() ) + { + r_index = 0; r_block_count = 0; r_burst_count = 0; @@ -169,10 +189,182 @@ r_latency_count = m_latency; - if ( r_read ) r_initiator_fsm = M_READ_BLOCK; - else r_initiator_fsm = M_WRITE_CMD; - } - break; - } + // compute r_burst_offset (zero when buffer aligned) + r_burst_offset = (r_buf_address.read()>>2) % m_flits_per_burst; + + // start tranfer + if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; + else r_initiator_fsm = M_WRITE_BURST; + } + break; + } + ////////////////// case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles + { + if ( r_latency_count.read() == 0 ) + { + r_latency_count = m_latency; + ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*4, SEEK_SET); + if( ::read(m_fd, r_local_buffer, m_flits_per_block*4) < 0 ) + { + r_initiator_fsm = M_READ_ERROR; + } + else + { + r_burst_count = 0; + r_flit_count = 0; + r_initiator_fsm = M_READ_BURST; + } + } + else + { + r_latency_count = r_latency_count.read() - 1; + } + break; + } + ////////////////// + case M_READ_BURST: // Compute the number of flits in the burst + { + uint32_t offset = r_burst_offset.read(); + + if ( offset ) // buffer not aligned + { + if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset; + else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset; + else r_burst_nflits = m_flits_per_burst; + } + else // buffer aligned + { + r_burst_nflits = m_flits_per_burst; + } + r_initiator_fsm = M_READ_CMD; + break; + } + //////////////// + case M_READ_CMD: // Send a multi-flits VCI WRITE command + { + if ( p_vci_initiator.cmdack.read() ) + { + if ( r_flit_count == (r_burst_nflits.read() - 1) ) // last flit in a burst + { + r_initiator_fsm = M_READ_RSP; + r_flit_count = 0; + } + else // not the last flit + { + r_flit_count = r_flit_count.read() + 1; + } + + // compute next flit address and next local buffer index + r_buf_address = r_buf_address.read() + 4; + r_index = r_index.read() + 1; + } + break; + } + //////////////// + case M_READ_RSP: // Wait a single flit VCI WRITE response + { + if ( p_vci_initiator.rspval.read() ) + { + bool aligned = (r_burst_offset.read() == 0); + + if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_initiator_fsm = M_READ_ERROR; + } + else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or + (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) + { + if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block + { + r_initiator_fsm = M_READ_SUCCESS; + } + else // last burst not last block + { + r_index = 0; + r_burst_count = 0; + r_block_count = r_block_count.read() + 1; + r_initiator_fsm = M_READ_BLOCK; + } + } + else // not the last burst + { + r_burst_count = r_burst_count.read() + 1; + r_initiator_fsm = M_READ_BURST; + } + } + break; + } + /////////////////// + case M_READ_SUCCESS: + case M_READ_ERROR: + { + if( !r_go ) r_initiator_fsm = M_IDLE; + break; + } + /////////////////// + case M_WRITE_BURST: // Compute the number of flits in the burst + { + uint32_t offset = r_burst_offset.read(); + + if ( offset ) // buffer not aligned + { + if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset; + else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset; + else r_burst_nflits = m_flits_per_burst; + } + else // buffer aligned + { + r_burst_nflits = m_flits_per_burst; + } + r_initiator_fsm = M_WRITE_CMD; + break; + } + ///////////////// + case M_WRITE_CMD: // This is actually a single flit VCI READ command + { + if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; + break; + } + ///////////////// + case M_WRITE_RSP: // This is actually a multi-flits VCI READ response + { + bool aligned = (r_burst_offset.read() == 0); + + if ( p_vci_initiator.rspval.read() ) + { + r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); + r_index = r_index.read() + 1; + + if ( p_vci_initiator.reop.read() ) // last flit of the burst + { + r_flit_count = 0; + r_buf_address = r_buf_address.read() + r_burst_nflits.read()<<2; + + if( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_initiator_fsm = M_WRITE_ERROR; + } + else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or + (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst + { + r_burst_count = 0; + r_block_count = r_block_count.read() + 1; + r_initiator_fsm = M_WRITE_BLOCK; + } + else // not the last burst + { + r_burst_count = r_burst_count.read() + 1; + r_initiator_fsm = M_WRITE_BURST; + } + } + else + { + r_flit_count = r_flit_count.read() + 1; + } + } + break; + } + /////////////////// + case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles { if ( r_latency_count == 0 ) @@ -180,134 +372,15 @@ r_latency_count = m_latency; ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET); - if( ::read(m_fd, m_local_buffer, m_flits_per_block*vci_param::B) < 0 ) - { - r_initiator_fsm = M_READ_ERROR; - } - else - { - r_initiator_fsm = M_READ_CMD; - } - } - else - { - r_latency_count = r_latency_count - 1; - } - break; - } - case M_READ_CMD: // This is actually a multi-flits VCI WRITE command - { - if ( p_vci_initiator.cmdack.read() ) - { - if ( r_flit_count == (m_flits_per_burst - 1) ) - { - r_initiator_fsm = M_READ_RSP; - r_flit_count = 0; + if( ::write(m_fd, r_local_buffer, m_flits_per_block*vci_param::B) < 0 ) + { + r_initiator_fsm = M_WRITE_ERROR; + } + else if ( r_block_count.read() == r_nblocks.read() ) + { + r_initiator_fsm = M_WRITE_SUCCESS; } else { - r_flit_count = r_flit_count + 1; - } - } - break; - } - case M_READ_RSP: // This is actually a single flit VCI WRITE response - { - if ( p_vci_initiator.rspval.read() ) - { - if ( (p_vci_initiator.rerror.read()&0x1) == 0 ) r_initiator_fsm = M_READ_TEST; - else r_initiator_fsm = M_READ_ERROR; - } - break; - } - case M_READ_TEST: - { - if ( r_burst_count.read() == (m_bursts_per_block - 1) ) - { - if ( r_block_count.read() == (r_nblocks.read() - 1) ) // last burst of the last block - { - r_burst_count = 0; - r_block_count = 0; - r_initiator_fsm = M_READ_SUCCESS; - } - else // last burst but not last block - { - r_burst_count = 0; - r_block_count = r_block_count.read() + 1; - r_initiator_fsm = M_READ_BLOCK; - } - } - else // not the last burst of the block - { - r_burst_count = r_burst_count.read() + 1; - r_initiator_fsm = M_READ_CMD; - } - break; - } - case M_READ_SUCCESS: - { - if( !r_go ) r_initiator_fsm = M_IDLE; - break; - } - case M_READ_ERROR: - { - if( !r_go ) r_initiator_fsm = M_IDLE; - break; - } - case M_WRITE_CMD: // This is actually a single flit VCI READ command - { - if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; - break; - } - case M_WRITE_RSP: // This is actually a multi-flits VCI READ response - { - if ( p_vci_initiator.rspval.read() ) - { - uint32_t index = (r_burst_count.read()*m_flits_per_burst) + r_flit_count.read(); - m_local_buffer[index] = (uint32_t)p_vci_initiator.rdata.read(); - if ( p_vci_initiator.reop.read() ) - { - r_flit_count = 0; - if( (p_vci_initiator.rerror.read()&0x1) == 0 ) r_initiator_fsm = M_WRITE_TEST; - else r_initiator_fsm = M_WRITE_ERROR; - } - else - { - r_flit_count = r_flit_count.read() + 1; - } - } - break; - } - case M_WRITE_TEST: - { - if ( r_burst_count.read() == (m_bursts_per_block - 1) ) // last burst of the block - { - r_burst_count = 0; - r_block_count = r_block_count.read() + 1; - r_initiator_fsm = M_WRITE_BLOCK; - } - else // not the last burst - { - r_burst_count = r_burst_count.read() + 1; - r_initiator_fsm = M_WRITE_CMD; - } - break; - } - case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles - { - if ( r_latency_count == 0 ) - { - r_latency_count = m_latency; - ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET); - if( ::write(m_fd, m_local_buffer, m_flits_per_block*vci_param::B) < 0 ) - { - r_initiator_fsm = M_WRITE_ERROR; - } - else if ( r_block_count.read() == r_nblocks.read() ) - { - r_initiator_fsm = M_WRITE_SUCCESS; - } - else - { - r_initiator_fsm = M_WRITE_CMD; + r_initiator_fsm = M_WRITE_BURST; } } @@ -318,9 +391,6 @@ break; } + ///////////////////// case M_WRITE_SUCCESS: - { - if( !r_go ) r_initiator_fsm = M_IDLE; - break; - } case M_WRITE_ERROR: { @@ -334,7 +404,4 @@ tmpl(void)::genMoore() { - sc_dt::sc_uint offset; - uint32_t index; - // p_vci_target port p_vci_target.rsrcid = (sc_dt::sc_uint)r_srcid.read(); @@ -346,12 +413,12 @@ case T_IDLE: p_vci_target.cmdack = true; - p_vci_target.rspval = false; + p_vci_target.rspval = false; break; case T_READ_STATUS: p_vci_target.cmdack = false; - p_vci_target.rspval = true; - if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; - else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; - else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; + p_vci_target.rspval = true; + if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; + else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; + else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; @@ -361,29 +428,29 @@ case T_READ_BUFFER: p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = (uint32_t)r_buf_address; + p_vci_target.rspval = true; + p_vci_target.rdata = (uint32_t)r_buf_address.read(); p_vci_target.rerror = VCI_READ_OK; break; case T_READ_COUNT: p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = (uint32_t)r_nblocks; + p_vci_target.rspval = true; + p_vci_target.rdata = (uint32_t)r_nblocks.read(); p_vci_target.rerror = VCI_READ_OK; break; case T_READ_LBA: p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = (uint32_t)r_lba; + p_vci_target.rspval = true; + p_vci_target.rdata = (uint32_t)r_lba.read(); p_vci_target.rerror = VCI_READ_OK; break; case T_READ_IRQEN: p_vci_target.cmdack = false; - p_vci_target.rspval = true; - p_vci_target.rdata = (uint32_t)r_irq_enable; + p_vci_target.rspval = true; + p_vci_target.rdata = (uint32_t)r_irq_enable.read(); p_vci_target.rerror = VCI_READ_OK; break; case T_READ_SIZE: p_vci_target.cmdack = false; - p_vci_target.rspval = true; + p_vci_target.rspval = true; p_vci_target.rdata = (uint32_t)m_device_size; p_vci_target.rerror = VCI_READ_OK; @@ -391,5 +458,5 @@ case T_READ_BLOCK: p_vci_target.cmdack = false; - p_vci_target.rspval = true; + p_vci_target.rspval = true; p_vci_target.rdata = (uint32_t)m_flits_per_block*vci_param::B; p_vci_target.rerror = VCI_READ_OK; @@ -397,5 +464,5 @@ case T_READ_ERROR: p_vci_target.cmdack = false; - p_vci_target.rspval = true; + p_vci_target.rspval = true; p_vci_target.rdata = 0; p_vci_target.rerror = VCI_READ_ERROR; @@ -403,5 +470,5 @@ case T_WRITE_ERROR: p_vci_target.cmdack = false; - p_vci_target.rspval = true; + p_vci_target.rspval = true; p_vci_target.rdata = 0; p_vci_target.rerror = VCI_WRITE_ERROR; @@ -427,28 +494,22 @@ switch (r_initiator_fsm) { case M_WRITE_CMD: // It is actually a single flit VCI read command - offset = (r_block_count.read()*m_flits_per_block + - r_burst_count.read()*m_flits_per_burst) * vci_param::B; p_vci_initiator.rspack = false; p_vci_initiator.cmdval = true; - p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read() + offset; + p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); p_vci_initiator.cmd = vci_param::CMD_READ; p_vci_initiator.wdata = 0; p_vci_initiator.be = (uint32_t)0xF; - p_vci_initiator.plen = (sc_dt::sc_uint)m_flits_per_burst*vci_param::B; + p_vci_initiator.plen = (sc_dt::sc_uint)(r_burst_nflits.read()<<2); p_vci_initiator.eop = true; break; case M_READ_CMD: // It is actually a multi-flits VCI WRITE command - offset = ( r_block_count.read()*m_flits_per_block + - r_burst_count.read()*m_flits_per_burst + - r_flit_count.read() ) * vci_param::B; - index = (r_burst_count.read()*m_flits_per_burst) + r_flit_count.read(); p_vci_initiator.rspack = false; p_vci_initiator.cmdval = true; - p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read() + offset; + p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); p_vci_initiator.cmd = vci_param::CMD_WRITE; - p_vci_initiator.wdata = (uint32_t)m_local_buffer[index]; + p_vci_initiator.wdata = (uint32_t)r_local_buffer[r_index.read()]; p_vci_initiator.be = 0xF; - p_vci_initiator.plen = (sc_dt::sc_uint)m_flits_per_burst*vci_param::B; - p_vci_initiator.eop = ( r_flit_count.read() == (m_flits_per_burst - 1) ); + p_vci_initiator.plen = (sc_dt::sc_uint)(r_burst_nflits.read()<<2); + p_vci_initiator.eop = ( r_flit_count.read() == (r_burst_nflits.read() - 1) ); break; case M_READ_RSP: @@ -456,9 +517,9 @@ p_vci_initiator.rspack = true; p_vci_initiator.cmdval = false; - break; + break; default: - p_vci_initiator.rspack = false; - p_vci_initiator.cmdval = false; - break; + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = false; + break; } @@ -472,12 +533,12 @@ ////////////////////////////////////////////////////////////////////////////// -tmpl(/**/)::VciBlockDeviceTsarV4( sc_core::sc_module_name name, - const soclib::common::MappingTable &mt, - const soclib::common::IntTab &srcid, - const soclib::common::IntTab &tgtid, - const std::string &filename, - const uint32_t block_size, - const uint32_t burst_size, - const uint32_t latency) +tmpl(/**/)::VciBlockDeviceTsarV4( sc_core::sc_module_name name, + const soclib::common::MappingTable &mt, + const soclib::common::IntTab &srcid, + const soclib::common::IntTab &tgtid, + const std::string &filename, + const uint32_t block_size, + const uint32_t burst_size, + const uint32_t latency) : caba::BaseModule(name), @@ -512,4 +573,16 @@ exit(1); } + if( (burst_size != 1 ) && + (burst_size != 2 ) && + (burst_size != 4 ) && + (burst_size != 8 ) && + (burst_size != 16) && + (burst_size != 32) && + (burst_size != 64) ) + { + std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; + std::cout << "The burst size must be 1, 2, 4, 8, 16, 32 or 64 bytes" << std::endl; + exit(1); + } if ( m_segment.size() < 32 ) { @@ -522,10 +595,4 @@ std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; std::cout << "The base address of the segment must be multiple of 32 bytes" << std::endl; - exit(1); - } - if ( block_size%burst_size != 0 ) - { - std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; - std::cout << "The block_size parameter must be a multiple of the burst_size" << std::endl; exit(1); } @@ -552,15 +619,6 @@ } - m_local_buffer = new uint32_t[m_flits_per_block]; -/* - std::cout << std::endl << "Instanciation of VciBlockDeviceTsarV4 : " << name << std::endl; - std::cout << " file_name = " << filename << std::endl; - std::cout << " burst_size = " << std::dec << m_flits_per_burst*vci_param::B << std::endl; - std::cout << " block_size = " << std::dec << m_flits_per_block*vci_param::B << std::endl; - std::cout << " latency = " << std::dec << m_latency << std::endl; - std::cout << " segment " << m_segment.name() - << " | base = 0x" << std::hex << m_segment.baseAddress() - << " | size = " << std::dec << m_segment.size() << std::endl; -*/ + r_local_buffer = new uint32_t[m_flits_per_block]; + } // end constructor @@ -569,17 +627,20 @@ { const char* initiator_str[] = { - "IDLE ", - "READ_BLOCK ", - "READ_CMD ", - "READ_RSP ", - "READ_TEST ", - "READ_SUCCESS ", - "READ_ERROR ", - "WRITE_BLOCK ", - "WRITE_CMD ", - "WRITE_RSP ", - "WRITE_TEST ", + "IDLE", + + "READ_BLOCK", + "READ_BURST", + "READ_CMD", + "READ_RSP", + "READ_TEST", + "READ_SUCCESS", + "READ_ERROR", + + "WRITE_BURST", + "WRITE_CMD", + "WRITE_RSP", + "WRITE_BLOCK", "WRITE_SUCCESS", - "WRITE_ERROR ", + "WRITE_ERROR", }; const char* target_str[] = {