Index: trunk/platforms/tsarv4_generic_mmu/top.cpp =================================================================== --- trunk/platforms/tsarv4_generic_mmu/top.cpp (revision 262) +++ trunk/platforms/tsarv4_generic_mmu/top.cpp (revision 263) @@ -7,4 +7,8 @@ ///////////////////////////////////////////////////////////////////////// // This file define a generic TSAR architecture with virtual memory. +// The physical address space is 32 bits. +// The number of clusters cannot be larger than 256. +// The number of processors per cluster cannot be larger than 8. +// // - It uses vci_local_crossbar as local interconnect // - It uses virtual_dspin as global interconnect @@ -12,6 +16,12 @@ // - It uses the vci_mem_cache_v4 // - It contains one vci_xicu and one vci_multi_dma per cluster. -// The peripherals BDEV, FBUF, MTTY, and the boot BROM -// are in the cluster containing address 0xBFC00000. +// +// All clusters are identical, but the cluster containing address +// 0xBFC00000 (called io_cluster), that contains 5 extra components: +// - the boot rom (BROM) +// - the disk controller (BDEV) +// - the multi-channel network controller (MNIC) +// - the multi-channel tty controller (MTTY) +// - the frame buffer controller (FBUF) // // It is build with one single component implementing a cluster: @@ -25,15 +35,29 @@ // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. // -// The physical address space is 32 bits. -// The number of clusters cannot be larger than 256. -// The number of processors per cluster cannot be larger than 8. +// The main hardware parameters must be defined in the hard_config.h file : +// - CLUSTER_X : number of clusters in a row (power of 2) +// - CLUSTER_Y : number of clusters in a column (power of 2) +// - CLUSTER_SIZE : size of the segment allocated to a cluster +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_DMAS_MAX : number of DMA channels per cluster (< 9) +// - NB_TTYS : number of TTY channels in I/O cluster (< 16) +// - NB_NICS : number of NIC channels in I/O cluster (< 9) +// +// Some secondary hardware parameters must be defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - BDEV_SECTOR_SIZE : block size for block drvice +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_TIMEOUT : max number of cycles before closing a container // -// The hardware parameters are : -// - xmax : number of clusters in a row (power of 2) -// - ymax : number of clusters in a column (power of 2) -// - nb_procs : number of processors per cluster (power of 2) -// - nb_dmas : number of DMA channels per cluster (< 9) -// - nb_ttys : number of TTYs in I/O cluster (< 16) -// // General policy for 32 bits physical address decoding: // All segments base addresses are multiple of 64 Kbytes @@ -75,8 +99,7 @@ #include #endif -/////////////////////////////////////////////////// // cluster index (computed from x,y coordinates) -#define cluster(x,y) (y + ymax*x) +#define cluster(x,y) (y + CLUSTER_Y*x) // flit widths for the DSPIN network @@ -96,14 +119,13 @@ #define wrplen_width 1 -/////////////////////////////////////////////////// -// Parameters default values -/////////////////////////////////////////////////// - -#define MESH_XMAX 2 -#define MESH_YMAX 2 - -#define NB_PROCS 1 -#define NB_TTYS 2 -#define NB_DMAS 1 +//////////////////////////////////////////////////////////// +// Main Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#include "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/hard_config.h" + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters values +//////////////////////i///////////////////////////////////// #define XRAM_LATENCY 0 @@ -122,7 +144,19 @@ #define BDEV_SECTOR_SIZE 512 -#define BDEV_IMAGE_NAME "hdd-img.bin" - -#define BOOT_SOFT_NAME "soft.bin" +#define BDEV_IMAGE_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/display/images.raw" + +#define NIC_RX_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/nic/rx_data.txt" +#define NIC_TX_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/nic/tx_data.txt" +#define NIC_TIMEOUT 10000 + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM & RAM +//////////////////////i///////////////////////////////////// + +#define BOOT_SOFT_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/soft.elf" + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////i///////////////////////////////////// #define MAX_FROZEN_CYCLES 10000 @@ -134,46 +168,37 @@ // Physical segments definition ///////////////////////////////////////////////////////// -// There is 3 segments replicated in all clusters: -// - seg_memc -> MEMC / BASE = 0x**000000 (12 M bytes) -// - seg_icu -> ICU / BASE = 0x**F00000 -// - seg_dma -> CDMA / BASE = 0x**F30000 -// -// There is 4 specific segments in the "IO" cluster +// There is 3 segments replicated in all clusters +// and 5 specific segments in the "IO" cluster // (containing address 0xBF000000) -// - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) -// - seg_fbuf -> FBUF / BASE = 0xBFD00000 (2 M bytes) -// - seg_bdev -> BDEV / BASE = 0xBFF10000 -// - seg_tty -> MTTY / BASE = 0x**F20000 -// -// There is one special segment corresponding to -// the processors in the coherence address space -// - seg_proc -> PROC / BASE = 0x**B0 to 0xBF -/////////////////////////////////////////////////// +///////////////////////////////////////////////////////// // specific segments in "IO" cluster : absolute physical address #define BROM_BASE 0xBFC00000 -#define BROM_SIZE 0x00100000 - -#define FBUF_BASE 0x80D00000 -#define FBUF_SIZE 0x00200000 - -#define BDEV_BASE 0x80F10000 -#define BDEV_SIZE 0x00001000 - -#define MTTY_BASE 0x80F20000 -#define MTTY_SIZE 0x00001000 - -// replicated segments : physical address is incremented by an offset +#define BROM_SIZE 0x00100000 // 1 Mbytes + +#define FBUF_BASE 0xBFD00000 +#define FBUF_SIZE 0x00200000 // 2 Mbytes + +#define BDEV_BASE 0xBFF10000 +#define BDEV_SIZE 0x00001000 // 4 Kbytes + +#define MTTY_BASE 0xBFF20000 +#define MTTY_SIZE 0x00001000 // 4 Kbytes + +#define MNIC_BASE 0xBFF80000 +#define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes + +// replicated segments : address is incremented by a cluster offset // offset = cluster(x,y) << (address_width-x_width-y_width); #define MEMC_BASE 0x00000000 -#define MEMC_SIZE 0x00C00000 +#define MEMC_SIZE 0x00C00000 // 12 Mbytes #define XICU_BASE 0x00F00000 -#define XICU_SIZE 0x00001000 +#define XICU_SIZE 0x00001000 // 4 Kbytes #define CDMA_BASE 0x00F30000 -#define CDMA_SIZE 0x00008000 +#define CDMA_SIZE 0x00001000 * NB_DMAS_MAX // 4 Kbytes per channel //////////////////////////////////////////////////////////////////// @@ -189,4 +214,5 @@ #define BROM_TGTID 5 #define BDEV_TGTID 6 +#define MNIC_TGTID 7 ///////////////////////////////// @@ -198,29 +224,16 @@ - char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code - size_t ncycles = 1000000000; // simulated cycles - size_t xmax = MESH_XMAX; // number of clusters in a row - size_t ymax = MESH_YMAX; // number of clusters in a column - size_t nb_procs = NB_PROCS; // number of processors per cluster - size_t nb_dmas = NB_DMAS; // number of RDMA channels per cluster - size_t nb_ttys = NB_TTYS; // number of TTY terminals in I/O cluster - size_t xfb = FBUF_X_SIZE; // frameBuffer column number - size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number - size_t memc_ways = MEMC_WAYS; - size_t memc_sets = MEMC_SETS; - size_t l1_d_ways = L1_DWAYS; - size_t l1_d_sets = L1_DSETS; - size_t l1_i_ways = L1_IWAYS; - size_t l1_i_sets = L1_ISETS; - char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image - size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) - size_t xram_latency = XRAM_LATENCY; // external RAM latency - ssize_t threads_nr = 1; // simulator's threads number - bool debug_ok = false; // trace activated - size_t debug_period = 1; // trace period - size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) - size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced - uint32_t debug_from = 0; // trace start cycle - uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code + size_t ncycles = 1000000000; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) + size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor ////////////// command line arguments ////////////////////// @@ -233,44 +246,4 @@ ncycles = atoi(argv[n+1]); } - else if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1 offset = cluster(x,y) << (address_width-x_width-y_width); @@ -462,9 +433,9 @@ std::ostringstream sh; sh << "c_seg_memc_" << x << "_" << y; - maptabc.add(Segment(sh.str(), (nb_procs << (address_width - srcid_width)) + offset, - 0x10, IntTab(cluster(x,y), nb_procs), false)); + maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset, + 0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false)); // update & invalidate requests must be routed to the proper processor - for ( size_t p = 0 ; p < nb_procs ; p++) + for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++) { std::ostringstream sp; @@ -480,7 +451,7 @@ MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); - for (size_t x = 0; x < xmax; x++) + for (size_t x = 0; x < CLUSTER_X; x++) { - for (size_t y = 0; y < ymax ; y++) + for (size_t y = 0; y < CLUSTER_Y ; y++) { sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); @@ -502,41 +473,41 @@ // Horizontal inter-clusters DSPIN signals DspinSignals*** signal_dspin_h_cmd_inc = - alloc_elems >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2); + alloc_elems >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2); DspinSignals*** signal_dspin_h_cmd_dec = - alloc_elems >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2); + alloc_elems >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2); DspinSignals*** signal_dspin_h_rsp_inc = - alloc_elems >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2); + alloc_elems >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2); DspinSignals*** signal_dspin_h_rsp_dec = - alloc_elems >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2); + alloc_elems >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2); // Vertical inter-clusters DSPIN signals DspinSignals*** signal_dspin_v_cmd_inc = - alloc_elems >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2); + alloc_elems >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2); DspinSignals*** signal_dspin_v_cmd_dec = - alloc_elems >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2); + alloc_elems >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2); DspinSignals*** signal_dspin_v_rsp_inc = - alloc_elems >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2); + alloc_elems >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2); DspinSignals*** signal_dspin_v_rsp_dec = - alloc_elems >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2); + alloc_elems >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2); // Mesh boundaries DSPIN signals DspinSignals**** signal_dspin_false_cmd_in = - alloc_elems >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4); + alloc_elems >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4); DspinSignals**** signal_dspin_false_cmd_out = - alloc_elems >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4); + alloc_elems >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4); DspinSignals**** signal_dspin_false_rsp_in = - alloc_elems >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4); + alloc_elems >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4); DspinSignals**** signal_dspin_false_rsp_out = - alloc_elems >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4); + alloc_elems >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4); //////////////////////////// - // Components + // Loader //////////////////////////// #if USE_ALMOS soclib::common::Loader loader(almos_bootloader_pathname, - almos_archinfo_pathname, - almos_kernel_pathname); + almos_archinfo_pathname, + almos_kernel_pathname); #else soclib::common::Loader loader(soft_name); @@ -546,119 +517,79 @@ proc_iss::set_loader(loader); - TsarV4ClusterMmu* clusters[xmax][ymax]; + //////////////////////////// + // Clusters construction + //////////////////////////// + + TsarV4ClusterMmu* clusters[CLUSTER_X][CLUSTER_Y]; #if USE_OPENMP - #pragma omp parallel - { + { #pragma omp for - for(size_t i = 0; i < (xmax * ymax); i++) - { - size_t x = i / ymax; - size_t y = i % ymax; +#endif + for(size_t i = 0; i < (CLUSTER_X * CLUSTER_Y); i++) + { + size_t x = i / CLUSTER_Y; + size_t y = i % CLUSTER_Y; + +#if USE_OPENMP #pragma omp critical - - std::cout << "building cluster_" << x << "_" << y << std::endl; - - std::ostringstream sc; - sc << "cluster_" << x << "_" << y; - clusters[x][y] = new TsarV4ClusterMmu - (sc.str().c_str(), - nb_procs, - nb_ttys, - nb_dmas, - x, - y, - cluster(x,y), - maptabd, - maptabc, - maptabx, - x_width, - y_width, - MEMC_TGTID, - XICU_TGTID, - FBUF_TGTID, - MTTY_TGTID, - BROM_TGTID, - BDEV_TGTID, - CDMA_TGTID, - memc_ways, - memc_sets, - l1_i_ways, - l1_i_sets, - l1_d_ways, - l1_d_sets, - xram_latency, - (cluster(x,y) == cluster_io_id), - xfb, - yfb, - disk_name, - blk_size, - loader, - frozen_cycles, - debug_from, - debug_ok and (cluster(x,y) == debug_memc_id), - debug_ok and (cluster(x,y) == debug_proc_id) ); - - std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; - - } - } - -#else // NO OPENMP - - for (size_t x = 0; x < xmax; x++) - { - for (size_t y = 0; y < ymax; y++) - { - - std::cout << "building cluster_" << x << "_" << y << std::endl; - - std::ostringstream sc; - sc << "cluster_" << x << "_" << y; - clusters[x][y] = new TsarV4ClusterMmu - (sc.str().c_str(), - nb_procs, - nb_ttys, - nb_dmas, - x, - y, - cluster(x,y), - maptabd, - maptabc, - maptabx, - x_width, - y_width, - MEMC_TGTID, - XICU_TGTID, - FBUF_TGTID, - MTTY_TGTID, - BROM_TGTID, - BDEV_TGTID, - CDMA_TGTID, - memc_ways, - memc_sets, - l1_i_ways, - l1_i_sets, - l1_d_ways, - l1_d_sets, - xram_latency, - (cluster(x,y) == cluster_io_id), - xfb, - yfb, - disk_name, - blk_size, - loader, - frozen_cycles, - debug_from, - debug_ok and ( cluster(x,y) == debug_memc_id ), - debug_ok and ( cluster(x,y) == debug_proc_id ) ); - - std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; - - } - } - -#endif // USE_OPENMP + { +#endif + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarV4ClusterMmu + ( + sc.str().c_str(), + NB_PROCS_MAX, + NB_TTYS, + NB_DMAS_MAX, + x, + y, + cluster(x,y), + maptabd, + maptabc, + maptabx, + x_width, + y_width, + MEMC_TGTID, + XICU_TGTID, + CDMA_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + MNIC_TGTID, + BDEV_TGTID, + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + XRAM_LATENCY, + (cluster(x,y) == cluster_io_id), + FBUF_X_SIZE, + FBUF_Y_SIZE, + disk_name, + BDEV_SECTOR_SIZE, + NB_NICS, + nic_rx_name, + nic_tx_name, + NIC_TIMEOUT, + loader, + frozen_cycles, + debug_from, + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id) + ); + + std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif /////////////////////////////////////////////////////////////// @@ -667,6 +598,6 @@ // Clock & RESET - for (size_t x = 0; x < (xmax); x++){ - for (size_t y = 0; y < ymax; y++){ + for (size_t x = 0; x < (CLUSTER_X); x++){ + for (size_t y = 0; y < CLUSTER_Y; y++){ clusters[x][y]->p_clk (signal_clk); clusters[x][y]->p_resetn (signal_resetn); @@ -675,7 +606,7 @@ // Inter Clusters horizontal connections - if (xmax > 1){ - for (size_t x = 0; x < (xmax-1); x++){ - for (size_t y = 0; y < ymax; y++){ + if (CLUSTER_X > 1){ + for (size_t x = 0; x < (CLUSTER_X-1); x++){ + for (size_t y = 0; y < CLUSTER_Y; y++){ for (size_t k = 0; k < 2; k++){ clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); @@ -691,10 +622,10 @@ } } - std::cout << "Horizontal connections established" << std::endl; + std::cout << std::endl << "Horizontal connections established" << std::endl; // Inter Clusters vertical connections - if (ymax > 1) { - for (size_t y = 0; y < (ymax-1); y++){ - for (size_t x = 0; x < xmax; x++){ + if (CLUSTER_Y > 1) { + for (size_t y = 0; y < (CLUSTER_Y-1); y++){ + for (size_t x = 0; x < CLUSTER_X; x++){ for (size_t k = 0; k < 2; k++){ clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); @@ -713,5 +644,5 @@ // East & West boundary cluster connections - for (size_t y = 0; y < ymax; y++) + for (size_t y = 0; y < CLUSTER_Y; y++) { for (size_t k = 0; k < 2; k++) @@ -722,13 +653,13 @@ clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); - clusters[xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]); - clusters[xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]); - clusters[xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]); - clusters[xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]); } } // North & South boundary clusters connections - for (size_t x = 0; x < xmax; x++) + for (size_t x = 0; x < CLUSTER_X; x++) { for (size_t k = 0; k < 2; k++) @@ -739,8 +670,8 @@ clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); - clusters[x][ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]); - clusters[x][ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]); - clusters[x][ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]); - clusters[x][ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]); } } @@ -755,6 +686,6 @@ // network boundaries signals - for (size_t x = 0; x < xmax ; x++){ - for (size_t y = 0; y < ymax ; y++){ + for (size_t x = 0; x < CLUSTER_X ; x++){ + for (size_t y = 0; y < CLUSTER_Y ; y++){ for (size_t k = 0; k < 2; k++){ for (size_t a = 0; a < 4; a++){ @@ -785,8 +716,8 @@ // trace proc[debug_proc_id] - if ( debug_proc_id < (xmax * ymax * nb_procs) ) - { - size_t proc_x = debug_proc_id / ymax; - size_t proc_y = debug_proc_id % ymax; + if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) + { + size_t proc_x = debug_proc_id / CLUSTER_Y; + size_t proc_y = debug_proc_id % CLUSTER_Y; clusters[proc_x][proc_y]->proc[0]->print_trace(); @@ -798,8 +729,8 @@ // trace memc[debug_memc_id] - if ( debug_memc_id < (xmax * ymax) ) - { - size_t memc_x = debug_memc_id / ymax; - size_t memc_y = debug_memc_id % ymax; + if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) + { + size_t memc_x = debug_memc_id / CLUSTER_Y; + size_t memc_y = debug_memc_id % CLUSTER_Y; clusters[memc_x][memc_y]->memc->print_trace(); @@ -810,24 +741,25 @@ } - // clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0"); - // clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1"); - // clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0"); - // clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1"); - - // if ( clusters[1][1]->signal_irq_mdma[0].read() ) - // std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; - // if ( clusters[1][1]->signal_proc_it[0].read() ) - // std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; - - // trace ioc component - size_t io_x = cluster_io_id / ymax; - size_t io_y = cluster_io_id % ymax; -// clusters[io_x][io_y]->bdev->print_trace(); -// clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); -// clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); - - clusters[1][1]->mdma->print_trace(); - clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("mdma_1_1_tgt_d "); - clusters[1][1]->signal_vci_ini_d_mdma.print_trace("mdma_1_1_ini_d "); +// clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0"); +// clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1"); +// clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0"); +// clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1"); + +// if ( clusters[1][1]->signal_irq_mdma[0].read() ) +// std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; +// if ( clusters[1][1]->signal_proc_it[0].read() ) +// std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; + +// trace ioc component +// size_t io_x = cluster_io_id / CLUSTER_Y; +// size_t io_y = cluster_io_id % CLUSTER_Y; +// clusters[io_x][io_y]->bdev->print_trace(); +// clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); +// clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); + +// clusters[1][1]->mdma->print_trace(); +// clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("mdma_1_1_tgt_d "); +// clusters[1][1]->signal_vci_ini_d_mdma.print_trace("mdma_1_1_ini_d "); + } Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd =================================================================== --- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd (revision 262) +++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd (revision 263) @@ -35,4 +35,5 @@ Uses('caba:vci_multi_tty'), Uses('caba:vci_framebuffer'), + Uses('caba:vci_multi_nic'), Uses('caba:vci_block_device_tsar_v4'), Uses('caba:vci_multi_dma'), Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h =================================================================== --- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h (revision 262) +++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h (revision 263) @@ -27,4 +27,5 @@ #include "vci_vdspin_initiator_wrapper.h" #include "vci_multi_tty.h" +#include "vci_multi_nic.h" #include "vci_block_device_tsar_v4.h" #include "vci_framebuffer.h" @@ -58,4 +59,6 @@ sc_signal signal_irq_mdma[8]; sc_signal signal_irq_mtty[23]; + sc_signal signal_irq_mnic_rx[8]; // unused + sc_signal signal_irq_mnic_tx[8]; // unused sc_signal signal_irq_bdev; @@ -88,4 +91,5 @@ VciSignals signal_vci_tgt_d_brom; VciSignals signal_vci_tgt_d_fbuf; + VciSignals signal_vci_tgt_d_mnic; // Coherence VCi signals @@ -114,4 +118,5 @@ VciMultiTty* mtty; VciFrameBuffer* fbuf; + VciMultiNic* mnic; VciBlockDeviceTsarV4* bdev; VciMultiDma* mdma; @@ -132,9 +137,10 @@ size_t tgtid_memc, size_t tgtid_xicu, + size_t tgtid_mdma, size_t tgtid_fbuf, size_t tgtid_mtty, size_t tgtid_brom, + size_t tgtid_mnic, size_t tgtid_bdev, - size_t tgtid_mdma, size_t memc_ways, size_t memc_sets, @@ -149,4 +155,8 @@ char* disk_name, // virtual disk name for BDEV size_t block_size, // block size for BDEV + size_t nic_channels, // number of channels + char* nic_rx_name, // file name rx packets + char* nic_tx_name, // file name tx packets + uint32_t nic_timeout, // number of cycles const Loader &loader, // loader for BROM uint32_t frozen_cycles, // max frozen cycles Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp =================================================================== --- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (revision 262) +++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (revision 263) @@ -48,9 +48,10 @@ size_t tgtid_memc, size_t tgtid_xicu, + size_t tgtid_mdma, size_t tgtid_fbuf, size_t tgtid_mtty, size_t tgtid_brom, + size_t tgtid_mnic, size_t tgtid_bdev, - size_t tgtid_mdma, size_t memc_ways, size_t memc_sets, @@ -65,4 +66,8 @@ char* disk_name, size_t block_size, + size_t nic_channels, + char* nic_rx_name, + char* nic_tx_name, + uint32_t nic_timeout, const Loader &loader, uint32_t frozen_cycles, @@ -182,5 +187,5 @@ { nb_direct_initiators = nb_procs + 2; - nb_direct_targets = 7; + nb_direct_targets = 8; } std::ostringstream sd; @@ -208,5 +213,4 @@ std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; - // direct initiator wrapper std::ostringstream wid; wid << "iniwrapperd_" << x_id << "_" << y_id; @@ -216,5 +220,4 @@ 4); // rsp fifo depth - // direct target wrapper std::ostringstream wtd; wtd << "tgtwrapperd_" << x_id << "_" << y_id; @@ -224,5 +227,4 @@ 4); // rsp fifo depth - // coherence initiator wrapper std::ostringstream wic; wic << "iniwrapperc_" << x_id << "_" << y_id; @@ -232,5 +234,4 @@ 4); // rsp fifo depth - // coherence target wrapper std::ostringstream wtc; wtc << "tgtwrapperc_" << x_id << "_" << y_id; @@ -252,5 +253,4 @@ std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; - // RSP router std::ostringstream srsp; srsp << "rsprouter_" << x_id << "_" << y_id; @@ -291,4 +291,15 @@ 64); // burst size + std::cout << " - building mnic" << std::endl; + + mnic = new VciMultiNic( + "mnic", + IntTab(cluster_id, tgtid_mnic), + mtd, + nic_channels, + nic_rx_name, + nic_tx_name, + nic_timeout); + std::cout << " - building mtty" << std::endl; @@ -391,4 +402,5 @@ xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); + xbard->p_to_target[tgtid_mnic] (signal_vci_tgt_d_mnic); xbard->p_to_initiator[nb_procs+1] (signal_vci_ini_d_bdev); @@ -471,5 +483,5 @@ xram->p_clk (this->p_clk); xram->p_resetn (this->p_resetn); - xram->p_vci (signal_vci_xram); + xram->p_vci (signal_vci_xram); std::cout << " - XRAM connected" << std::endl; @@ -492,33 +504,45 @@ { // BDEV - bdev->p_clk (this->p_clk); - bdev->p_resetn (this->p_resetn); - bdev->p_irq (signal_irq_bdev); - bdev->p_vci_target (signal_vci_tgt_d_bdev); - bdev->p_vci_initiator (signal_vci_ini_d_bdev); + bdev->p_clk (this->p_clk); + bdev->p_resetn (this->p_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_d_bdev); + bdev->p_vci_initiator (signal_vci_ini_d_bdev); std::cout << " - BDEV connected" << std::endl; // FBUF - fbuf->p_clk (this->p_clk); - fbuf->p_resetn (this->p_resetn); - fbuf->p_vci (signal_vci_tgt_d_fbuf); + fbuf->p_clk (this->p_clk); + fbuf->p_resetn (this->p_resetn); + fbuf->p_vci (signal_vci_tgt_d_fbuf); std::cout << " - FBUF connected" << std::endl; + // MNIC + mnic->p_clk (this->p_clk); + mnic->p_resetn (this->p_resetn); + mnic->p_vci (signal_vci_tgt_d_mnic); + for ( size_t i=0 ; ip_rx_irq[i] (signal_irq_mnic_rx[i]); + mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + std::cout << " - MNIC connected" << std::endl; + // BROM - brom->p_clk (this->p_clk); - brom->p_resetn (this->p_resetn); - brom->p_vci (signal_vci_tgt_d_brom); + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_vci_tgt_d_brom); std::cout << " - BROM connected" << std::endl; // MTTY - mtty->p_clk (this->p_clk); - mtty->p_resetn (this->p_resetn); - mtty->p_vci (signal_vci_tgt_d_mtty); + mtty->p_clk (this->p_clk); + mtty->p_resetn (this->p_resetn); + mtty->p_vci (signal_vci_tgt_d_mtty); for ( size_t i=0 ; ip_irq[i] (signal_irq_mtty[i]); + mtty->p_irq[i] (signal_irq_mtty[i]); }