Index: trunk/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd (revision 253) +++ trunk/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd (revision 273) @@ -6,42 +6,54 @@ Module('caba:vci_mem_cache_v4', - classname = 'soclib::caba::VciMemCacheV4', - tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),], - header_files = ['../source/include/vci_mem_cache_v4.h', - '../source/include/xram_transaction_v4.h', - '../source/include/mem_cache_directory_v4.h', - '../source/include/update_tab_v4.h',], - implementation_files = ['../source/src/vci_mem_cache_v4.cpp',], - uses = [Uses('caba:base_module'), - Uses('common:loader'), - Uses('common:mapping_table'), - Uses('caba:generic_fifo'), - ], - ports = [Port('caba:vci_target', 'p_vci_tgt'), - Port('caba:vci_target','p_vci_tgt_cleanup'), - Port('caba:vci_initiator','p_vci_ini'), - Port('caba:vci_initiator','p_vci_ixr'), - Port('caba:bit_in', 'p_resetn', auto = 'resetn'), - Port('caba:clock_in', 'p_clk', auto = 'clock'),], - instance_parameters = [ - parameter.Module('mtp', 'common:mapping_table'), - parameter.Module('mtc', 'common:mapping_table'), - parameter.Module('mtx', 'common:mapping_table'), - parameter.IntTab('vci_ixr_index'), - parameter.IntTab('vci_ini_index'), - parameter.IntTab('vci_tgt_index'), - parameter.IntTab('vci_tgt_index_cleanup'), - parameter.Int('nways'), - parameter.Int('nsets'), - parameter.Int('nwords'), - parameter.Int('heap_size'), - ], - extensions = [ - 'dsx:get_ident=' - 'vci_ini_index:p_vci_ini:mtc,' - 'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,' - 'vci_tgt_index:p_vci_tgt:mtp,' - 'vci_ixr_index:p_vci_ixr:mtx', - 'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup', - ], + classname = 'soclib::caba::VciMemCacheV4', + + tmpl_parameters = [ parameter.Module('vci_param', default = 'caba:vci_param') ], + + header_files = [ + '../source/include/vci_mem_cache_v4.h', + '../source/include/xram_transaction_v4.h', + '../source/include/mem_cache_directory_v4.h', + '../source/include/update_tab_v4.h' + ], + + implementation_files = [ '../source/src/vci_mem_cache_v4.cpp' ], + + uses = [ + Uses('caba:base_module'), + Uses('common:loader'), + Uses('common:mapping_table'), + Uses('caba:generic_fifo'), + ], + + ports = [ + Port( 'caba:vci_target' , 'p_vci_tgt' ), + Port( 'caba:vci_target' , 'p_vci_tgt_cleanup' ), + Port( 'caba:vci_initiator', 'p_vci_ini' ), + Port( 'caba:vci_initiator', 'p_vci_ixr' ), + Port( 'caba:bit_in' , 'p_resetn' , auto = 'resetn' ), + Port( 'caba:clock_in' , 'p_clk' , auto = 'clock' ), + ], + + instance_parameters = [ + parameter.Module( 'mtp', 'common:mapping_table' ), + parameter.Module( 'mtc', 'common:mapping_table' ), + parameter.Module( 'mtx', 'common:mapping_table' ), + parameter.IntTab( 'vci_ixr_index' ), + parameter.IntTab( 'vci_ini_index' ), + parameter.IntTab( 'vci_tgt_index' ), + parameter.IntTab( 'vci_tgt_index_cleanup '), + parameter.Int ( 'nways' ), + parameter.Int ( 'nsets' ), + parameter.Int ( 'nwords' ), + parameter.Int ( 'heap_size' ), + ], + + extensions = [ + 'dsx:get_ident=' + 'vci_ini_index:p_vci_ini:mtc,' + 'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,' + 'vci_tgt_index:p_vci_tgt:mtp,' + 'vci_ixr_index:p_vci_ixr:mtx', + 'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup', + ], ) Index: trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 253) +++ trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 273) @@ -26,6 +26,5 @@ * * Maintainers: alain eric.guthmuller@polytechnique.edu - */ -/* + * cesar.fuguet-tortolero@lip6.fr * * Modifications done by Christophe Choichillon on the 7/04/2009: @@ -33,5 +32,5 @@ * - Adding a new VCI target port for the CLEANUP network * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP - * + * * Modifications to do : * - Adding new variables used by the CLEANUP FSM @@ -58,6 +57,6 @@ #include "update_tab_v4.h" -#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab -#define UPDATE_TAB_LINES 4 // Number of lines in the update tab +#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab +#define UPDATE_TAB_LINES 4 // Number of lines in the update tab namespace soclib { namespace caba { @@ -81,5 +80,5 @@ TGT_CMD_READ, TGT_CMD_WRITE, - TGT_CMD_ATOMIC, + TGT_CMD_ATOMIC }; @@ -97,5 +96,5 @@ TGT_RSP_XRAM, TGT_RSP_INIT, - TGT_RSP_CLEANUP, + TGT_RSP_CLEANUP }; @@ -115,5 +114,5 @@ INIT_CMD_SC_UPDT_INDEX, INIT_CMD_SC_UPDT_DATA, - INIT_CMD_SC_UPDT_DATA_HIGH, + INIT_CMD_SC_UPDT_DATA_HIGH }; @@ -123,5 +122,5 @@ INIT_RSP_UPT_LOCK, INIT_RSP_UPT_CLEAR, - INIT_RSP_END, + INIT_RSP_END }; @@ -129,6 +128,8 @@ enum read_fsm_state_e{ READ_IDLE, + READ_DIR_REQ, READ_DIR_LOCK, READ_DIR_HIT, + READ_HEAP_REQ, READ_HEAP_LOCK, READ_HEAP_WRITE, @@ -138,5 +139,5 @@ READ_TRT_LOCK, READ_TRT_SET, - READ_TRT_REQ, + READ_TRT_REQ }; @@ -145,4 +146,5 @@ WRITE_IDLE, WRITE_NEXT, + WRITE_DIR_REQ, WRITE_DIR_LOCK, WRITE_DIR_READ, @@ -163,5 +165,5 @@ WRITE_BC_CC_SEND, WRITE_BC_XRAM_REQ, - WRITE_WAIT, + WRITE_WAIT }; @@ -171,5 +173,5 @@ IXR_RSP_ACK, IXR_RSP_TRT_ERASE, - IXR_RSP_TRT_READ, + IXR_RSP_TRT_READ }; @@ -186,8 +188,9 @@ XRAM_RSP_INVAL, XRAM_RSP_WRITE_DIRTY, + XRAM_RSP_HEAP_REQ, XRAM_RSP_HEAP_ERASE, XRAM_RSP_HEAP_LAST, XRAM_RSP_ERROR_ERASE, - XRAM_RSP_ERROR_RSP, + XRAM_RSP_ERROR_RSP }; @@ -201,5 +204,5 @@ IXR_CMD_WRITE_NLINE, IXR_CMD_SC_NLINE, - IXR_CMD_XRAM_DATA, + IXR_CMD_XRAM_DATA }; @@ -207,4 +210,5 @@ enum sc_fsm_state_e{ SC_IDLE, + SC_DIR_REQ, SC_DIR_LOCK, SC_DIR_HIT_READ, @@ -224,5 +228,5 @@ SC_MISS_TRT_SET, SC_MISS_XRAM_REQ, - SC_WAIT, + SC_WAIT }; @@ -230,6 +234,8 @@ enum cleanup_fsm_state_e{ CLEANUP_IDLE, + CLEANUP_DIR_REQ, CLEANUP_DIR_LOCK, CLEANUP_DIR_WRITE, + CLEANUP_HEAP_REQ, CLEANUP_HEAP_LOCK, CLEANUP_HEAP_SEARCH, @@ -239,14 +245,15 @@ CLEANUP_UPT_WRITE, CLEANUP_WRITE_RSP, - CLEANUP_RSP, + CLEANUP_RSP }; /* States of the ALLOC_DIR fsm */ enum alloc_dir_fsm_state_e{ + ALLOC_DIR_RESET, ALLOC_DIR_READ, ALLOC_DIR_WRITE, ALLOC_DIR_SC, ALLOC_DIR_CLEANUP, - ALLOC_DIR_XRAM_RSP, + ALLOC_DIR_XRAM_RSP }; @@ -257,5 +264,5 @@ ALLOC_TRT_SC, ALLOC_TRT_XRAM_RSP, - ALLOC_TRT_IXR_RSP, + ALLOC_TRT_IXR_RSP }; @@ -266,14 +273,15 @@ ALLOC_UPT_INIT_RSP, ALLOC_UPT_CLEANUP, - ALLOC_UPT_SC, + ALLOC_UPT_SC }; /* States of the ALLOC_HEAP fsm */ enum alloc_heap_fsm_state_e{ + ALLOC_HEAP_RESET, ALLOC_HEAP_READ, ALLOC_HEAP_WRITE, ALLOC_HEAP_SC, ALLOC_HEAP_CLEANUP, - ALLOC_HEAP_XRAM_RSP, + ALLOC_HEAP_XRAM_RSP }; @@ -301,21 +309,21 @@ // instrumentation counters - uint32_t m_cpt_cycles; // Counter of cycles - uint32_t m_cpt_read; // Number of READ transactions - uint32_t m_cpt_read_miss; // Number of MISS READ - uint32_t m_cpt_write; // Number of WRITE transactions - uint32_t m_cpt_write_miss; // Number of MISS WRITE - uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions - uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions - uint32_t m_cpt_update; // Number of UPDATE transactions - uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt - uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt - uint32_t m_cpt_update_mult; // Number of targets for UPDATE - uint32_t m_cpt_inval; // Number of INVAL transactions - uint32_t m_cpt_inval_mult; // Number of targets for INVAL - uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL - uint32_t m_cpt_cleanup; // Number of CLEANUP transactions - uint32_t m_cpt_ll; // Number of LL transactions - uint32_t m_cpt_sc; // Number of SC transactions + uint32_t m_cpt_cycles; // Counter of cycles + uint32_t m_cpt_read; // Number of READ transactions + uint32_t m_cpt_read_miss; // Number of MISS READ + uint32_t m_cpt_write; // Number of WRITE transactions + uint32_t m_cpt_write_miss; // Number of MISS WRITE + uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions + uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions + uint32_t m_cpt_update; // Number of UPDATE transactions + uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt + uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt + uint32_t m_cpt_update_mult; // Number of targets for UPDATE + uint32_t m_cpt_inval; // Number of INVAL transactions + uint32_t m_cpt_inval_mult; // Number of targets for INVAL + uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL + uint32_t m_cpt_cleanup; // Number of CLEANUP transactions + uint32_t m_cpt_ll; // Number of LL transactions + uint32_t m_cpt_sc; // Number of SC transactions size_t m_prev_count; @@ -326,13 +334,13 @@ public: - sc_in p_clk; - sc_in p_resetn; - soclib::caba::VciTarget p_vci_tgt; - soclib::caba::VciTarget p_vci_tgt_cleanup; - soclib::caba::VciInitiator p_vci_ini; - soclib::caba::VciInitiator p_vci_ixr; + sc_in p_clk; + sc_in p_resetn; + soclib::caba::VciTarget p_vci_tgt; + soclib::caba::VciTarget p_vci_tgt_cleanup; + soclib::caba::VciInitiator p_vci_ini; + soclib::caba::VciInitiator p_vci_ixr; VciMemCacheV4( - sc_module_name name, // Instance Name + sc_module_name name, // Instance Name const soclib::common::MappingTable &mtp, // Mapping table for primary requets const soclib::common::MappingTable &mtc, // Mapping table for coherence requets @@ -342,5 +350,5 @@ const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup - size_t nways, // Number of ways per set + size_t nways, // Number of ways per set size_t nsets, // Number of sets size_t nwords, // Number of words per line @@ -348,5 +356,5 @@ size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT - size_t debug_start_cycle=0, + size_t debug_start_cycle=0, bool debug_ok=false); @@ -366,37 +374,38 @@ // Component attributes - const size_t m_initiators; // Number of initiators - const size_t m_heap_size; // Size of the heap - const size_t m_ways; // Number of ways in a set - const size_t m_sets; // Number of cache sets - const size_t m_words; // Number of words in a line - const size_t m_srcid_ixr; // Srcid for requests to XRAM - const size_t m_srcid_ini; // Srcid for requests to processors - std::list m_seglist; // memory cached into the cache - std::list m_cseglist; // coherence segment for the cache - vci_addr_t *m_coherence_table; // address(srcid) - uint32_t m_transaction_tab_lines; - TransactionTab m_transaction_tab; // xram transaction table - uint32_t m_update_tab_lines; - UpdateTab m_update_tab; // pending update & invalidate - CacheDirectory m_cache_directory; // data cache directory - HeapDirectory m_heap; // heap for copies - - data_t ***m_cache_data; // data array[set][way][word] + std::list m_seglist; // memory cached into the cache + std::list m_cseglist; // coherence segment for the cache + + const size_t m_initiators; // Number of initiators + const size_t m_heap_size; // Size of the heap + const size_t m_ways; // Number of ways in a set + const size_t m_sets; // Number of cache sets + const size_t m_words; // Number of words in a line + const size_t m_srcid_ixr; // Srcid for requests to XRAM + const size_t m_srcid_ini; // Srcid for requests to processors + + uint32_t m_transaction_tab_lines; + TransactionTab m_transaction_tab; // xram transaction table + uint32_t m_update_tab_lines; + UpdateTab m_update_tab; // pending update & invalidate + CacheDirectory m_cache_directory; // data cache directory + HeapDirectory m_heap; // heap for copies + + data_t *** m_cache_data; // data array[set][way][word] // adress masks - const soclib::common::AddressMaskingTable m_x; - const soclib::common::AddressMaskingTable m_y; - const soclib::common::AddressMaskingTable m_z; - const soclib::common::AddressMaskingTable m_nline; + const soclib::common::AddressMaskingTable m_x; + const soclib::common::AddressMaskingTable m_y; + const soclib::common::AddressMaskingTable m_z; + const soclib::common::AddressMaskingTable m_nline; // broadcast address - vci_addr_t m_broadcast_address; + vci_addr_t m_broadcast_address; ////////////////////////////////////////////////// // Others registers ////////////////////////////////////////////////// - sc_signal r_copies_limit; // Limit of the number of copies for one line - sc_signal xxx_count; + sc_signal r_copies_limit; // Limit of the number of copies for one line + sc_signal xxx_count; ////////////////////////////////////////////////// @@ -411,5 +420,5 @@ GenericFifo m_cmd_read_pktid_fifo; - // Fifo between TGT_CMD fsm and WRITE fsm + // Fifo between TGT_CMD fsm and WRITE fsm GenericFifo m_cmd_write_addr_fifo; GenericFifo m_cmd_write_eop_fifo; @@ -418,5 +427,5 @@ GenericFifo m_cmd_write_pktid_fifo; GenericFifo m_cmd_write_data_fifo; - GenericFifo m_cmd_write_be_fifo; + GenericFifo m_cmd_write_be_fifo; // Fifo between TGT_CMD fsm and SC fsm @@ -434,38 +443,37 @@ soclib::common::Segment **m_seg; soclib::common::Segment **m_cseg; - /////////////////////////////////////////////////////// // Registers controlled by the READ fsm /////////////////////////////////////////////////////// - sc_signal r_read_fsm; // FSM state - sc_signal r_read_copy; // Srcid of the first copy - sc_signal r_read_copy_cache; // Srcid of the first copy - sc_signal r_read_copy_inst; // Type of the first copy - sc_signal r_read_tag; // cache line tag (in directory) - sc_signal r_read_is_cnt; // is_cnt bit (in directory) - sc_signal r_read_lock; // lock bit (in directory) - sc_signal r_read_dirty; // dirty bit (in directory) - sc_signal r_read_count; // number of copies - sc_signal r_read_ptr; // pointer to the heap - sc_signal *r_read_data; // data (one cache line) - sc_signal r_read_way; // associative way (in cache) - sc_signal r_read_trt_index; // Transaction Table index - sc_signal r_read_next_ptr; // Next entry to point to - sc_signal r_read_last_free; // Last free entry - - // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) - sc_signal r_read_to_ixr_cmd_req; // valid request - sc_signal r_read_to_ixr_cmd_nline; // cache line index - sc_signal r_read_to_ixr_cmd_trdid; // index in Transaction Table + sc_signal r_read_fsm; // FSM state + sc_signal r_read_copy; // Srcid of the first copy + sc_signal r_read_copy_cache; // Srcid of the first copy + sc_signal r_read_copy_inst; // Type of the first copy + sc_signal r_read_tag; // cache line tag (in directory) + sc_signal r_read_is_cnt; // is_cnt bit (in directory) + sc_signal r_read_lock; // lock bit (in directory) + sc_signal r_read_dirty; // dirty bit (in directory) + sc_signal r_read_count; // number of copies + sc_signal r_read_ptr; // pointer to the heap + sc_signal * r_read_data; // data (one cache line) + sc_signal r_read_way; // associative way (in cache) + sc_signal r_read_trt_index; // Transaction Table index + sc_signal r_read_next_ptr; // Next entry to point to + sc_signal r_read_last_free; // Last free entry + + // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) + sc_signal r_read_to_ixr_cmd_req; // valid request + sc_signal r_read_to_ixr_cmd_nline; // cache line index + sc_signal r_read_to_ixr_cmd_trdid; // index in Transaction Table // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) - sc_signal r_read_to_tgt_rsp_req; // valid request - sc_signal r_read_to_tgt_rsp_srcid; // Transaction srcid - sc_signal r_read_to_tgt_rsp_trdid; // Transaction trdid - sc_signal r_read_to_tgt_rsp_pktid; // Transaction pktid - sc_signal *r_read_to_tgt_rsp_data; // data (one cache line) - sc_signal r_read_to_tgt_rsp_word; // first word of the response - sc_signal r_read_to_tgt_rsp_length; // length of the response + sc_signal r_read_to_tgt_rsp_req; // valid request + sc_signal r_read_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_read_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_read_to_tgt_rsp_pktid; // Transaction pktid + sc_signal * r_read_to_tgt_rsp_data; // data (one cache line) + sc_signal r_read_to_tgt_rsp_word; // first word of the response + sc_signal r_read_to_tgt_rsp_length; // length of the response /////////////////////////////////////////////////////////////// @@ -473,57 +481,57 @@ /////////////////////////////////////////////////////////////// - sc_signal r_write_fsm; // FSM state - sc_signal r_write_address; // first word address - sc_signal r_write_word_index; // first word index in line - sc_signal r_write_word_count; // number of words in line - sc_signal r_write_srcid; // transaction srcid - sc_signal r_write_trdid; // transaction trdid - sc_signal r_write_pktid; // transaction pktid - sc_signal *r_write_data; // data (one cache line) - sc_signal *r_write_be; // one byte enable per word - sc_signal r_write_byte; // (BE != 0X0) and (BE != 0xF) - sc_signal r_write_is_cnt; // is_cnt bit (in directory) - sc_signal r_write_lock; // lock bit (in directory) - sc_signal r_write_tag; // cache line tag (in directory) - sc_signal r_write_copy; // first owner of the line - sc_signal r_write_copy_cache; // first owner of the line - sc_signal r_write_copy_inst; // is this owner a ICache ? - sc_signal r_write_count; // number of copies - sc_signal r_write_ptr; // pointer to the heap - sc_signal r_write_next_ptr; // next pointer to the heap - sc_signal r_write_to_dec; // need to decrement update counter - sc_signal r_write_way; // way of the line - sc_signal r_write_trt_index; // index in Transaction Table - sc_signal r_write_upt_index; // index in Update Table + sc_signal r_write_fsm; // FSM state + sc_signal r_write_address; // first word address + sc_signal r_write_word_index; // first word index in line + sc_signal r_write_word_count; // number of words in line + sc_signal r_write_srcid; // transaction srcid + sc_signal r_write_trdid; // transaction trdid + sc_signal r_write_pktid; // transaction pktid + sc_signal * r_write_data; // data (one cache line) + sc_signal * r_write_be; // one byte enable per word + sc_signal r_write_byte; // (BE != 0X0) and (BE != 0xF) + sc_signal r_write_is_cnt; // is_cnt bit (in directory) + sc_signal r_write_lock; // lock bit (in directory) + sc_signal r_write_tag; // cache line tag (in directory) + sc_signal r_write_copy; // first owner of the line + sc_signal r_write_copy_cache; // first owner of the line + sc_signal r_write_copy_inst; // is this owner a ICache ? + sc_signal r_write_count; // number of copies + sc_signal r_write_ptr; // pointer to the heap + sc_signal r_write_next_ptr; // next pointer to the heap + sc_signal r_write_to_dec; // need to decrement update counter + sc_signal r_write_way; // way of the line + sc_signal r_write_trt_index; // index in Transaction Table + sc_signal r_write_upt_index; // index in Update Table // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) - sc_signal r_write_to_tgt_rsp_req; // valid request - sc_signal r_write_to_tgt_rsp_srcid; // transaction srcid - sc_signal r_write_to_tgt_rsp_trdid; // transaction trdid - sc_signal r_write_to_tgt_rsp_pktid; // transaction pktid - - // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) - sc_signal r_write_to_ixr_cmd_req; // valid request - sc_signal r_write_to_ixr_cmd_write; // write request - sc_signal r_write_to_ixr_cmd_nline; // cache line index - sc_signal *r_write_to_ixr_cmd_data; // cache line data - sc_signal r_write_to_ixr_cmd_trdid; // index in Transaction Table + sc_signal r_write_to_tgt_rsp_req; // valid request + sc_signal r_write_to_tgt_rsp_srcid; // transaction srcid + sc_signal r_write_to_tgt_rsp_trdid; // transaction trdid + sc_signal r_write_to_tgt_rsp_pktid; // transaction pktid + + // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) + sc_signal r_write_to_ixr_cmd_req; // valid request + sc_signal r_write_to_ixr_cmd_write; // write request + sc_signal r_write_to_ixr_cmd_nline; // cache line index + sc_signal * r_write_to_ixr_cmd_data; // cache line data + sc_signal r_write_to_ixr_cmd_trdid; // index in Transaction Table // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches) - sc_signal r_write_to_init_cmd_multi_req; // valid multicast request - sc_signal r_write_to_init_cmd_brdcast_req; // valid brdcast request - sc_signal r_write_to_init_cmd_nline; // cache line index - sc_signal r_write_to_init_cmd_trdid; // index in Update Table - sc_signal *r_write_to_init_cmd_data; // data (one cache line) - sc_signal *r_write_to_init_cmd_be; // word enable - sc_signal r_write_to_init_cmd_count; // number of words in line - sc_signal r_write_to_init_cmd_index; // index of first word in line - GenericFifo m_write_to_init_cmd_inst_fifo; // fifo for the L1 type - GenericFifo m_write_to_init_cmd_srcid_fifo; // fifo for srcids - GenericFifo m_write_to_init_cmd_cache_id_fifo; // fifo for srcids + sc_signal r_write_to_init_cmd_multi_req; // valid multicast request + sc_signal r_write_to_init_cmd_brdcast_req; // valid brdcast request + sc_signal r_write_to_init_cmd_nline; // cache line index + sc_signal r_write_to_init_cmd_trdid; // index in Update Table + sc_signal * r_write_to_init_cmd_data; // data (one cache line) + sc_signal * r_write_to_init_cmd_be; // word enable + sc_signal r_write_to_init_cmd_count; // number of words in line + sc_signal r_write_to_init_cmd_index; // index of first word in line + GenericFifo m_write_to_init_cmd_inst_fifo; // fifo for the L1 type + GenericFifo m_write_to_init_cmd_srcid_fifo; // fifo for srcids + GenericFifo m_write_to_init_cmd_cache_id_fifo; // fifo for srcids // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry) - sc_signal r_write_to_init_rsp_req; // valid request - sc_signal r_write_to_init_rsp_upt_index; // index in update table + sc_signal r_write_to_init_rsp_req; // valid request + sc_signal r_write_to_init_rsp_upt_index; // index in update table ///////////////////////////////////////////////////////// @@ -531,16 +539,16 @@ ////////////////////////////////////////////////////////// - sc_signal r_init_rsp_fsm; // FSM state - sc_signal r_init_rsp_upt_index; // index in the Update Table - sc_signal r_init_rsp_srcid; // pending write srcid - sc_signal r_init_rsp_trdid; // pending write trdid - sc_signal r_init_rsp_pktid; // pending write pktid - sc_signal r_init_rsp_nline; // pending write nline + sc_signal r_init_rsp_fsm; // FSM state + sc_signal r_init_rsp_upt_index; // index in the Update Table + sc_signal r_init_rsp_srcid; // pending write srcid + sc_signal r_init_rsp_trdid; // pending write trdid + sc_signal r_init_rsp_pktid; // pending write pktid + sc_signal r_init_rsp_nline; // pending write nline // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction) - sc_signal r_init_rsp_to_tgt_rsp_req; // valid request - sc_signal r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid - sc_signal r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid - sc_signal r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid + sc_signal r_init_rsp_to_tgt_rsp_req; // valid request + sc_signal r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid /////////////////////////////////////////////////////// @@ -548,38 +556,38 @@ /////////////////////////////////////////////////////// - sc_signal r_cleanup_fsm; // FSM state - sc_signal r_cleanup_srcid; // transaction srcid - sc_signal r_cleanup_trdid; // transaction trdid - sc_signal r_cleanup_pktid; // transaction pktid - sc_signal r_cleanup_nline; // cache line index - - sc_signal r_cleanup_copy; // first copy - sc_signal r_cleanup_copy_cache; // first copy - sc_signal r_cleanup_copy_inst; // type of the first copy - sc_signal r_cleanup_count; // number of copies - sc_signal r_cleanup_ptr; // pointer to the heap - sc_signal r_cleanup_prev_ptr; // previous pointer to the heap - sc_signal r_cleanup_prev_srcid; // srcid of previous heap entry - sc_signal r_cleanup_prev_cache_id; // srcid of previous heap entry - sc_signal r_cleanup_prev_inst; // inst bit of previous heap entry - sc_signal r_cleanup_next_ptr; // next pointer to the heap - sc_signal r_cleanup_tag; // cache line tag (in directory) - sc_signal r_cleanup_is_cnt; // inst bit (in directory) - sc_signal r_cleanup_lock; // lock bit (in directory) - sc_signal r_cleanup_dirty; // dirty bit (in directory) - sc_signal r_cleanup_way; // associative way (in cache) - - sc_signal r_cleanup_write_srcid; // srcid of write response - sc_signal r_cleanup_write_trdid; // trdid of write rsp - sc_signal r_cleanup_write_pktid; // pktid of write rsp - sc_signal r_cleanup_need_rsp; // needs a write rsp - - sc_signal r_cleanup_index; // index of the INVAL line (in the UPT) + sc_signal r_cleanup_fsm; // FSM state + sc_signal r_cleanup_srcid; // transaction srcid + sc_signal r_cleanup_trdid; // transaction trdid + sc_signal r_cleanup_pktid; // transaction pktid + sc_signal r_cleanup_nline; // cache line index + + sc_signal r_cleanup_copy; // first copy + sc_signal r_cleanup_copy_cache; // first copy + sc_signal r_cleanup_copy_inst; // type of the first copy + sc_signal r_cleanup_count; // number of copies + sc_signal r_cleanup_ptr; // pointer to the heap + sc_signal r_cleanup_prev_ptr; // previous pointer to the heap + sc_signal r_cleanup_prev_srcid; // srcid of previous heap entry + sc_signal r_cleanup_prev_cache_id; // srcid of previous heap entry + sc_signal r_cleanup_prev_inst; // inst bit of previous heap entry + sc_signal r_cleanup_next_ptr; // next pointer to the heap + sc_signal r_cleanup_tag; // cache line tag (in directory) + sc_signal r_cleanup_is_cnt; // inst bit (in directory) + sc_signal r_cleanup_lock; // lock bit (in directory) + sc_signal r_cleanup_dirty; // dirty bit (in directory) + sc_signal r_cleanup_way; // associative way (in cache) + + sc_signal r_cleanup_write_srcid; // srcid of write response + sc_signal r_cleanup_write_trdid; // trdid of write rsp + sc_signal r_cleanup_write_pktid; // pktid of write rsp + sc_signal r_cleanup_need_rsp; // needs a write rsp + + sc_signal r_cleanup_index; // index of the INVAL line (in the UPT) // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) - sc_signal r_cleanup_to_tgt_rsp_req; // valid request - sc_signal r_cleanup_to_tgt_rsp_srcid; // transaction srcid - sc_signal r_cleanup_to_tgt_rsp_trdid; // transaction trdid - sc_signal r_cleanup_to_tgt_rsp_pktid; // transaction pktid + sc_signal r_cleanup_to_tgt_rsp_req; // valid request + sc_signal r_cleanup_to_tgt_rsp_srcid; // transaction srcid + sc_signal r_cleanup_to_tgt_rsp_trdid; // transaction trdid + sc_signal r_cleanup_to_tgt_rsp_pktid; // transaction pktid /////////////////////////////////////////////////////// @@ -587,54 +595,54 @@ /////////////////////////////////////////////////////// - sc_signal r_sc_fsm; // FSM state - sc_signal r_sc_wdata; // write data word - sc_signal *r_sc_rdata; // read data word - sc_signal r_sc_lfsr; // lfsr for random introducing - sc_signal r_sc_cpt; // size of command - sc_signal r_sc_copy; // Srcid of the first copy - sc_signal r_sc_copy_cache; // Srcid of the first copy - sc_signal r_sc_copy_inst; // Type of the first copy - sc_signal r_sc_count; // number of copies - sc_signal r_sc_ptr; // pointer to the heap - sc_signal r_sc_next_ptr; // next pointer to the heap - sc_signal r_sc_is_cnt; // is_cnt bit (in directory) - sc_signal r_sc_dirty; // dirty bit (in directory) - sc_signal r_sc_way; // way in directory - sc_signal r_sc_set; // set in directory - sc_signal r_sc_tag; // cache line tag (in directory) - sc_signal r_sc_trt_index; // Transaction Table index - sc_signal r_sc_upt_index; // Update Table index - - // Buffer between SC fsm and INIT_CMD fsm (XRAM read) - sc_signal r_sc_to_ixr_cmd_req; // valid request - sc_signal r_sc_to_ixr_cmd_nline; // cache line index - sc_signal r_sc_to_ixr_cmd_trdid; // index in Transaction Table - sc_signal r_sc_to_ixr_cmd_write; // write request - sc_signal *r_sc_to_ixr_cmd_data; // cache line data + sc_signal r_sc_fsm; // FSM state + sc_signal r_sc_wdata; // write data word + sc_signal * r_sc_rdata; // read data word + sc_signal r_sc_lfsr; // lfsr for random introducing + sc_signal r_sc_cpt; // size of command + sc_signal r_sc_copy; // Srcid of the first copy + sc_signal r_sc_copy_cache; // Srcid of the first copy + sc_signal r_sc_copy_inst; // Type of the first copy + sc_signal r_sc_count; // number of copies + sc_signal r_sc_ptr; // pointer to the heap + sc_signal r_sc_next_ptr; // next pointer to the heap + sc_signal r_sc_is_cnt; // is_cnt bit (in directory) + sc_signal r_sc_dirty; // dirty bit (in directory) + sc_signal r_sc_way; // way in directory + sc_signal r_sc_set; // set in directory + sc_signal r_sc_tag; // cache line tag (in directory) + sc_signal r_sc_trt_index; // Transaction Table index + sc_signal r_sc_upt_index; // Update Table index + + // Buffer between SC fsm and INIT_CMD fsm (XRAM read) + sc_signal r_sc_to_ixr_cmd_req; // valid request + sc_signal r_sc_to_ixr_cmd_nline; // cache line index + sc_signal r_sc_to_ixr_cmd_trdid; // index in Transaction Table + sc_signal r_sc_to_ixr_cmd_write; // write request + sc_signal * r_sc_to_ixr_cmd_data; // cache line data // Buffer between SC fsm and TGT_RSP fsm - sc_signal r_sc_to_tgt_rsp_req; // valid request - sc_signal r_sc_to_tgt_rsp_data; // read data word - sc_signal r_sc_to_tgt_rsp_srcid; // Transaction srcid - sc_signal r_sc_to_tgt_rsp_trdid; // Transaction trdid - sc_signal r_sc_to_tgt_rsp_pktid; // Transaction pktid + sc_signal r_sc_to_tgt_rsp_req; // valid request + sc_signal r_sc_to_tgt_rsp_data; // read data word + sc_signal r_sc_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_sc_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_sc_to_tgt_rsp_pktid; // Transaction pktid // Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches) - sc_signal r_sc_to_init_cmd_multi_req; // valid request - sc_signal r_sc_to_init_cmd_brdcast_req; // brdcast request - sc_signal r_sc_to_init_cmd_nline; // cache line index - sc_signal r_sc_to_init_cmd_trdid; // index in Update Table - sc_signal r_sc_to_init_cmd_wdata; // data (one word) - sc_signal r_sc_to_init_cmd_is_long; // it is a 64 bits SC - sc_signal r_sc_to_init_cmd_wdata_high; // data high (one word) - sc_signal r_sc_to_init_cmd_index; // index of the word in line - GenericFifo m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type - GenericFifo m_sc_to_init_cmd_srcid_fifo; // fifo for srcids - GenericFifo m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids + sc_signal r_sc_to_init_cmd_multi_req; // valid request + sc_signal r_sc_to_init_cmd_brdcast_req; // brdcast request + sc_signal r_sc_to_init_cmd_nline; // cache line index + sc_signal r_sc_to_init_cmd_trdid; // index in Update Table + sc_signal r_sc_to_init_cmd_wdata; // data (one word) + sc_signal r_sc_to_init_cmd_is_long; // it is a 64 bits SC + sc_signal r_sc_to_init_cmd_wdata_high; // data high (one word) + sc_signal r_sc_to_init_cmd_index; // index of the word in line + GenericFifo m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type + GenericFifo m_sc_to_init_cmd_srcid_fifo; // fifo for srcids + GenericFifo m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids // Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry) - sc_signal r_sc_to_init_rsp_req; // valid request - sc_signal r_sc_to_init_rsp_upt_index; // index in update table + sc_signal r_sc_to_init_rsp_req; // valid request + sc_signal r_sc_to_init_rsp_upt_index; // index in update table //////////////////////////////////////////////////// @@ -642,10 +650,10 @@ //////////////////////////////////////////////////// - sc_signal r_ixr_rsp_fsm; // FSM state - sc_signal r_ixr_rsp_trt_index; // TRT entry index - sc_signal r_ixr_rsp_cpt; // word counter + sc_signal r_ixr_rsp_fsm; // FSM state + sc_signal r_ixr_rsp_trt_index; // TRT entry index + sc_signal r_ixr_rsp_cpt; // word counter // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) - sc_signal *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready + sc_signal * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready //////////////////////////////////////////////////// @@ -653,46 +661,46 @@ //////////////////////////////////////////////////// - sc_signal r_xram_rsp_fsm; // FSM state - sc_signal r_xram_rsp_trt_index; // TRT entry index - TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer - sc_signal r_xram_rsp_victim_inval; // victim line invalidate - sc_signal r_xram_rsp_victim_is_cnt; // victim line inst bit - sc_signal r_xram_rsp_victim_dirty; // victim line dirty bit - sc_signal r_xram_rsp_victim_way; // victim line way - sc_signal r_xram_rsp_victim_set; // victim line set - sc_signal r_xram_rsp_victim_nline; // victim line index - sc_signal r_xram_rsp_victim_copy; // victim line first copy - sc_signal r_xram_rsp_victim_copy_cache;// victim line first copy - sc_signal r_xram_rsp_victim_copy_inst; // victim line type of first copy - sc_signal r_xram_rsp_victim_count; // victim line number of copies - sc_signal r_xram_rsp_victim_ptr; // victim line pointer to the heap - sc_signal *r_xram_rsp_victim_data; // victim line data - sc_signal r_xram_rsp_upt_index; // UPT entry index - sc_signal r_xram_rsp_next_ptr; // Next pointer to the heap + sc_signal r_xram_rsp_fsm; // FSM state + sc_signal r_xram_rsp_trt_index; // TRT entry index + TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer + sc_signal r_xram_rsp_victim_inval; // victim line invalidate + sc_signal r_xram_rsp_victim_is_cnt; // victim line inst bit + sc_signal r_xram_rsp_victim_dirty; // victim line dirty bit + sc_signal r_xram_rsp_victim_way; // victim line way + sc_signal r_xram_rsp_victim_set; // victim line set + sc_signal r_xram_rsp_victim_nline; // victim line index + sc_signal r_xram_rsp_victim_copy; // victim line first copy + sc_signal r_xram_rsp_victim_copy_cache; // victim line first copy + sc_signal r_xram_rsp_victim_copy_inst; // victim line type of first copy + sc_signal r_xram_rsp_victim_count; // victim line number of copies + sc_signal r_xram_rsp_victim_ptr; // victim line pointer to the heap + sc_signal * r_xram_rsp_victim_data; // victim line data + sc_signal r_xram_rsp_upt_index; // UPT entry index + sc_signal r_xram_rsp_next_ptr; // Next pointer to the heap // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) - sc_signal r_xram_rsp_to_tgt_rsp_req; // Valid request - sc_signal r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid - sc_signal r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid - sc_signal r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid - sc_signal *r_xram_rsp_to_tgt_rsp_data; // data (one cache line) - sc_signal r_xram_rsp_to_tgt_rsp_word; // first word index - sc_signal r_xram_rsp_to_tgt_rsp_length;// length of the response - sc_signal r_xram_rsp_to_tgt_rsp_rerror;// send error to requester - - // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) - sc_signal r_xram_rsp_to_init_cmd_multi_req; // Valid request - sc_signal r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request - sc_signal r_xram_rsp_to_init_cmd_nline; // cache line index; - sc_signal r_xram_rsp_to_init_cmd_trdid; // index of UPT entry - GenericFifo m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type - GenericFifo m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids - GenericFifo m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids + sc_signal r_xram_rsp_to_tgt_rsp_req; // Valid request + sc_signal r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid + sc_signal * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) + sc_signal r_xram_rsp_to_tgt_rsp_word; // first word index + sc_signal r_xram_rsp_to_tgt_rsp_length; // length of the response + sc_signal r_xram_rsp_to_tgt_rsp_rerror; // send error to requester + + // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) + sc_signal r_xram_rsp_to_init_cmd_multi_req; // Valid request + sc_signal r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request + sc_signal r_xram_rsp_to_init_cmd_nline; // cache line index; + sc_signal r_xram_rsp_to_init_cmd_trdid; // index of UPT entry + GenericFifo m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type + GenericFifo m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids + GenericFifo m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) - sc_signal r_xram_rsp_to_ixr_cmd_req; // Valid request - sc_signal r_xram_rsp_to_ixr_cmd_nline; // cache line index - sc_signal *r_xram_rsp_to_ixr_cmd_data; // cache line data - sc_signal r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table + sc_signal r_xram_rsp_to_ixr_cmd_req; // Valid request + sc_signal r_xram_rsp_to_ixr_cmd_nline; // cache line index + sc_signal * r_xram_rsp_to_ixr_cmd_data; // cache line data + sc_signal r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table //////////////////////////////////////////////////// @@ -700,6 +708,6 @@ //////////////////////////////////////////////////// - sc_signal r_ixr_cmd_fsm; - sc_signal r_ixr_cmd_cpt; + sc_signal r_ixr_cmd_fsm; + sc_signal r_ixr_cmd_cpt; //////////////////////////////////////////////////// @@ -707,6 +715,6 @@ //////////////////////////////////////////////////// - sc_signal r_tgt_rsp_fsm; - sc_signal r_tgt_rsp_cpt; + sc_signal r_tgt_rsp_fsm; + sc_signal r_tgt_rsp_cpt; //////////////////////////////////////////////////// @@ -714,5 +722,5 @@ //////////////////////////////////////////////////// - sc_signal r_init_cmd_fsm; + sc_signal r_init_cmd_fsm; sc_signal r_init_cmd_cpt; sc_signal r_init_cmd_inst; @@ -722,5 +730,6 @@ //////////////////////////////////////////////////// - sc_signal r_alloc_dir_fsm; + sc_signal r_alloc_dir_fsm; + sc_signal r_alloc_dir_reset_cpt; //////////////////////////////////////////////////// @@ -728,5 +737,5 @@ //////////////////////////////////////////////////// - sc_signal r_alloc_trt_fsm; + sc_signal r_alloc_trt_fsm; //////////////////////////////////////////////////// @@ -734,5 +743,5 @@ //////////////////////////////////////////////////// - sc_signal r_alloc_upt_fsm; + sc_signal r_alloc_upt_fsm; //////////////////////////////////////////////////// @@ -740,6 +749,6 @@ //////////////////////////////////////////////////// - sc_signal r_alloc_heap_fsm; - + sc_signal r_alloc_heap_fsm; + sc_signal r_alloc_heap_reset_cpt; }; // end class VciMemCacheV4 @@ -755,4 +764,4 @@ // End: -// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 - +// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 + Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 253) +++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 273) @@ -1,7 +1,7 @@ /* -*- c++ -*- - * File : vci_mem_cache_v4.cpp - * Date : 30/10/2008 - * Copyright : UPMC / LIP6 - * Authors : Alain Greiner / Eric Guthmuller + * File : vci_mem_cache_v4.cpp + * Date : 30/10/2008 + * Copyright : UPMC / LIP6 + * Authors : Alain Greiner / Eric Guthmuller * * SOCLIB_LGPL_HEADER_BEGIN @@ -26,4 +26,5 @@ * * Maintainers: alain eric.guthmuller@polytechnique.edu + * cesar.fuguet-tortolero@lip6.fr */ @@ -32,23 +33,23 @@ ////// debug services /////////////////////////////////////////////////////// // All debug messages are conditionned by two variables: -// - compile time : DEBUG_MEMC_*** : defined below -// - execution time : m_debug_*** : defined by constructor arguments +// - compile time : DEBUG_MEMC_*** : defined below +// - execution time : m_debug_*** : defined by constructor arguments // m_debug_* = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) ///////////////////////////////////////////////////////////////////////////////// -#define DEBUG_MEMC_GLOBAL 0 // synthetic trace of all FSMs -#define DEBUG_MEMC_READ 1 // detailed trace of READ FSM -#define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM -#define DEBUG_MEMC_SC 1 // detailed trace of SC FSM -#define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_RSP FSM -#define DEBUG_MEMC_IXR_RSP 1 // detailed trace of IXR_RSP FSM -#define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM -#define DEBUG_MEMC_INIT_CMD 1 // detailed trace of INIT_CMD FSM -#define DEBUG_MEMC_INIT_RSP 1 // detailed trace of INIT_RSP FSM -#define DEBUG_MEMC_TGT_CMD 1 // detailed trace of TGT_CMD FSM -#define DEBUG_MEMC_TGT_RSP 1 // detailed trace of TGT_RSP FSM -#define DEBUG_MEMC_CLEANUP 1 // detailed trace of CLEANUP FSM - -#define RANDOMIZE_SC 1 +#define DEBUG_MEMC_GLOBAL 0 // synthetic trace of all FSMs +#define DEBUG_MEMC_READ 1 // detailed trace of READ FSM +#define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM +#define DEBUG_MEMC_SC 1 // detailed trace of SC FSM +#define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_RSP FSM +#define DEBUG_MEMC_IXR_RSP 1 // detailed trace of IXR_RSP FSM +#define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM +#define DEBUG_MEMC_INIT_CMD 1 // detailed trace of INIT_CMD FSM +#define DEBUG_MEMC_INIT_RSP 1 // detailed trace of INIT_RSP FSM +#define DEBUG_MEMC_TGT_CMD 1 // detailed trace of TGT_CMD FSM +#define DEBUG_MEMC_TGT_RSP 1 // detailed trace of TGT_RSP FSM +#define DEBUG_MEMC_CLEANUP 1 // detailed trace of CLEANUP FSM + +#define RANDOMIZE_SC 1 namespace soclib { namespace caba { @@ -58,5 +59,5 @@ "TGT_CMD_READ", "TGT_CMD_WRITE", - "TGT_CMD_ATOMIC", + "TGT_CMD_ATOMIC" }; const char *tgt_rsp_fsm_str[] = { @@ -72,5 +73,5 @@ "TGT_RSP_XRAM", "TGT_RSP_INIT", - "TGT_RSP_CLEANUP", + "TGT_RSP_CLEANUP" }; const char *init_cmd_fsm_str[] = { @@ -88,5 +89,5 @@ "INIT_CMD_SC_UPDT_INDEX", "INIT_CMD_SC_UPDT_DATA", - "INIT_CMD_SC_UPDT_DATA_HIGH", + "INIT_CMD_SC_UPDT_DATA_HIGH" }; const char *init_rsp_fsm_str[] = { @@ -94,10 +95,12 @@ "INIT_RSP_UPT_LOCK", "INIT_RSP_UPT_CLEAR", - "INIT_RSP_END", + "INIT_RSP_END" }; const char *read_fsm_str[] = { "READ_IDLE", + "READ_DIR_REQ", "READ_DIR_LOCK", "READ_DIR_HIT", + "READ_HEAP_REQ", "READ_HEAP_LOCK", "READ_HEAP_WRITE", @@ -107,9 +110,10 @@ "READ_TRT_LOCK", "READ_TRT_SET", - "READ_TRT_REQ", + "READ_TRT_REQ" }; const char *write_fsm_str[] = { "WRITE_IDLE", "WRITE_NEXT", + "WRITE_DIR_REQ", "WRITE_DIR_LOCK", "WRITE_DIR_READ", @@ -130,5 +134,5 @@ "WRITE_BC_CC_SEND", "WRITE_BC_XRAM_REQ", - "WRITE_WAIT", + "WRITE_WAIT" }; const char *ixr_rsp_fsm_str[] = { @@ -136,5 +140,5 @@ "IXR_RSP_ACK", "IXR_RSP_TRT_ERASE", - "IXR_RSP_TRT_READ", + "IXR_RSP_TRT_READ" }; const char *xram_rsp_fsm_str[] = { @@ -149,8 +153,9 @@ "XRAM_RSP_INVAL", "XRAM_RSP_WRITE_DIRTY", + "XRAM_RSP_HEAP_REQ", "XRAM_RSP_HEAP_ERASE", "XRAM_RSP_HEAP_LAST", "XRAM_RSP_ERROR_ERASE", - "XRAM_RSP_ERROR_RSP", + "XRAM_RSP_ERROR_RSP" }; const char *ixr_cmd_fsm_str[] = { @@ -162,8 +167,9 @@ "IXR_CMD_WRITE_NLINE", "IXR_CMD_SC_NLINE", - "IXR_CMD_XRAM_DATA", + "IXR_CMD_XRAM_DATA" }; const char *sc_fsm_str[] = { "SC_IDLE", + "SC_DIR_REQ", "SC_DIR_LOCK", "SC_DIR_HIT_READ", @@ -183,10 +189,12 @@ "SC_MISS_TRT_SET", "SC_MISS_XRAM_REQ", - "SC_WAIT", + "SC_WAIT" }; const char *cleanup_fsm_str[] = { "CLEANUP_IDLE", + "CLEANUP_DIR_REQ", "CLEANUP_DIR_LOCK", "CLEANUP_DIR_WRITE", + "CLEANUP_HEAP_REQ", "CLEANUP_HEAP_LOCK", "CLEANUP_HEAP_SEARCH", @@ -196,12 +204,13 @@ "CLEANUP_UPT_WRITE", "CLEANUP_WRITE_RSP", - "CLEANUP_RSP", + "CLEANUP_RSP" }; const char *alloc_dir_fsm_str[] = { + "ALLOC_DIR_RESET", "ALLOC_DIR_READ", "ALLOC_DIR_WRITE", "ALLOC_DIR_SC", "ALLOC_DIR_CLEANUP", - "ALLOC_DIR_XRAM_RSP", + "ALLOC_DIR_XRAM_RSP" }; const char *alloc_trt_fsm_str[] = { @@ -210,5 +219,5 @@ "ALLOC_TRT_SC", "ALLOC_TRT_XRAM_RSP", - "ALLOC_TRT_IXR_RSP", + "ALLOC_TRT_IXR_RSP" }; const char *alloc_upt_fsm_str[] = { @@ -217,11 +226,13 @@ "ALLOC_UPT_INIT_RSP", "ALLOC_UPT_CLEANUP", + "ALLOC_UPT_SC" }; const char *alloc_heap_fsm_str[] = { + "ALLOC_HEAP_RESET", "ALLOC_HEAP_READ", "ALLOC_HEAP_WRITE", "ALLOC_HEAP_SC", "ALLOC_HEAP_CLEANUP", - "ALLOC_HEAP_XRAM_RSP", + "ALLOC_HEAP_XRAM_RSP" }; @@ -231,8 +242,8 @@ //////////////////////////////// - // Constructor + // Constructor //////////////////////////////// - tmpl(/**/)::VciMemCacheV4( + tmpl(/**/)::VciMemCacheV4( sc_module_name name, const soclib::common::MappingTable &mtp, @@ -243,10 +254,10 @@ const soclib::common::IntTab &vci_tgt_index, const soclib::common::IntTab &vci_tgt_index_cleanup, - size_t nways, // number of ways per set - size_t nsets, // number of cache sets - size_t nwords, // number of words in cache line - size_t heap_size, // number of heap entries - size_t transaction_tab_lines, // number of TRT entries - size_t update_tab_lines, // number of UPT entries + size_t nways, // number of ways per set + size_t nsets, // number of cache sets + size_t nwords, // number of words in cache line + size_t heap_size, // number of heap entries + size_t transaction_tab_lines, // number of TRT entries + size_t update_tab_lines, // number of UPT entries size_t debug_start_cycle, bool debug_ok) @@ -287,5 +298,5 @@ #undef L2 - // FIFOs + // FIFOs m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4), @@ -311,7 +322,7 @@ r_tgt_cmd_fsm("r_tgt_cmd_fsm"), - - m_nseg(0), - m_ncseg(0), + + m_nseg(0), + m_ncseg(0), r_read_fsm("r_read_fsm"), @@ -352,7 +363,9 @@ r_alloc_dir_fsm("r_alloc_dir_fsm"), + r_alloc_dir_reset_cpt("r_alloc_dir_reset_cpt"), r_alloc_trt_fsm("r_alloc_trt_fsm"), r_alloc_upt_fsm("r_alloc_upt_fsm"), - r_alloc_heap_fsm("r_alloc_heap_fsm") + r_alloc_heap_fsm("r_alloc_heap_fsm"), + r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") { assert(IS_POW_OF_2(nsets)); @@ -370,5 +383,5 @@ m_broadcast_address = 0x3 | (0x7C1F << (vci_param::N-20)); - // Get the segments associated to the MemCache + // Get the segments associated to the MemCache std::list::iterator seg; size_t i; @@ -384,5 +397,5 @@ i = 0; - for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { m_seg[i] = &(*seg); i++; @@ -392,5 +405,5 @@ i = 0; - for ( seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++ ) { + for ( seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++ ) { m_cseg[i] = &(*seg); i++; @@ -407,30 +420,30 @@ for ( size_t k=0; k[m_transaction_tab_lines]; + r_ixr_rsp_to_xram_rsp_rok = new sc_signal[m_transaction_tab_lines]; // Allocation for XRAM_RSP FSM - r_xram_rsp_victim_data = new sc_signal[nwords]; - r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; - r_xram_rsp_to_ixr_cmd_data = new sc_signal[nwords]; + r_xram_rsp_victim_data = new sc_signal[nwords]; + r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; + r_xram_rsp_to_ixr_cmd_data = new sc_signal[nwords]; // Allocation for READ FSM - r_read_data = new sc_signal[nwords]; - r_read_to_tgt_rsp_data = new sc_signal[nwords]; + r_read_data = new sc_signal[nwords]; + r_read_to_tgt_rsp_data = new sc_signal[nwords]; // Allocation for WRITE FSM - r_write_data = new sc_signal[nwords]; - r_write_be = new sc_signal[nwords]; - r_write_to_init_cmd_data = new sc_signal[nwords]; - r_write_to_init_cmd_be = new sc_signal[nwords]; - r_write_to_ixr_cmd_data = new sc_signal[nwords]; + r_write_data = new sc_signal[nwords]; + r_write_be = new sc_signal[nwords]; + r_write_to_init_cmd_data = new sc_signal[nwords]; + r_write_to_init_cmd_be = new sc_signal[nwords]; + r_write_to_ixr_cmd_data = new sc_signal[nwords]; // Allocation for SC FSM - r_sc_to_ixr_cmd_data = new sc_signal[nwords]; - r_sc_rdata = new sc_signal[2]; + r_sc_to_ixr_cmd_data = new sc_signal[nwords]; + r_sc_rdata = new sc_signal[2]; @@ -471,5 +484,5 @@ { std::cout << " MEMC Write Monitor : " << buf << " Address = " << std::hex << addr - << " / Data = " << data << std::endl; + << " / Data = " << data << std::endl; } } @@ -480,5 +493,5 @@ { DirectoryEntry entry = m_cache_directory.read_neutral(addr); - if ( (entry.count != m_debug_previous_count) or + if ( (entry.count != m_debug_previous_count) or (entry.valid != m_debug_previous_hit) ) { @@ -498,13 +511,13 @@ { std::cout << "MEMC " << name() << std::endl; - std::cout << " " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] - << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] + std::cout << " " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] + << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << " | " << read_fsm_str[r_read_fsm] - << " | " << write_fsm_str[r_write_fsm] - << " | " << sc_fsm_str[r_sc_fsm] + << " | " << write_fsm_str[r_write_fsm] + << " | " << sc_fsm_str[r_sc_fsm] << " | " << cleanup_fsm_str[r_cleanup_fsm] << std::endl; std::cout << " " << init_cmd_fsm_str[r_init_cmd_fsm] - << " | " << init_rsp_fsm_str[r_init_rsp_fsm] - << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] + << " | " << init_rsp_fsm_str[r_init_rsp_fsm] + << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl; @@ -515,25 +528,26 @@ ///////////////////////////////////////// { - std::cout << "----------------------------------" << std::dec << std::endl; - std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl - << "- READ RATE = " << (double)m_cpt_read/m_cpt_cycles << std::endl - << "- READ TOTAL = " << m_cpt_read << std::endl - << "- READ MISS RATE = " << (double)m_cpt_read_miss/m_cpt_read << std::endl - << "- WRITE RATE = " << (double)m_cpt_write/m_cpt_cycles << std::endl - << "- WRITE TOTAL = " << m_cpt_write << std::endl - << "- WRITE MISS RATE = " << (double)m_cpt_write_miss/m_cpt_write << std::endl - << "- WRITE BURST LENGTH = " << (double)m_cpt_write_cells/m_cpt_write << std::endl - << "- WRITE BURST TOTAL = " << m_cpt_write_cells << std::endl - << "- REQUESTS TRT FULL = " << m_cpt_trt_full << std::endl - << "- READ TRT BLOKED HIT = " << m_cpt_trt_rb << std::endl - << "- UPDATE RATE = " << (double)m_cpt_update/m_cpt_cycles << std::endl - << "- UPDATE ARITY = " << (double)m_cpt_update_mult/m_cpt_update << std::endl - << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl - << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl - << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl - << "- SAVE DIRTY RATE = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl - << "- CLEANUP RATE = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl - << "- LL RATE = " << (double)m_cpt_ll/m_cpt_cycles << std::endl - << "- SC RATE = " << (double)m_cpt_sc/m_cpt_cycles << std::endl; + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout + << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl + << "- READ RATE = " << (double) m_cpt_read/m_cpt_cycles << std::endl + << "- READ TOTAL = " << m_cpt_read << std::endl + << "- READ MISS RATE = " << (double) m_cpt_read_miss/m_cpt_read << std::endl + << "- WRITE RATE = " << (double) m_cpt_write/m_cpt_cycles << std::endl + << "- WRITE TOTAL = " << m_cpt_write << std::endl + << "- WRITE MISS RATE = " << (double) m_cpt_write_miss/m_cpt_write << std::endl + << "- WRITE BURST LENGTH = " << (double) m_cpt_write_cells/m_cpt_write << std::endl + << "- WRITE BURST TOTAL = " << m_cpt_write_cells << std::endl + << "- REQUESTS TRT FULL = " << m_cpt_trt_full << std::endl + << "- READ TRT BLOKED HIT = " << m_cpt_trt_rb << std::endl + << "- UPDATE RATE = " << (double) m_cpt_update/m_cpt_cycles << std::endl + << "- UPDATE ARITY = " << (double) m_cpt_update_mult/m_cpt_update << std::endl + << "- INVAL MULTICAST RATE = " << (double) (m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl + << "- INVAL MULTICAST ARITY= " << (double) m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl + << "- INVAL BROADCAST RATE = " << (double) m_cpt_inval_brdcast/m_cpt_cycles << std::endl + << "- SAVE DIRTY RATE = " << (double) m_cpt_write_dirty/m_cpt_cycles << std::endl + << "- CLEANUP RATE = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl + << "- LL RATE = " << (double) m_cpt_ll/m_cpt_cycles << std::endl + << "- SC RATE = " << (double) m_cpt_sc/m_cpt_cycles << std::endl; } @@ -570,194 +584,198 @@ ////////////////////////////////// { - using soclib::common::uint32_log2; - - // RESET - if ( ! p_resetn.read() ) { - - // Initializing FSMs - r_tgt_cmd_fsm = TGT_CMD_IDLE; - r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; - r_init_cmd_fsm = INIT_CMD_INVAL_IDLE; - r_init_rsp_fsm = INIT_RSP_IDLE; - r_read_fsm = READ_IDLE; - r_write_fsm = WRITE_IDLE; - r_sc_fsm = SC_IDLE; - r_cleanup_fsm = CLEANUP_IDLE; - r_alloc_dir_fsm = ALLOC_DIR_READ; - r_alloc_heap_fsm = ALLOC_HEAP_READ; - r_alloc_trt_fsm = ALLOC_TRT_READ; - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - r_ixr_rsp_fsm = IXR_RSP_IDLE; - r_xram_rsp_fsm = XRAM_RSP_IDLE; - r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; - - m_debug_global = false; - m_debug_tgt_cmd_fsm = false; - m_debug_tgt_rsp_fsm = false; - m_debug_init_cmd_fsm = false; - m_debug_init_rsp_fsm = false; - m_debug_read_fsm = false; - m_debug_write_fsm = false; - m_debug_sc_fsm = false; - m_debug_cleanup_fsm = false; - m_debug_ixr_cmd_fsm = false; - m_debug_ixr_rsp_fsm = false; - m_debug_xram_rsp_fsm = false; - m_debug_previous_hit = false; - m_debug_previous_count = 0; - - // Initializing Tables - m_cache_directory.init(); - m_transaction_tab.init(); - m_heap.init(); - - // initializing FIFOs and communication Buffers - - m_cmd_read_addr_fifo.init(); - m_cmd_read_length_fifo.init(); - m_cmd_read_srcid_fifo.init(); - m_cmd_read_trdid_fifo.init(); - m_cmd_read_pktid_fifo.init(); - - m_cmd_write_addr_fifo.init(); - m_cmd_write_eop_fifo.init(); - m_cmd_write_srcid_fifo.init(); - m_cmd_write_trdid_fifo.init(); - m_cmd_write_pktid_fifo.init(); - m_cmd_write_data_fifo.init(); - - m_cmd_sc_addr_fifo.init(); - m_cmd_sc_srcid_fifo.init(); - m_cmd_sc_trdid_fifo.init(); - m_cmd_sc_pktid_fifo.init(); - m_cmd_sc_wdata_fifo.init(); - m_cmd_sc_eop_fifo.init(); - - r_read_to_tgt_rsp_req = false; - r_read_to_ixr_cmd_req = false; - - r_write_to_tgt_rsp_req = false; - r_write_to_ixr_cmd_req = false; - r_write_to_init_cmd_multi_req = false; - r_write_to_init_cmd_brdcast_req = false; - r_write_to_init_rsp_req = false; - m_write_to_init_cmd_inst_fifo.init(); - m_write_to_init_cmd_srcid_fifo.init(); + using soclib::common::uint32_log2; + + // RESET + if ( ! p_resetn.read() ) { + + // Initializing FSMs + r_tgt_cmd_fsm = TGT_CMD_IDLE; + r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; + r_init_cmd_fsm = INIT_CMD_INVAL_IDLE; + r_init_rsp_fsm = INIT_RSP_IDLE; + r_read_fsm = READ_IDLE; + r_write_fsm = WRITE_IDLE; + r_sc_fsm = SC_IDLE; + r_cleanup_fsm = CLEANUP_IDLE; + r_alloc_dir_fsm = ALLOC_DIR_RESET; + r_alloc_heap_fsm = ALLOC_HEAP_RESET; + r_alloc_trt_fsm = ALLOC_TRT_READ; + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + r_ixr_rsp_fsm = IXR_RSP_IDLE; + r_xram_rsp_fsm = XRAM_RSP_IDLE; + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + + m_debug_global = false; + m_debug_tgt_cmd_fsm = false; + m_debug_tgt_rsp_fsm = false; + m_debug_init_cmd_fsm = false; + m_debug_init_rsp_fsm = false; + m_debug_read_fsm = false; + m_debug_write_fsm = false; + m_debug_sc_fsm = false; + m_debug_cleanup_fsm = false; + m_debug_ixr_cmd_fsm = false; + m_debug_ixr_rsp_fsm = false; + m_debug_xram_rsp_fsm = false; + m_debug_previous_hit = false; + m_debug_previous_count = 0; + + // Initializing Tables + m_transaction_tab.init(); + m_update_tab.init(); + + // initializing FIFOs and communication Buffers + + m_cmd_read_addr_fifo.init(); + m_cmd_read_length_fifo.init(); + m_cmd_read_srcid_fifo.init(); + m_cmd_read_trdid_fifo.init(); + m_cmd_read_pktid_fifo.init(); + + m_cmd_write_addr_fifo.init(); + m_cmd_write_eop_fifo.init(); + m_cmd_write_srcid_fifo.init(); + m_cmd_write_trdid_fifo.init(); + m_cmd_write_pktid_fifo.init(); + m_cmd_write_data_fifo.init(); + + m_cmd_sc_addr_fifo.init(); + m_cmd_sc_srcid_fifo.init(); + m_cmd_sc_trdid_fifo.init(); + m_cmd_sc_pktid_fifo.init(); + m_cmd_sc_wdata_fifo.init(); + m_cmd_sc_eop_fifo.init(); + + r_read_to_tgt_rsp_req = false; + r_read_to_ixr_cmd_req = false; + + r_write_to_tgt_rsp_req = false; + r_write_to_ixr_cmd_req = false; + r_write_to_init_cmd_multi_req = false; + r_write_to_init_cmd_brdcast_req = false; + r_write_to_init_rsp_req = false; + + m_write_to_init_cmd_inst_fifo.init(); + m_write_to_init_cmd_srcid_fifo.init(); #if L1_MULTI_CACHE - m_write_to_init_cmd_cache_id_fifo.init(); -#endif - - r_cleanup_to_tgt_rsp_req = false; - - r_init_rsp_to_tgt_rsp_req = false; - - r_sc_to_tgt_rsp_req = false; - r_sc_cpt = 0; - r_sc_lfsr = -1; - r_sc_to_ixr_cmd_req = false; - r_sc_to_init_cmd_multi_req = false; - r_sc_to_init_cmd_brdcast_req = false; - m_sc_to_init_cmd_inst_fifo.init(); - m_sc_to_init_cmd_srcid_fifo.init(); + m_write_to_init_cmd_cache_id_fifo.init(); +#endif + + r_cleanup_to_tgt_rsp_req = false; + + r_init_rsp_to_tgt_rsp_req = false; + + r_sc_to_tgt_rsp_req = false; + r_sc_cpt = 0; + r_sc_lfsr = -1; + r_sc_to_ixr_cmd_req = false; + r_sc_to_init_cmd_multi_req = false; + r_sc_to_init_cmd_brdcast_req = false; + + m_sc_to_init_cmd_inst_fifo.init(); + m_sc_to_init_cmd_srcid_fifo.init(); #if L1_MULTI_CACHE - m_sc_to_init_cmd_cache_id_fifo.init(); -#endif - - for(size_t i=0; i m_debug_start_cycle) and m_debug_ok; -m_debug_tgt_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_tgt_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_init_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_init_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_read_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_write_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_sc_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_cleanup_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_ixr_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_ixr_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; -m_debug_xram_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - - -#if DEBUG_MEMC_GLOBAL -if( m_debug_global ) -{ - std::cout << "---------------------------------------------" << std::dec << std::endl; - std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl + size_t sc_to_init_cmd_fifo_cache_id = 0; +#endif + + m_debug_global = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_tgt_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_tgt_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_init_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_init_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_read_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_write_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_sc_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_cleanup_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_ixr_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_ixr_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_xram_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + +#if DEBUG_MEMC_GLOBAL + if( m_debug_global ) + { + std::cout + << "---------------------------------------------" << std::dec << std::endl + << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl << " - TGT_CMD FSM = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl << " - TGT_RSP FSM = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl @@ -775,1706 +793,1912 @@ << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm] << std::endl; -} -#endif - - //////////////////////////////////////////////////////////////////////////////////// - // TGT_CMD FSM - //////////////////////////////////////////////////////////////////////////////////// - // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors - // - // There is 3 types of accepted commands : - // - READ : a READ request has a length of 1 VCI cell. It can be a single word - // or an entire cache line, depending on the PLEN value. - // - WRITE : a WRITE request has a maximum length of 16 cells, and can only - // concern words in a same line. - // - SC : The SC request has a length of 2 cells or 4 cells. - //////////////////////////////////////////////////////////////////////////////////// - - switch ( r_tgt_cmd_fsm.read() ) + } +#endif + + //////////////////////////////////////////////////////////////////////////////////// + // TGT_CMD FSM + //////////////////////////////////////////////////////////////////////////////////// + // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors + // + // There is 3 types of accepted commands : + // - READ : a READ request has a length of 1 VCI cell. It can be a single word + // or an entire cache line, depending on the PLEN value. + // - WRITE : a WRITE request has a maximum length of 16 cells, and can only + // concern words in a same line. + // - SC : The SC request has a length of 2 cells or 4 cells. + //////////////////////////////////////////////////////////////////////////////////// + + switch ( r_tgt_cmd_fsm.read() ) + { + ////////////////// + case TGT_CMD_IDLE: + if ( p_vci_tgt.cmdval ) + { + +#if DEBUG_MEMC_TGT_CMD + if( m_debug_tgt_cmd_fsm ) + { + std::cout + << " Receive command from srcid " + << std::dec << p_vci_tgt.srcid.read() + << " / for address " << std::hex << p_vci_tgt.address.read() << std::endl; + } +#endif + // checking segmentation violation + vci_addr_t address = p_vci_tgt.address.read(); + uint32_t plen = p_vci_tgt.plen.read(); + bool found = false; + for ( size_t seg_id = 0 ; seg_id < m_nseg ; seg_id++ ) + { + if ( m_seg[seg_id]->contains(address) && + m_seg[seg_id]->contains(address + plen - vci_param::B) ) + { + found = true; + } + } + if ( not found ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << std::endl; + std::cout + << "Out of segment VCI address in TGT_CMD_IDLE state (address = " + << std::hex << address << ", srcid = " << p_vci_tgt.srcid.read() + << std::dec << ", cycle = " << m_cpt_cycles << ")" << std::endl; + exit(0); + } + + if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) + { + r_tgt_cmd_fsm = TGT_CMD_READ; + } + else if ( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) + { + r_tgt_cmd_fsm = TGT_CMD_WRITE; + } + else if ( p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND ) + { + r_tgt_cmd_fsm = TGT_CMD_ATOMIC; + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " TGT_CMD_IDLE state" << std::endl; + std::cout << " illegal VCI command type" << std::endl; + exit(0); + } + } + break; + + ////////////////// + case TGT_CMD_READ: + if ((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2)) > 16) + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << std::endl; + std::cout + << " illegal address/plen combination for VCI read command" << std::endl; + exit(0); + } + if ( !p_vci_tgt.eop.read() ) + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << std::endl; + std::cout + << " read command packets must contain one single flit" + << std::endl; + exit(0); + } + + if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) + { + +#if DEBUG_MEMC_TGT_CMD + if( m_debug_tgt_cmd_fsm ) + { + std::cout << " Push into read_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " srcid = " << std::dec << p_vci_tgt.srcid.read() + << " trdid = " << p_vci_tgt.trdid.read() + << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; + } +#endif + cmd_read_fifo_put = true; + m_cpt_read++; + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + break; + + /////////////////// + case TGT_CMD_WRITE: + if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) + { + +#if DEBUG_MEMC_TGT_CMD + if( m_debug_tgt_cmd_fsm ) + { + std::cout << " Push into write_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " srcid = " << std::dec << p_vci_tgt.srcid.read() + << " trdid = " << p_vci_tgt.trdid.read() + << " wdata = " << std::hex << p_vci_tgt.wdata.read() + << " be = " << p_vci_tgt.be.read() + << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; + } +#endif + cmd_write_fifo_put = true; + if( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + break; + + //////////////////// + case TGT_CMD_ATOMIC: + if ( (p_vci_tgt.plen.read() != 8) && (p_vci_tgt.plen.read() != 16) ) + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_ATOMIC state" + << std::endl + << "illegal format for sc command " << std::endl; + + exit(0); + } + + if ( p_vci_tgt.cmdval && m_cmd_sc_addr_fifo.wok() ) + { + +#if DEBUG_MEMC_TGT_CMD + if( m_debug_tgt_cmd_fsm ) + { + std::cout << " Pushing command into cmd_sc_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " srcid = " << std::dec << p_vci_tgt.srcid.read() + << " trdid = " << p_vci_tgt.trdid.read() + << " wdata = " << std::hex << p_vci_tgt.wdata.read() + << " be = " << p_vci_tgt.be.read() + << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; + } +#endif + cmd_sc_fifo_put = true; + if( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + break; + } // end switch tgt_cmd_fsm + + ///////////////////////////////////////////////////////////////////////// + // INIT_RSP FSM + ///////////////////////////////////////////////////////////////////////// + // This FSM controls the response to the update or inval coherence + // requests sent by the memory cache to the L1 caches and update the UPT. + // + // It can be update or inval requests initiated by the WRITE FSM, + // or inval requests initiated by the XRAM_RSP FSM. + // It can also be a direct request from the WRITE FSM. + // + // The FSM decrements the proper entry in UPT. + // It sends a request to the TGT_RSP FSM to complete the pending + // write transaction (acknowledge response to the writer processor), + // and clear the UPT entry when all responses have been received. + // + // All those response packets are one word, compact + // packets complying with the VCI advanced format. + // The index in the Table is defined in the RTRDID field, and + // the transaction type is defined in the UPT entry. + ///////////////////////////////////////////////////////////////////// + + switch ( r_init_rsp_fsm.read() ) + { + /////////////////// + case INIT_RSP_IDLE: // wait a response for a coherence transaction + if ( p_vci_ini.rspval ) + { + +#if DEBUG_MEMC_INIT_RSP + if( m_debug_init_rsp_fsm ) + { + std::cout << " Response for UPT entry " + << p_vci_ini.rtrdid.read() << std::endl; + } +#endif + if ( p_vci_ini.rtrdid.read() >= m_update_tab.size() ) + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() + << " INIT_RSP_IDLE state" << std::endl + << "index too large for UPT: " + << " / rtrdid = " << std::dec << p_vci_ini.rtrdid.read() + << " / UPT size = " << std::dec << m_update_tab.size() + << std::endl; + + exit(0); + } + if ( !p_vci_ini.reop.read() ) + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() + << " INIT_RSP_IDLE state" << std::endl + << "all coherence response packets must be one flit" + << std::endl; + + exit(0); + } + + r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); + r_init_rsp_fsm = INIT_RSP_UPT_LOCK; + } + else if( r_write_to_init_rsp_req.read() ) + { + r_init_rsp_upt_index = r_write_to_init_rsp_upt_index.read(); + r_write_to_init_rsp_req = false; + r_init_rsp_fsm = INIT_RSP_UPT_LOCK; + } + break; + + /////////////////////// + case INIT_RSP_UPT_LOCK: // decrement the number of expected responses + if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) + { + size_t count = 0; + bool valid = m_update_tab.decrement(r_init_rsp_upt_index.read(), count); + +#if DEBUG_MEMC_INIT_RSP + if( m_debug_init_rsp_fsm ) + { + std::cout << " Decrement the responses counter for UPT:" + << " entry = " << r_init_rsp_upt_index.read() + << " / rsp_count = " << std::dec << count << std::endl; + } +#endif + if ( not valid ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " INIT_RSP_UPT_LOCK state" << std::endl + << "unsuccessful access to decrement the UPT" << std::endl; + + exit(0); + } + + if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR; + else r_init_rsp_fsm = INIT_RSP_IDLE; + } + break; + + //////////////////////// + case INIT_RSP_UPT_CLEAR: // clear the UPT entry + if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) + { + r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read()); + r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read()); + r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read()); + r_init_rsp_nline = m_update_tab.nline(r_init_rsp_upt_index.read()); + bool need_rsp = m_update_tab.need_rsp(r_init_rsp_upt_index.read()); + + if ( need_rsp ) r_init_rsp_fsm = INIT_RSP_END; + else r_init_rsp_fsm = INIT_RSP_IDLE; + + m_update_tab.clear(r_init_rsp_upt_index.read()); + +#if DEBUG_MEMC_INIT_RSP + if ( m_debug_init_rsp_fsm ) + { + std::cout << " Clear UPT entry " + << r_init_rsp_upt_index.read() << std::endl; + } +#endif + } + break; + + ////////////////// + case INIT_RSP_END: // Post a request to TGT_RSP FSM + if ( !r_init_rsp_to_tgt_rsp_req ) + { + r_init_rsp_to_tgt_rsp_req = true; + r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read(); + r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read(); + r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read(); + r_init_rsp_fsm = INIT_RSP_IDLE; + +#if DEBUG_MEMC_INIT_RSP + if ( m_debug_init_rsp_fsm ) + { + std::cout + << " Request TGT_RSP FSM to send a response to srcid " + << r_init_rsp_srcid.read() + << std::endl; + } +#endif + } + break; + } // end switch r_init_rsp_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // READ FSM + //////////////////////////////////////////////////////////////////////////////////// + // The READ FSM controls the VCI read requests. + // It takes the lock protecting the cache directory to check the cache line status: + // - In case of HIT + // The fsm copies the data (one line, or one single word) + // in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty. + // The requesting initiator is registered in the cache directory. + // If the number of copy is larger than 1, the new copy is registered + // in the HEAP. + // If the number of copy is larger than the threshold, the HEAP is cleared, + // and the corresponding line switches to the counter mode. + // - In case of MISS + // The READ fsm takes the lock protecting the transaction tab. + // If a read transaction to the XRAM for this line already exists, + // or if the transaction tab is full, the fsm is stalled. + // If a TRT entry is free, the READ request is registered in TRT, + // it is consumed in the request FIFO, and transmited to the IXR_CMD FSM. + // The READ FSM returns in the IDLE state as the read transaction will be + // completed when the missing line will be received. + //////////////////////////////////////////////////////////////////////////////////// + + switch ( r_read_fsm.read() ) + { + /////////////// + case READ_IDLE: + // waiting a read request { - ////////////////// - case TGT_CMD_IDLE: - { - if ( p_vci_tgt.cmdval ) - { - -#if DEBUG_MEMC_TGT_CMD -if( m_debug_tgt_cmd_fsm ) -{ - std::cout << " Receive command from srcid " << std::dec << p_vci_tgt.srcid.read() - << " / for address " << std::hex << p_vci_tgt.address.read() << std::endl; -} -#endif - // checking segmentation violation - vci_addr_t address = p_vci_tgt.address.read(); - uint32_t plen = p_vci_tgt.plen.read(); - bool found = false; - for ( size_t seg_id = 0 ; seg_id < m_nseg ; seg_id++ ) - { - if ( m_seg[seg_id]->contains(address) && - m_seg[seg_id]->contains(address + plen - vci_param::B) ) - { - found = true; - } - } - if ( not found ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << std::endl; - std::cout << "Out of segment VCI address in TGT_CMD_IDLE state (address = " << std::hex << address << ", srcid = " << p_vci_tgt.srcid.read() << std::dec << ", cycle = " << m_cpt_cycles << ")" << std::endl; - exit(0); - } - - if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) - { - r_tgt_cmd_fsm = TGT_CMD_READ; - } - else if ( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) - { - r_tgt_cmd_fsm = TGT_CMD_WRITE; - } - else if ( p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND ) - { - r_tgt_cmd_fsm = TGT_CMD_ATOMIC; - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " TGT_CMD_IDLE state" << std::endl; - std::cout << " illegal VCI command type" << std::endl; - exit(0); - } - } - break; - } - ////////////////// - case TGT_CMD_READ: - { - if ((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2)) > 16) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" << std::endl; - std::cout << " illegal address/plen combination for VCI read command" << std::endl; - exit(0); - } - if ( !p_vci_tgt.eop.read() ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" << std::endl; - std::cout << " read command packets must contain one single flit" << std::endl; - exit(0); - } - - if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) - { - -#if DEBUG_MEMC_TGT_CMD -if( m_debug_tgt_cmd_fsm ) -{ - std::cout << " Push into read_fifo:" - << " address = " << std::hex << p_vci_tgt.address.read() - << " srcid = " << std::dec << p_vci_tgt.srcid.read() - << " trdid = " << p_vci_tgt.trdid.read() - << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; -} -#endif - cmd_read_fifo_put = true; - m_cpt_read++; - r_tgt_cmd_fsm = TGT_CMD_IDLE; - } - break; - } - /////////////////// - case TGT_CMD_WRITE: - { - if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) - { - -#if DEBUG_MEMC_TGT_CMD -if( m_debug_tgt_cmd_fsm ) -{ - std::cout << " Push into write_fifo:" - << " address = " << std::hex << p_vci_tgt.address.read() - << " srcid = " << std::dec << p_vci_tgt.srcid.read() - << " trdid = " << p_vci_tgt.trdid.read() - << " wdata = " << std::hex << p_vci_tgt.wdata.read() - << " be = " << p_vci_tgt.be.read() - << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; -} -#endif - cmd_write_fifo_put = true; - if( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE; - } - break; - } - //////////////////// - case TGT_CMD_ATOMIC: - { - if ( (p_vci_tgt.plen.read() != 8) && (p_vci_tgt.plen.read() != 16) ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_ATOMIC state" << std::endl; - std::cout << "illegal format for sc command " << std::endl; - exit(0); - } - - if ( p_vci_tgt.cmdval && m_cmd_sc_addr_fifo.wok() ) - { - -#if DEBUG_MEMC_TGT_CMD -if( m_debug_tgt_cmd_fsm ) -{ - std::cout << " Pushing command into cmd_sc_fifo:" - << " address = " << std::hex << p_vci_tgt.address.read() - << " srcid = " << std::dec << p_vci_tgt.srcid.read() - << " trdid = " << p_vci_tgt.trdid.read() - << " wdata = " << std::hex << p_vci_tgt.wdata.read() - << " be = " << p_vci_tgt.be.read() - << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; -} -#endif - cmd_sc_fifo_put = true; - if( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE; - } - break; - } - } // end switch tgt_cmd_fsm - - ///////////////////////////////////////////////////////////////////////// - // INIT_RSP FSM - ///////////////////////////////////////////////////////////////////////// - // This FSM controls the response to the update or inval coherence - // requests sent by the memory cache to the L1 caches and update the UPT. - // - // It can be update or inval requests initiated by the WRITE FSM, - // or inval requests initiated by the XRAM_RSP FSM. - // It can also be a direct request from the WRITE FSM. - // - // The FSM decrements the proper entry in UPT. - // It sends a request to the TGT_RSP FSM to complete the pending - // write transaction (acknowledge response to the writer processor), - // and clear the UPT entry when all responses have been received. - // - // All those response packets are one word, compact - // packets complying with the VCI advanced format. - // The index in the Table is defined in the RTRDID field, and - // the transaction type is defined in the UPT entry. - ///////////////////////////////////////////////////////////////////// - - switch ( r_init_rsp_fsm.read() ) + if (m_cmd_read_addr_fifo.rok()) + { + +#if DEBUG_MEMC_READ + if( m_debug_read_fsm ) + { + std::cout << " Read request:" + << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; + } +#endif + r_read_fsm = READ_DIR_REQ; + } + break; + } + + /////////////////// + case READ_DIR_REQ: + // Get the lock to the directory { - /////////////////// - case INIT_RSP_IDLE: // wait a response for a coherence transaction - { - if ( p_vci_ini.rspval ) - { - -#if DEBUG_MEMC_INIT_RSP -if( m_debug_init_rsp_fsm ) -{ - std::cout << " Response for UPT entry " - << p_vci_ini.rtrdid.read() << std::endl; -} -#endif - if ( p_vci_ini.rtrdid.read() >= m_update_tab.size() ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " INIT_RSP_IDLE state" << std::endl - << "index too large for UPT: " - << " / rtrdid = " << std::dec << p_vci_ini.rtrdid.read() - << " / UPT size = " << std::dec << m_update_tab.size() << std::endl; - exit(0); - } - if ( !p_vci_ini.reop.read() ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " INIT_RSP_IDLE state" << std::endl; - std::cout << "all coherence response packets must be one flit" << std::endl; - exit(0); - } - - r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); - r_init_rsp_fsm = INIT_RSP_UPT_LOCK; - } - else if( r_write_to_init_rsp_req.read() ) - { - r_init_rsp_upt_index = r_write_to_init_rsp_upt_index.read(); - r_write_to_init_rsp_req = false; - r_init_rsp_fsm = INIT_RSP_UPT_LOCK; - } - break; - } - /////////////////////// - case INIT_RSP_UPT_LOCK: // decrement the number of expected responses - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) - { - size_t count = 0; - bool valid = m_update_tab.decrement(r_init_rsp_upt_index.read(), count); - -#if DEBUG_MEMC_INIT_RSP -if( m_debug_init_rsp_fsm ) -{ - std::cout << " Decrement the responses counter for UPT:" - << " entry = " << r_init_rsp_upt_index.read() - << " / rsp_count = " << std::dec << count << std::endl; -} -#endif - if ( not valid ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " INIT_RSP_UPT_LOCK state" << std::endl - << "unsuccessful access to decrement the UPT" << std::endl; - exit(0); - } - - if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR; - else r_init_rsp_fsm = INIT_RSP_IDLE; - } - break; - } - //////////////////////// - case INIT_RSP_UPT_CLEAR: // clear the UPT entry - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) - { - r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read()); - r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read()); - r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read()); - r_init_rsp_nline = m_update_tab.nline(r_init_rsp_upt_index.read()); - bool need_rsp = m_update_tab.need_rsp(r_init_rsp_upt_index.read()); - - if ( need_rsp ) r_init_rsp_fsm = INIT_RSP_END; - else r_init_rsp_fsm = INIT_RSP_IDLE; - - m_update_tab.clear(r_init_rsp_upt_index.read()); - -#if DEBUG_MEMC_INIT_RSP -if ( m_debug_init_rsp_fsm ) -{ - std::cout << " Clear UPT entry " - << r_init_rsp_upt_index.read() << std::endl; -} -#endif - } - break; - } - ////////////////// - case INIT_RSP_END: // Post a request to TGT_RSP FSM - { - if ( !r_init_rsp_to_tgt_rsp_req ) - { - r_init_rsp_to_tgt_rsp_req = true; - r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read(); - r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read(); - r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read(); - r_init_rsp_fsm = INIT_RSP_IDLE; - -#if DEBUG_MEMC_INIT_RSP -if ( m_debug_init_rsp_fsm ) -{ - std::cout << " Request TGT_RSP FSM to send a response to srcid " - << r_init_rsp_srcid.read() << std::endl; -} -#endif - } - break; - } - } // end switch r_init_rsp_fsm - - //////////////////////////////////////////////////////////////////////////////////// - // READ FSM - //////////////////////////////////////////////////////////////////////////////////// - // The READ FSM controls the VCI read requests. - // It takes the lock protecting the cache directory to check the cache line status: - // - In case of HIT - // The fsm copies the data (one line, or one single word) - // in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty. - // The requesting initiator is registered in the cache directory. - // If the number of copy is larger than 1, the new copy is registered - // in the HEAP. - // If the number of copy is larger than the threshold, the HEAP is cleared, - // and the corresponding line switches to the counter mode. - // - In case of MISS - // The READ fsm takes the lock protecting the transaction tab. - // If a read transaction to the XRAM for this line already exists, - // or if the transaction tab is full, the fsm is stalled. - // If a TRT entry is free, the READ request is registered in TRT, - // it is consumed in the request FIFO, and transmited to the IXR_CMD FSM. - // The READ FSM returns in the IDLE state as the read transaction will be - // completed when the missing line will be received. - //////////////////////////////////////////////////////////////////////////////////// - - switch ( r_read_fsm.read() ) + if ( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) + { + r_read_fsm = READ_DIR_LOCK; + } + +#if DEBUG_MEMC_READ + if( m_debug_read_fsm ) + { + std::cout + << " Requesting DIR lock " + << std::endl; + } +#endif + break; + } + + /////////////////// + case READ_DIR_LOCK: + // check directory for hit / miss { - /////////////// - case READ_IDLE: // waiting a read request - { - if (m_cmd_read_addr_fifo.rok()) - { + if ( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) + { + size_t way = 0; + DirectoryEntry entry = + m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); + + r_read_is_cnt = entry.is_cnt; + r_read_dirty = entry.dirty; + r_read_lock = entry.lock; + r_read_tag = entry.tag; + r_read_way = way; + r_read_count = entry.count; + r_read_copy = entry.owner.srcid; + +#if L1_MULTI_CACHE + r_read_copy_cache = entry.owner.cache_id; +#endif + r_read_copy_inst = entry.owner.inst; + r_read_ptr = entry.ptr; // pointer to the heap + + bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1); + if( entry.valid ) // hit + { + // test if we need to register a new copy in the heap + if ( entry.is_cnt || (entry.count == 0) || !cached_read ) + { + r_read_fsm = READ_DIR_HIT; + } + else + { + r_read_fsm = READ_HEAP_REQ; + } + } + else // miss + { + r_read_fsm = READ_TRT_LOCK; + } #if DEBUG_MEMC_READ -if( m_debug_read_fsm ) -{ - std::cout << " Read request:" - << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; -} -#endif - r_read_fsm = READ_DIR_LOCK; - } - break; - } - /////////////////// - case READ_DIR_LOCK: // check directory for hit / miss - { - if ( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) - { - size_t way = 0; - DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); - - r_read_is_cnt = entry.is_cnt; - r_read_dirty = entry.dirty; - r_read_lock = entry.lock; - r_read_tag = entry.tag; - r_read_way = way; - r_read_count = entry.count; - r_read_copy = entry.owner.srcid; - + if( m_debug_read_fsm ) + { + std::cout + << " Accessing directory: " + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / count = " < we must update the copies + { + if (!is_cnt) // Not counter mode + { + entry.owner.srcid = m_cmd_read_srcid_fifo.read(); #if L1_MULTI_CACHE - r_read_copy_cache = entry.owner.cache_id; -#endif - r_read_copy_inst = entry.owner.inst; - r_read_ptr = entry.ptr; // pointer to the heap - - bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1); - if( entry.valid ) // hit - { - // test if we need to register a new copy in the heap - if ( entry.is_cnt || (entry.count == 0) || !cached_read ) - r_read_fsm = READ_DIR_HIT; - else - r_read_fsm = READ_HEAP_LOCK; - } - else // miss - { - r_read_fsm = READ_TRT_LOCK; - } + entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); +#endif + entry.owner.inst = inst_read; + entry.count = r_read_count.read() + 1; + } + else // Counter mode + { + entry.owner.srcid = 0; +#if L1_MULTI_CACHE + entry.owner.cache_id = 0; +#endif + entry.owner.inst = false; + entry.count = r_read_count.read() + 1; + } + } + else // Uncached read + { + entry.owner.srcid = r_read_copy.read(); +#if L1_MULTI_CACHE + entry.owner.cache_id = r_read_copy_cache.read(); +#endif + entry.owner.inst = r_read_copy_inst.read(); + entry.count = r_read_count.read(); + } #if DEBUG_MEMC_READ -if( m_debug_read_fsm ) -{ - std::cout << " Accessing directory: " - << " address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / hit = " << std::dec << entry.valid - << " / count = " < Update directory entry:" + << " set = " << std::dec << set + << " / way = " << way + << " / owner_id = " << entry.owner.srcid + << " / owner_ins = " << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + } +#endif + + m_cache_directory.write(set, way, entry); + r_read_fsm = READ_RSP; + } + break; + } + + //////////////////// + case READ_HEAP_REQ: + // Get the lock to the HEAP directory + { + if( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) + { + r_read_fsm = READ_HEAP_LOCK; + } + +#if DEBUG_MEMC_READ + if( m_debug_read_fsm ) + { + std::cout + << " Requesting HEAP lock " + << std::endl; + } +#endif + break; + } + + //////////////////// + case READ_HEAP_LOCK: + // read data in cache, update the directory + // and prepare the HEAP update + { + if( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) + { + // enter counter mode when we reach the limit of copies or the heap is full + bool go_cnt = (r_read_count.read() >= r_copies_limit.read()) || m_heap.is_full(); + + // read data in the cache + size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())]; + size_t way = r_read_way.read(); + for ( size_t i=0 ; i1 ) // heap must be cleared + { + HeapEntry next_entry = m_heap.read(r_read_ptr.read()); + r_read_next_ptr = m_heap.next_free_ptr(); + m_heap.write_free_ptr(r_read_ptr.read()); + + if( next_entry.next == r_read_ptr.read() ) // last entry + { + r_read_fsm = READ_HEAP_LAST; // erase the entry + } + else // not the last entry + { + r_read_ptr = next_entry.next; + r_read_fsm = READ_HEAP_ERASE; // erase the list + } + } + else // the heap is not used / nothing to do + { + r_read_fsm = READ_RSP; + } + } + +#if DEBUG_MEMC_READ + if( m_debug_read_fsm ) + { + std::cout << " Update directory:" + << " tag = " << std::hex << entry.tag + << " set = " << std::dec << set + << " way = " << way + << " count = " << entry.count + << " is_cnt = " << entry.is_cnt << std::endl; + } +#endif + } + else + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() + << " READ_HEAP_LOCK state" << std::endl + << "Bad HEAP allocation" << std::endl; + + exit(0); + } + + break; + } + + ///////////////////// + case READ_HEAP_WRITE: // add a entry in the heap + { + if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) + { + HeapEntry heap_entry; + heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); #if L1_MULTI_CACHE - entry.owner.cache_id = r_read_copy_cache.read(); -#endif - entry.owner.inst = r_read_copy_inst.read(); - entry.count = r_read_count.read(); - } + heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); +#endif + heap_entry.owner.inst = (m_cmd_read_trdid_fifo.read() & 0x2); + + if(r_read_count.read() == 1) // creation of a new linked list + { + heap_entry.next = m_heap.next_free_ptr(); + } + else // head insertion in existing list + { + heap_entry.next = r_read_ptr.read(); + } + m_heap.write_free_entry(heap_entry); + m_heap.write_free_ptr(r_read_next_ptr.read()); + if(r_read_last_free.read()) m_heap.set_full(); + + r_read_fsm = READ_RSP; #if DEBUG_MEMC_READ -if( m_debug_read_fsm ) -{ - std::cout << " Update directory entry:" - << " set = " << std::dec << set - << " / way = " << way - << " / owner_id = " << entry.owner.srcid - << " / owner_ins = " << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -} -#endif - - m_cache_directory.write(set, way, entry); - r_read_fsm = READ_RSP; - } - break; - } - //////////////////// - case READ_HEAP_LOCK: // read data in cache, update the directory - // and prepare the HEAP update - { - if( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) - { - // enter counter mode when we reach the limit of copies or the heap is full - bool go_cnt = (r_read_count.read() >= r_copies_limit.read()) || m_heap.is_full(); - - // read data in the cache - size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())]; - size_t way = r_read_way.read(); - for ( size_t i=0 ; i Add an entry in the heap:" + << " owner_id = " << heap_entry.owner.srcid + << " owner_ins = " << heap_entry.owner.inst << std::endl; + } +#endif + } + else + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() + << " READ_HEAP_WRITE state" << std::endl + << "Bad HEAP allocation" << std::endl; + + exit(0); + } + break; + } + + ///////////////////// + case READ_HEAP_ERASE: + { + if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) + { + HeapEntry next_entry = m_heap.read(r_read_ptr.read()); + if( next_entry.next == r_read_ptr.read() ) + { + r_read_fsm = READ_HEAP_LAST; + } + else + { + r_read_ptr = next_entry.next; + r_read_fsm = READ_HEAP_ERASE; + } + } + else + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() + << " READ_HEAP_ERASE state" << std::endl + << "Bad HEAP allocation" << std::endl; + + exit(0); + } + break; + } + + //////////////////// + case READ_HEAP_LAST: + { + if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) + { + HeapEntry last_entry; + last_entry.owner.srcid = 0; #if L1_MULTI_CACHE - entry.owner.cache_id= r_read_copy_cache.read(); -#endif - entry.owner.inst = r_read_copy_inst.read(); - entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap - } - else // Entering Counter mode - { - entry.owner.srcid = 0; + last_entry.owner.cache_id = 0; +#endif + last_entry.owner.inst = false; + + if(m_heap.is_full()) + { + last_entry.next = r_read_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = r_read_next_ptr.read(); + } + m_heap.write(r_read_ptr.read(),last_entry); + r_read_fsm = READ_RSP; + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " READ_HEAP_LAST state" << std::endl; + std::cout << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + + ////////////// + case READ_RSP: // request the TGT_RSP FSM to return data + { + if( !r_read_to_tgt_rsp_req ) + { + for ( size_t i=0 ; i Request the TGT_RSP FSM to return data:" + << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; + } +#endif + } + break; + } + + /////////////////// + case READ_TRT_LOCK: // read miss : check the Transaction Table + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) + { + size_t index = 0; + vci_addr_t addr = (vci_addr_t)m_cmd_read_addr_fifo.read(); + bool hit_read = m_transaction_tab.hit_read(m_nline[addr], index); + bool hit_write = m_transaction_tab.hit_write(m_nline[addr]); + bool wok = !m_transaction_tab.full(index); + + if( hit_read || !wok || hit_write ) // missing line already requested or no space + { + if(!wok) m_cpt_trt_full++; + if(hit_read || hit_write) m_cpt_trt_rb++; + r_read_fsm = READ_IDLE; + } + else // missing line is requested to the XRAM + { + m_cpt_read_miss++; + r_read_trt_index = index; + r_read_fsm = READ_TRT_SET; + } + +#if DEBUG_MEMC_READ + if( m_debug_read_fsm ) + { + std::cout << " Check TRT:" + << " hit_read = " << hit_read + << " / hit_write = " << hit_write + << " / full = " << !wok << std::endl; + } +#endif + } + break; + } + + ////////////////// + case READ_TRT_SET: // register get transaction in TRT + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) + { + m_transaction_tab.set(r_read_trt_index.read(), + true, + m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], + m_cmd_read_srcid_fifo.read(), + m_cmd_read_trdid_fifo.read(), + m_cmd_read_pktid_fifo.read(), + true, + m_cmd_read_length_fifo.read(), + m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())], + std::vector(m_words,0), + std::vector(m_words,0)); +#if DEBUG_MEMC_READ + if( m_debug_read_fsm ) + { + std::cout << " Write in Transaction Table: " << std::hex + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() + << std::endl; + } +#endif + r_read_fsm = READ_TRT_REQ; + } + break; + } + + ////////////////// + case READ_TRT_REQ: + { + // consume the read request in the FIFO, + // and send it to the ixr_cmd_fsm + + if( not r_read_to_ixr_cmd_req ) + { + cmd_read_fifo_get = true; + r_read_to_ixr_cmd_req = true; + r_read_to_ixr_cmd_nline = m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())]; + r_read_to_ixr_cmd_trdid = r_read_trt_index.read(); + r_read_fsm = READ_IDLE; + +#if DEBUG_MEMC_READ + if( m_debug_read_fsm ) + { + std::cout + << " Request GET transaction for address " + << std::hex << m_cmd_read_addr_fifo.read() << std::endl; + } +#endif + } + break; + } + } // end switch read_fsm + + /////////////////////////////////////////////////////////////////////////////////// + // WRITE FSM + /////////////////////////////////////////////////////////////////////////////////// + // The WRITE FSM handles the write bursts sent by the processors. + // All addresses in a burst must be in the same cache line. + // A complete write burst is consumed in the FIFO & copied to a local buffer. + // Then the FSM takes the lock protecting the cache directory, to check + // if the line is in the cache. + // + // - In case of HIT, the cache is updated. + // If there is no other copy, an acknowledge response is immediately + // returned to the writing processor. + // If the data is cached by other processors, a coherence transaction must + // be launched: + // It is a multicast update if the line is not in counter mode, and the processor + // takes the lock protecting the Update Table (UPT) to register this transaction. + // It is a broadcast invalidate if the line is in counter mode. + // If the UPT is full, it releases the lock(s) and retry. Then, it sends + // a multi-update request to all owners of the line (but the writer), + // through the INIT_CMD FSM. In case of coherence transaction, the WRITE FSM + // does not respond to the writing processor, as this response will be sent by + // the INIT_RSP FSM when all update responses have been received. + // + // - In case of MISS, the WRITE FSM takes the lock protecting the transaction + // table (TRT). If a read transaction to the XRAM for this line already exists, + // it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, + // the WRITE FSM register a new transaction in TRT, and sends a read line request + // to the XRAM. If the TRT is full, it releases the lock, and waits. + // Finally, the WRITE FSM returns an aknowledge response to the writing processor. + ///////////////////////////////////////////////////////////////////////////////////// + + switch ( r_write_fsm.read() ) + { + //////////////// + case WRITE_IDLE: // copy first word of a write burst in local buffer + { + if ( m_cmd_write_addr_fifo.rok() ) + { + m_cpt_write++; + m_cpt_write_cells++; + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 1; + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_srcid = m_cmd_write_srcid_fifo.read(); + r_write_trdid = m_cmd_write_trdid_fifo.read(); + r_write_pktid = m_cmd_write_pktid_fifo.read(); + + // initialize the be field for all words + for ( size_t i=0 ; i Write request " + << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; + } +#endif + } + break; + } + + //////////////// + case WRITE_NEXT: // copy next word of a write burst in local buffer + { + if ( m_cmd_write_addr_fifo.rok() ) + { + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout << " Write another word in local buffer" + << std::endl; + } +#endif + m_cpt_write_cells++; + + // check that the next word is in the same cache line + if (( m_nline[(vci_addr_t)(r_write_address.read())] != + m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())] )) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_NEXT state" << std::endl + << "all words in a write burst must be in same cache line" << std::endl; + + exit(0); + } + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = r_write_word_index.read() + r_write_word_count.read(); + + r_write_be[index] = m_cmd_write_be_fifo.read(); + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_word_count = r_write_word_count.read() + 1; + + if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) ) + r_write_byte = true; + + if ( m_cmd_write_eop_fifo.read() ) + { + r_write_fsm = WRITE_DIR_REQ; + } + } + break; + } + + //////////////////// + case WRITE_DIR_REQ: + // Get the lock to the directory + { + if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) + { + r_write_fsm = WRITE_DIR_LOCK; + } + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout + << " Requesting DIR lock " + << std::endl; + } +#endif + + break; + } + + //////////////////// + case WRITE_DIR_LOCK: + // access directory to check hit/miss + { + if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) + { + size_t way = 0; + DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); + + if ( entry.valid ) // hit + { + // copy directory entry in local buffer in case of hit + r_write_is_cnt = entry.is_cnt; + r_write_lock = entry.lock; + r_write_tag = entry.tag; + r_write_copy = entry.owner.srcid; #if L1_MULTI_CACHE - entry.owner.cache_id= 0; -#endif - entry.owner.inst = false; - entry.ptr = 0; - } - - m_cache_directory.write(set, way, entry); - - // prepare the heap update (add an entry, or clear the linked list) - if (not go_cnt) // not switching to counter mode - { - // We test if the next free entry in the heap is the last - HeapEntry heap_entry = m_heap.next_free_entry(); - r_read_next_ptr = heap_entry.next; - r_read_last_free = ( heap_entry.next == m_heap.next_free_ptr() ); - - r_read_fsm = READ_HEAP_WRITE; // add an entry in the HEAP - } - else // switching to counter mode - { - if ( r_read_count.read()>1 ) // heap must be cleared - { - HeapEntry next_entry = m_heap.read(r_read_ptr.read()); - r_read_next_ptr = m_heap.next_free_ptr(); - m_heap.write_free_ptr(r_read_ptr.read()); - - if( next_entry.next == r_read_ptr.read() ) // last entry - { - r_read_fsm = READ_HEAP_LAST; // erase the entry - } - else // not the last entry - { - r_read_ptr = next_entry.next; - r_read_fsm = READ_HEAP_ERASE; // erase the list - } - } - else // the heap is not used / nothing to do - { - r_read_fsm = READ_RSP; - } - } - -#if DEBUG_MEMC_READ -if( m_debug_read_fsm ) -{ - std::cout << " Update directory:" - << " tag = " << std::hex << entry.tag - << " set = " << std::dec << set - << " way = " << way - << " count = " << entry.count - << " is_cnt = " << entry.is_cnt << std::endl; -} -#endif - } - break; - } - ///////////////////// - case READ_HEAP_WRITE: // add a entry in the heap - { - if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) - { - HeapEntry heap_entry; - heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + r_write_copy_cache = entry.owner.cache_id; +#endif + r_write_copy_inst = entry.owner.inst; + r_write_count = entry.count; + r_write_ptr = entry.ptr; + r_write_way = way; + + if( entry.is_cnt && entry.count ) + { + r_write_fsm = WRITE_DIR_READ; + } + else + { + if (r_write_byte.read()) + { + r_write_fsm = WRITE_DIR_READ; + } + else + { + r_write_fsm = WRITE_DIR_HIT; + } + } + } + else // miss + { + r_write_fsm = WRITE_MISS_TRT_LOCK; + } + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout << " Check the directory: " + << " address = " << std::hex << r_write_address.read() + << " hit = " << std::dec << entry.valid + << " count = " << entry.count + << " is_cnt = " << entry.is_cnt << std::endl; + } +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " WRITE_DIR_LOCK state" << std::endl + << "bad DIR allocation" << std::endl; + + exit(0); + } + + break; + } + + //////////////////// + case WRITE_DIR_READ: // read the cache and complete the buffer when be!=0xF + { + // update local buffer + size_t set = m_y[(vci_addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + for(size_t i=0 ; i Read the cache to complete local buffer" << std::endl; + } +#endif + break; + } + + /////////////////// + case WRITE_DIR_HIT: + { + // update the cache directory + // update directory with Dirty bit + DirectoryEntry entry; + entry.valid = true; + entry.dirty = true; + entry.tag = r_write_tag.read(); + entry.is_cnt = r_write_is_cnt.read(); + entry.lock = r_write_lock.read(); + entry.owner.srcid = r_write_copy.read(); #if L1_MULTI_CACHE - heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); -#endif - heap_entry.owner.inst = (m_cmd_read_trdid_fifo.read() & 0x2); - - if(r_read_count.read() == 1) // creation of a new linked list - { - heap_entry.next = m_heap.next_free_ptr(); - } - else // head insertion in existing list - { - heap_entry.next = r_read_ptr.read(); - } - m_heap.write_free_entry(heap_entry); - m_heap.write_free_ptr(r_read_next_ptr.read()); - if(r_read_last_free.read()) m_heap.set_full(); - - r_read_fsm = READ_RSP; - -#if DEBUG_MEMC_READ -if( m_debug_read_fsm ) -{ - std::cout << " Add an entry in the heap:" - << " owner_id = " << heap_entry.owner.srcid - << " owner_ins = " << heap_entry.owner.inst << std::endl; -} -#endif - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " READ_HEAP_WRITE state" << std::endl; - std::cout << "Bad HEAP allocation" << std::endl; - exit(0); - } - break; - } - ///////////////////// - case READ_HEAP_ERASE: - { - if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) - { - HeapEntry next_entry = m_heap.read(r_read_ptr.read()); - if( next_entry.next == r_read_ptr.read() ) - { - r_read_fsm = READ_HEAP_LAST; - } - else - { - r_read_ptr = next_entry.next; - r_read_fsm = READ_HEAP_ERASE; - } - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " READ_HEAP_ERASE state" << std::endl; - std::cout << "Bad HEAP allocation" << std::endl; - exit(0); - } - break; - } - //////////////////// - case READ_HEAP_LAST: - { - if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) - { - HeapEntry last_entry; - last_entry.owner.srcid = 0; + entry.owner.cache_id = r_write_copy_cache.read(); +#endif + entry.owner.inst = r_write_copy_inst.read(); + entry.count = r_write_count.read(); + entry.ptr = r_write_ptr.read(); + + size_t set = m_y[(vci_addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + // update directory + m_cache_directory.write(set, way, entry); + + // owner is true when the the first registered copy is the writer itself + bool owner = (((r_write_copy.read() == r_write_srcid.read()) #if L1_MULTI_CACHE - last_entry.owner.cache_id = 0; -#endif - last_entry.owner.inst = false; - - if(m_heap.is_full()) - { - last_entry.next = r_read_ptr.read(); - m_heap.unset_full(); - } - else - { - last_entry.next = r_read_next_ptr.read(); - } - m_heap.write(r_read_ptr.read(),last_entry); - r_read_fsm = READ_RSP; - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " READ_HEAP_LAST state" << std::endl; - std::cout << "Bad HEAP allocation" << std::endl; - exit(0); - } - break; - } - ////////////// - case READ_RSP: // request the TGT_RSP FSM to return data - { - if( !r_read_to_tgt_rsp_req ) - { - for ( size_t i=0 ; i Request the TGT_RSP FSM to return data:" - << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; -} -#endif - } - break; - } - /////////////////// - case READ_TRT_LOCK: // read miss : check the Transaction Table - { - if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) - { - size_t index = 0; - vci_addr_t addr = (vci_addr_t)m_cmd_read_addr_fifo.read(); - bool hit_read = m_transaction_tab.hit_read(m_nline[addr], index); - bool hit_write = m_transaction_tab.hit_write(m_nline[addr]); - bool wok = !m_transaction_tab.full(index); - - if( hit_read || !wok || hit_write ) // missing line already requested or no space - { - if(!wok) m_cpt_trt_full++; - if(hit_read || hit_write) m_cpt_trt_rb++; - r_read_fsm = READ_IDLE; - } - else // missing line is requested to the XRAM - { - m_cpt_read_miss++; - r_read_trt_index = index; - r_read_fsm = READ_TRT_SET; - } - -#if DEBUG_MEMC_READ -if( m_debug_read_fsm ) -{ - std::cout << " Check TRT:" - << " hit_read = " << hit_read - << " / hit_write = " << hit_write - << " / full = " << !wok << std::endl; -} -#endif - } - break; - } - ////////////////// - case READ_TRT_SET: // register get transaction in TRT - { - if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) - { - m_transaction_tab.set(r_read_trt_index.read(), - true, - m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], - m_cmd_read_srcid_fifo.read(), - m_cmd_read_trdid_fifo.read(), - m_cmd_read_pktid_fifo.read(), - true, - m_cmd_read_length_fifo.read(), - m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())], - std::vector(m_words,0), - std::vector(m_words,0)); -#if DEBUG_MEMC_READ -if( m_debug_read_fsm ) -{ - std::cout << " Write in Transaction Table: " << std::hex - << " address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() - << std::endl; -} -#endif - r_read_fsm = READ_TRT_REQ; - } - break; - } - ////////////////// - case READ_TRT_REQ: // consume the read request in the FIFO, - // and send it to the ixr_cmd_fsm - { - if( not r_read_to_ixr_cmd_req ) - { - cmd_read_fifo_get = true; - r_read_to_ixr_cmd_req = true; - r_read_to_ixr_cmd_nline = m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())]; - r_read_to_ixr_cmd_trdid = r_read_trt_index.read(); - r_read_fsm = READ_IDLE; - -#if DEBUG_MEMC_READ -if( m_debug_read_fsm ) -{ - std::cout << " Request GET transaction for address " - << std::hex << m_cmd_read_addr_fifo.read() << std::endl; -} -#endif - } - break; - } - } // end switch read_fsm - - /////////////////////////////////////////////////////////////////////////////////// - // WRITE FSM - /////////////////////////////////////////////////////////////////////////////////// - // The WRITE FSM handles the write bursts sent by the processors. - // All addresses in a burst must be in the same cache line. - // A complete write burst is consumed in the FIFO & copied to a local buffer. - // Then the FSM takes the lock protecting the cache directory, to check - // if the line is in the cache. - // - // - In case of HIT, the cache is updated. - // If there is no other copy, an acknowledge response is immediately - // returned to the writing processor. - // If the data is cached by other processors, a coherence transaction must - // be launched: - // It is a multicast update if the line is not in counter mode, and the processor - // takes the lock protecting the Update Table (UPT) to register this transaction. - // It is a broadcast invalidate if the line is in counter mode. - // If the UPT is full, it releases the lock(s) and retry. Then, it sends - // a multi-update request to all owners of the line (but the writer), - // through the INIT_CMD FSM. In case of coherence transaction, the WRITE FSM - // does not respond to the writing processor, as this response will be sent by - // the INIT_RSP FSM when all update responses have been received. - // - // - In case of MISS, the WRITE FSM takes the lock protecting the transaction - // table (TRT). If a read transaction to the XRAM for this line already exists, - // it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, - // the WRITE FSM register a new transaction in TRT, and sends a read line request - // to the XRAM. If the TRT is full, it releases the lock, and waits. - // Finally, the WRITE FSM returns an aknowledge response to the writing processor. - ///////////////////////////////////////////////////////////////////////////////////// - - switch ( r_write_fsm.read() ) + and (r_write_copy_cache.read()==r_write_pktid.read()) +#endif + ) and not r_write_copy_inst.read()); + + // no_update is true when there is no need for coherence transaction + bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1)); + + // write data in the cache if no coherence transaction + if( no_update ) + { + for(size_t i=0 ; i Write into cache / No coherence transaction" + << std::endl; + } + else + { + std::cout << " Coherence update required:" + << " is_cnt = " << r_write_is_cnt.read() + << " nb_copies = " << std::dec << r_write_count.read() << std::endl; + if (owner) + std::cout << " ... but the first copy is the writer" << std::endl; + } + } +#endif + break; + } + + //////////////////// + case WRITE_UPT_LOCK: // Try to register the update request in UPT { - //////////////// - case WRITE_IDLE: // copy first word of a write burst in local buffer - { - if ( m_cmd_write_addr_fifo.rok() ) - { - m_cpt_write++; - m_cpt_write_cells++; - - // consume a word in the FIFO & write it in the local buffer - cmd_write_fifo_get = true; - size_t index = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())]; - - r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); - r_write_word_index = index; - r_write_word_count = 1; - r_write_data[index] = m_cmd_write_data_fifo.read(); - r_write_srcid = m_cmd_write_srcid_fifo.read(); - r_write_trdid = m_cmd_write_trdid_fifo.read(); - r_write_pktid = m_cmd_write_pktid_fifo.read(); - - // initialize the be field for all words - for ( size_t i=0 ; i Write request " + if( m_debug_write_fsm ) + { + if ( wok ) + { + std::cout << " Register the multicast update in UPT / " + << " nb_copies = " << r_write_count.read() << std::endl; + } + } +#endif + r_write_upt_index = index; + // releases the lock protecting UPT and the DIR if no entry... + if ( wok ) r_write_fsm = WRITE_UPT_HEAP_LOCK; + else r_write_fsm = WRITE_WAIT; + } + break; + } + + ///////////////////////// + case WRITE_UPT_HEAP_LOCK: // get access to heap + { + if( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE ) + { + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout << " Get acces to the HEAP" << std::endl; + } +#endif + r_write_fsm = WRITE_UPT_REQ; + } + break; + } + + ////////////////// + case WRITE_UPT_REQ: + { + // prepare the coherence ransaction for the INIT_CMD FSM + // and write the first copy in the FIFO + // send the request if only one copy + + if( !r_write_to_init_cmd_multi_req.read() && + !r_write_to_init_cmd_brdcast_req.read() ) // no pending coherence request + { + r_write_to_init_cmd_brdcast_req = false; + r_write_to_init_cmd_trdid = r_write_upt_index.read(); + r_write_to_init_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())]; + r_write_to_init_cmd_index = r_write_word_index.read(); + r_write_to_init_cmd_count = r_write_word_count.read(); + + for(size_t i=0; i Post first request to INIT_CMD FSM" + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if ( r_write_count.read() == 1) + std::cout << " ... and this is the last" << std::endl; + } +#endif + } + break; + } + + /////////////////// + case WRITE_UPT_NEXT: + { + // continue the multi-update request to INIT_CMD fsm + // when there is copies in the heap. + // if one copy in the heap is the writer itself + // the corresponding SRCID should not be written in the fifo, + // but the UPT counter must be decremented. + // As this decrement is done in the WRITE_UPT_DEC state, + // after the last copy has been found, the decrement request + // must be registered in the r_write_to_dec flip-flop. + + HeapEntry entry = m_heap.read(r_write_ptr.read()); + + bool dec_upt_counter; + + if( (entry.owner.srcid != r_write_srcid.read()) or +#if L1_MULTI_CACHE + (entry.owner.cache_id != r_write_pktid.read()) or +#endif + entry.owner.inst) // put te next srcid in the fifo + { + dec_upt_counter = false; + write_to_init_cmd_fifo_put = true; + write_to_init_cmd_fifo_inst = entry.owner.inst; + write_to_init_cmd_fifo_srcid = entry.owner.srcid; +#if L1_MULTI_CACHE + write_to_init_cmd_fifo_cache_id = entry.owner.cache_id; +#endif + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout << " Post another request to INIT_CMD FSM" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if( entry.next == r_write_ptr.read() ) + std::cout << " ... and this is the last" << std::endl; + } +#endif + } + else // the UPT counter must be decremented + { + dec_upt_counter = true; + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout << " Skip one entry in heap matching the writer" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if( entry.next == r_write_ptr.read() ) + std::cout << " ... and this is the last" << std::endl; + } +#endif + } + + // register the possible UPT decrement request + r_write_to_dec = dec_upt_counter or r_write_to_dec.read(); + + if( not m_write_to_init_cmd_inst_fifo.wok() ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl + << "The write_to_init_cmd_fifo should not be full" << std::endl + << "as the depth should be larger than the max number of copies" << std::endl; + exit(0); + } + + r_write_ptr = entry.next; + + if( entry.next == r_write_ptr.read() ) // last copy + { + r_write_to_init_cmd_multi_req = true; + if( r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; + else r_write_fsm = WRITE_IDLE; + } + break; + } + + ////////////////// + case WRITE_UPT_DEC: + { + // If the initial writer has a copy, it should not + // receive an update request, but the counter in the + // update table must be decremented by the INIT_RSP FSM. + + if ( !r_write_to_init_rsp_req.read() ) + { + r_write_to_init_rsp_req = true; + r_write_to_init_rsp_upt_index = r_write_upt_index.read(); + r_write_fsm = WRITE_IDLE; + } + break; + } + + /////////////// + case WRITE_RSP: + { + // Post a request to TGT_RSP FSM to acknowledge the write + // In order to increase the Write requests throughput, + // we don't wait to return in the IDLE state to consume + // a new request in the write FIFO + + if ( !r_write_to_tgt_rsp_req.read() ) + { + // post the request to TGT_RSP_FSM + r_write_to_tgt_rsp_req = true; + r_write_to_tgt_rsp_srcid = r_write_srcid.read(); + r_write_to_tgt_rsp_trdid = r_write_trdid.read(); + r_write_to_tgt_rsp_pktid = r_write_pktid.read(); + + // try to get a new write request from the FIFO + if ( m_cmd_write_addr_fifo.rok() ) + { + m_cpt_write++; + m_cpt_write_cells++; + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 1; + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_srcid = m_cmd_write_srcid_fifo.read(); + r_write_trdid = m_cmd_write_trdid_fifo.read(); + r_write_pktid = m_cmd_write_pktid_fifo.read(); + + // initialize the be field for all words + for ( size_t i=0 ; i Post a request to TGT_RSP FSM: rsrcid = " + << std::dec << r_write_srcid.read() << std::endl; + if ( m_cmd_write_addr_fifo.rok() ) + { + std::cout << " New Write request: " << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_write_addr_fifo.read() + << " / address = " << std::hex << m_cmd_write_addr_fifo.read() << " / data = " << m_cmd_write_data_fifo.read() << std::endl; -} -#endif - } - break; - } - //////////////// - case WRITE_NEXT: // copy next word of a write burst in local buffer - { - if ( m_cmd_write_addr_fifo.rok() ) - { + } + } +#endif + } + break; + } + + ///////////////////////// + case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) + { #if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Write another word in local buffer" << std::endl; -} -#endif - m_cpt_write_cells++; - - // check that the next word is in the same cache line - if ( (m_nline[(vci_addr_t)(r_write_address.read())] != - m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())]) ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_NEXT state" << std::endl; - std::cout << "all words in a write burst must be in same cache line" << std::endl; - exit(0); - } - - // consume a word in the FIFO & write it in the local buffer - cmd_write_fifo_get=true; - size_t index = r_write_word_index.read() + r_write_word_count.read(); - - r_write_be[index] = m_cmd_write_be_fifo.read(); - r_write_data[index] = m_cmd_write_data_fifo.read(); - r_write_word_count = r_write_word_count.read() + 1; - - if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) ) - r_write_byte = true; - - if ( m_cmd_write_eop_fifo.read() ) r_write_fsm = WRITE_DIR_LOCK; - } - break; - } - //////////////////// - case WRITE_DIR_LOCK: // access directory to check hit/miss - { - if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) - { - size_t way = 0; - DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); - - if ( entry.valid ) // hit - { - // copy directory entry in local buffer in case of hit - r_write_is_cnt = entry.is_cnt; - r_write_lock = entry.lock; - r_write_tag = entry.tag; - r_write_copy = entry.owner.srcid; + if( m_debug_write_fsm ) + { + std::cout << " Check the TRT" << std::endl; + } +#endif + size_t hit_index = 0; + size_t wok_index = 0; + vci_addr_t addr = (vci_addr_t)r_write_address.read(); + bool hit_read = m_transaction_tab.hit_read(m_nline[addr], hit_index); + bool hit_write = m_transaction_tab.hit_write(m_nline[addr]); + bool wok = !m_transaction_tab.full(wok_index); + + if ( hit_read ) // register the modified data in TRT + { + r_write_trt_index = hit_index; + r_write_fsm = WRITE_MISS_TRT_DATA; + m_cpt_write_miss++; + } + else if ( wok && !hit_write ) // set a new entry in TRT + { + r_write_trt_index = wok_index; + r_write_fsm = WRITE_MISS_TRT_SET; + m_cpt_write_miss++; + } + else // wait an empty entry in TRT + { + r_write_fsm = WRITE_WAIT; + m_cpt_trt_full++; + } + } + break; + } + + //////////////// + case WRITE_WAIT: // release the locks protecting the shared ressources + { +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout << " Releases the locks before retry" << std::endl; + } +#endif + r_write_fsm = WRITE_DIR_REQ; + break; + } + + //////////////////////// + case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) + { + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for ( size_t i=0; i Set a new entry in TRT" << std::endl; + } +#endif + } + break; + } + + ///////////////////////// + case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) + { + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for ( size_t i=0; i Modify an existing entry in TRT" << std::endl; + m_transaction_tab.print( r_write_trt_index.read() ); + } +#endif + } + break; + } + + ///////////////////////// + case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM + { + if ( !r_write_to_ixr_cmd_req ) + { + r_write_to_ixr_cmd_req = true; + r_write_to_ixr_cmd_write = false; + r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())]; + r_write_to_ixr_cmd_trdid = r_write_trt_index.read(); + r_write_fsm = WRITE_RSP; + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout << " Post a GET request to the IXR_CMD FSM" << std::endl; + } +#endif + } + break; + } + + /////////////////////// + case WRITE_BC_TRT_LOCK: // Check TRT not full + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) + { + size_t wok_index = 0; + bool wok = !m_transaction_tab.full( wok_index ); + if ( wok ) // set a new entry in TRT + { + r_write_trt_index = wok_index; + r_write_fsm = WRITE_BC_UPT_LOCK; + } + else // wait an empty entry in TRT + { + r_write_fsm = WRITE_WAIT; + } + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + std::cout << " Check TRT : wok = " + << wok << " / index = " << wok_index << std::endl; + } +#endif + } + break; + } + + ////////////////////// + case WRITE_BC_UPT_LOCK: // register BC transaction in UPT + { + if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_write_srcid.read(); + size_t trdid = r_write_trdid.read(); + size_t pktid = r_write_pktid.read(); + addr_t nline = m_nline[(vci_addr_t)(r_write_address.read())]; + size_t nb_copies = r_write_count.read(); + + wok =m_update_tab.set(false, // it's an inval transaction + true, // it's a broadcast + true, // it needs a response + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + +#if DEBUG_MEMC_WRITE + if( m_debug_write_fsm ) + { + if ( wok ) + { + std::cout << " Register the broadcast inval in UPT / " + << " nb_copies = " << r_write_count.read() << std::endl; + } + } +#endif + r_write_upt_index = index; + + if ( wok ) r_write_fsm = WRITE_BC_DIR_INVAL; + else r_write_fsm = WRITE_WAIT; + } + break; + } + + //////////////////////// + case WRITE_BC_DIR_INVAL: + { + // Register a put transaction to XRAM in TRT + // and invalidate the line in directory + if ( (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE ) || + (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE ) || + (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; + std::cout << "bad TRT, DIR, or UPT allocation" << std::endl; + exit(0); + } + + // register a write request to XRAM in TRT + m_transaction_tab.set(r_write_trt_index.read(), + false, // write request to XRAM + m_nline[(vci_addr_t)(r_write_address.read())], + 0, + 0, + 0, + false, // not a processor read + 0, // not a single word + 0, // word index + std::vector(m_words,0), + std::vector(m_words,0)); + + // invalidate directory entry + DirectoryEntry entry; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; + entry.is_cnt = false; + entry.lock = false; + entry.owner.srcid = 0; #if L1_MULTI_CACHE - r_write_copy_cache = entry.owner.cache_id; -#endif - r_write_copy_inst = entry.owner.inst; - r_write_count = entry.count; - r_write_ptr = entry.ptr; - r_write_way = way; - - if( entry.is_cnt && entry.count ) - { - r_write_fsm = WRITE_DIR_READ; - } - else - { - if (r_write_byte.read()) r_write_fsm = WRITE_DIR_READ; - else r_write_fsm = WRITE_DIR_HIT; - } - } - else // miss - { - r_write_fsm = WRITE_MISS_TRT_LOCK; - } + entry.owner.cache_id= 0; +#endif + entry.owner.inst = false; + entry.ptr = 0; + entry.count = 0; + size_t set = m_y[(vci_addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + m_cache_directory.write(set, way, entry); #if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Check the directory: " - << " address = " << std::hex << r_write_address.read() - << " hit = " << std::dec << entry.valid - << " count = " << entry.count - << " is_cnt = " << entry.is_cnt << std::endl; -} -#endif - } - break; - } - //////////////////// - case WRITE_DIR_READ: // read the cache and complete the buffer when be!=0xF - { - // update local buffer - size_t set = m_y[(vci_addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - for(size_t i=0 ; i Invalidate the directory entry: @ = " + << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; + } +#endif + r_write_fsm = WRITE_BC_CC_SEND; + break; + } + + ////////////////////// + case WRITE_BC_CC_SEND: // Post a coherence broadcast request to INIT_CMD FSM + { + if ( !r_write_to_init_cmd_multi_req.read() && !r_write_to_init_cmd_brdcast_req.read() ) + { + r_write_to_init_cmd_multi_req = false; + r_write_to_init_cmd_brdcast_req = true; + r_write_to_init_cmd_trdid = r_write_upt_index.read(); + r_write_to_init_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())]; + r_write_to_init_cmd_index = 0; + r_write_to_init_cmd_count = 0; + + for(size_t i=0; i Read the cache to complete local buffer" << std::endl; -} -#endif - break; - } - /////////////////// - case WRITE_DIR_HIT: // update the cache directory - { - // update directory with Dirty bit - DirectoryEntry entry; - entry.valid = true; - entry.dirty = true; - entry.tag = r_write_tag.read(); - entry.is_cnt = r_write_is_cnt.read(); - entry.lock = r_write_lock.read(); - entry.owner.srcid = r_write_copy.read(); -#if L1_MULTI_CACHE - entry.owner.cache_id = r_write_copy_cache.read(); -#endif - entry.owner.inst = r_write_copy_inst.read(); - entry.count = r_write_count.read(); - entry.ptr = r_write_ptr.read(); - size_t set = m_y[(vci_addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - // update directory - m_cache_directory.write(set, way, entry); - - // owner is true when the the first registered copy is the writer itself - bool owner = (((r_write_copy.read() == r_write_srcid.read()) -#if L1_MULTI_CACHE - and (r_write_copy_cache.read()==r_write_pktid.read()) -#endif - ) and not r_write_copy_inst.read()); - - // no_update is true when there is no need for coherence transaction - bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1)); - - // write data in the cache if no coherence transaction - if( no_update ) - { - for(size_t i=0 ; i Post a broadcast request to INIT_CMD FSM" << std::endl; + } +#endif + } + break; + } + + /////////////////////// + case WRITE_BC_XRAM_REQ: // Post a put request to IXR_CMD FSM + { + if ( !r_write_to_ixr_cmd_req ) + { + r_write_to_ixr_cmd_req = true; + r_write_to_ixr_cmd_write = true; + r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())]; + r_write_to_ixr_cmd_trdid = r_write_trt_index.read(); + + for(size_t i=0; i Write into cache / No coherence transaction" - << std::endl; + if( m_debug_write_fsm ) + { + std::cout << " Post a put request to IXR_CMD FSM" << std::endl; + } +#endif + } + break; } - else - { - std::cout << " Coherence update required:" - << " is_cnt = " << r_write_is_cnt.read() - << " nb_copies = " << std::dec << r_write_count.read() << std::endl; - if (owner) - std::cout << " ... but the first copy is the writer" << std::endl; - } -} -#endif - break; - } - //////////////////// - case WRITE_UPT_LOCK: // Try to register the update request in UPT - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) - { - bool wok = false; - size_t index = 0; - size_t srcid = r_write_srcid.read(); - size_t trdid = r_write_trdid.read(); - size_t pktid = r_write_pktid.read(); - addr_t nline = m_nline[(vci_addr_t)(r_write_address.read())]; - size_t nb_copies = r_write_count.read(); - size_t set = m_y[(vci_addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - wok = m_update_tab.set(true, // it's an update transaction - false, // it's not a broadcast - true, // it needs a response - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - if ( wok ) // write data in cache - { - for(size_t i=0 ; i Register the multicast update in UPT / " - << " nb_copies = " << r_write_count.read() << std::endl; - } -} -#endif - r_write_upt_index = index; - // releases the lock protecting UPT and the DIR if no entry... - if ( wok ) r_write_fsm = WRITE_UPT_HEAP_LOCK; - else r_write_fsm = WRITE_WAIT; - } - break; - } - ///////////////////////// - case WRITE_UPT_HEAP_LOCK: // get access to heap - { - if( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE ) - { - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Get acces to the HEAP" << std::endl; -} -#endif - r_write_fsm = WRITE_UPT_REQ; - } - break; - } - ////////////////// - case WRITE_UPT_REQ: // prepare the coherence ransaction for the INIT_CMD FSM - // and write the first copy in the FIFO - // send the request if only one copy - { - if( !r_write_to_init_cmd_multi_req.read() && - !r_write_to_init_cmd_brdcast_req.read() ) // no pending coherence request - { - r_write_to_init_cmd_brdcast_req = false; - r_write_to_init_cmd_trdid = r_write_upt_index.read(); - r_write_to_init_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())]; - r_write_to_init_cmd_index = r_write_word_index.read(); - r_write_to_init_cmd_count = r_write_word_count.read(); - - for(size_t i=0; i Post first request to INIT_CMD FSM" - << " / srcid = " << std::dec << r_write_copy.read() - << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; - if ( r_write_count.read() == 1) - std::cout << " ... and this is the last" << std::endl; -} -#endif - } - break; - } - /////////////////// - case WRITE_UPT_NEXT: // continue the multi-update request to INIT_CMD fsm - // when there is copies in the heap. - // if one copy in the heap is the writer itself - // the corresponding SRCID should not be written in the fifo, - // but the UPT counter must be decremented. - // As this decrement is done in the WRITE_UPT_DEC state, - // after the last copy has been found, the decrement request - // must be registered in the r_write_to_dec flip-flop. - { - HeapEntry entry = m_heap.read(r_write_ptr.read()); - - bool dec_upt_counter; - - if( (entry.owner.srcid != r_write_srcid.read()) or -#if L1_MULTI_CACHE - (entry.owner.cache_id != r_write_pktid.read()) or -#endif - entry.owner.inst) // put te next srcid in the fifo - { - dec_upt_counter = false; - write_to_init_cmd_fifo_put = true; - write_to_init_cmd_fifo_inst = entry.owner.inst; - write_to_init_cmd_fifo_srcid = entry.owner.srcid; -#if L1_MULTI_CACHE - write_to_init_cmd_fifo_cache_id = entry.owner.cache_id; -#endif - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Post another request to INIT_CMD FSM" - << " / heap_index = " << std::dec << r_write_ptr.read() - << " / srcid = " << std::dec << r_write_copy.read() - << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; - if( entry.next == r_write_ptr.read() ) - std::cout << " ... and this is the last" << std::endl; -} -#endif - } - else // the UPT counter must be decremented - { - dec_upt_counter = true; - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Skip one entry in heap matching the writer" - << " / heap_index = " << std::dec << r_write_ptr.read() - << " / srcid = " << std::dec << r_write_copy.read() - << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; - if( entry.next == r_write_ptr.read() ) - std::cout << " ... and this is the last" << std::endl; -} -#endif - } - - // register the possible UPT decrement request - r_write_to_dec = dec_upt_counter or r_write_to_dec.read(); - - if( not m_write_to_init_cmd_inst_fifo.wok() ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl - << "The write_to_init_cmd_fifo should not be full" << std::endl - << "as the depth should be larger than the max number of copies" << std::endl; - exit(0); - } - - r_write_ptr = entry.next; - - if( entry.next == r_write_ptr.read() ) // last copy - { - r_write_to_init_cmd_multi_req = true; - if( r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; - else r_write_fsm = WRITE_IDLE; - } - break; - } - ////////////////// - case WRITE_UPT_DEC: // If the initial writer has a copy, it should not - // receive an update request, but the counter in the - // update table must be decremented by the INIT_RSP FSM. - { - if ( !r_write_to_init_rsp_req.read() ) - { - r_write_to_init_rsp_req = true; - r_write_to_init_rsp_upt_index = r_write_upt_index.read(); - r_write_fsm = WRITE_IDLE; - } - break; - } - /////////////// - case WRITE_RSP: // Post a request to TGT_RSP FSM to acknowledge the write - // In order to increase the Write requests throughput, - // we don't wait to return in the IDLE state to consume - // a new request in the write FIFO - { - if ( !r_write_to_tgt_rsp_req.read() ) - { - // post the request to TGT_RSP_FSM - r_write_to_tgt_rsp_req = true; - r_write_to_tgt_rsp_srcid = r_write_srcid.read(); - r_write_to_tgt_rsp_trdid = r_write_trdid.read(); - r_write_to_tgt_rsp_pktid = r_write_pktid.read(); - - // try to get a new write request from the FIFO - if ( m_cmd_write_addr_fifo.rok() ) - { - m_cpt_write++; - m_cpt_write_cells++; - - // consume a word in the FIFO & write it in the local buffer - cmd_write_fifo_get = true; - size_t index = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())]; - - r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); - r_write_word_index = index; - r_write_word_count = 1; - r_write_data[index] = m_cmd_write_data_fifo.read(); - r_write_srcid = m_cmd_write_srcid_fifo.read(); - r_write_trdid = m_cmd_write_trdid_fifo.read(); - r_write_pktid = m_cmd_write_pktid_fifo.read(); - - // initialize the be field for all words - for ( size_t i=0 ; i Post a request to TGT_RSP FSM: rsrcid = " - << std::dec << r_write_srcid.read() << std::endl; - if ( m_cmd_write_addr_fifo.rok() ) - { - std::cout << " New Write request: " - << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_write_addr_fifo.read() - << " / data = " << m_cmd_write_data_fifo.read() << std::endl; - } -} -#endif - } - break; - } - ///////////////////////// - case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table - { - if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) - { - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Check the TRT" << std::endl; -} -#endif - size_t hit_index = 0; - size_t wok_index = 0; - vci_addr_t addr = (vci_addr_t)r_write_address.read(); - bool hit_read = m_transaction_tab.hit_read(m_nline[addr], hit_index); - bool hit_write = m_transaction_tab.hit_write(m_nline[addr]); - bool wok = !m_transaction_tab.full(wok_index); - - if ( hit_read ) // register the modified data in TRT - { - r_write_trt_index = hit_index; - r_write_fsm = WRITE_MISS_TRT_DATA; - m_cpt_write_miss++; - } - else if ( wok && !hit_write ) // set a new entry in TRT - { - r_write_trt_index = wok_index; - r_write_fsm = WRITE_MISS_TRT_SET; - m_cpt_write_miss++; - } - else // wait an empty entry in TRT - { - r_write_fsm = WRITE_WAIT; - m_cpt_trt_full++; - } - } - break; - } - //////////////// - case WRITE_WAIT: // release the locks protecting the shared ressources - { - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Releases the locks before retry" << std::endl; -} -#endif - r_write_fsm = WRITE_DIR_LOCK; - break; - } - //////////////////////// - case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) - { - if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) - { - std::vector be_vector; - std::vector data_vector; - be_vector.clear(); - data_vector.clear(); - for ( size_t i=0; i Set a new entry in TRT" << std::endl; -} -#endif - } - break; - } - ///////////////////////// - case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) - { - if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) - { - std::vector be_vector; - std::vector data_vector; - be_vector.clear(); - data_vector.clear(); - for ( size_t i=0; i Modify an existing entry in TRT" << std::endl; - m_transaction_tab.print( r_write_trt_index.read() ); -} -#endif - } - break; - } - ///////////////////////// - case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM - { - if ( !r_write_to_ixr_cmd_req ) - { - r_write_to_ixr_cmd_req = true; - r_write_to_ixr_cmd_write = false; - r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())]; - r_write_to_ixr_cmd_trdid = r_write_trt_index.read(); - r_write_fsm = WRITE_RSP; - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Post a GET request to the IXR_CMD FSM" << std::endl; -} -#endif - } - break; - } - /////////////////////// - case WRITE_BC_TRT_LOCK: // Check TRT not full - { - if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) - { - size_t wok_index = 0; - bool wok = !m_transaction_tab.full( wok_index ); - if ( wok ) // set a new entry in TRT - { - r_write_trt_index = wok_index; - r_write_fsm = WRITE_BC_UPT_LOCK; - } - else // wait an empty entry in TRT - { - r_write_fsm = WRITE_WAIT; - } - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Check TRT : wok = " - << wok << " / index = " << wok_index << std::endl; -} -#endif - } - break; - } - ////////////////////// - case WRITE_BC_UPT_LOCK: // register BC transaction in UPT - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) - { - bool wok = false; - size_t index = 0; - size_t srcid = r_write_srcid.read(); - size_t trdid = r_write_trdid.read(); - size_t pktid = r_write_pktid.read(); - addr_t nline = m_nline[(vci_addr_t)(r_write_address.read())]; - size_t nb_copies = r_write_count.read(); - - wok =m_update_tab.set(false, // it's an inval transaction - true, // it's a broadcast - true, // it needs a response - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - if ( wok ) - { - std::cout << " Register the broadcast inval in UPT / " - << " nb_copies = " << r_write_count.read() << std::endl; - } -} -#endif - r_write_upt_index = index; - - if ( wok ) r_write_fsm = WRITE_BC_DIR_INVAL; - else r_write_fsm = WRITE_WAIT; - } - break; - } - //////////////////////// - case WRITE_BC_DIR_INVAL: // Register a put transaction to XRAM in TRT - // and invalidate the line in directory - { - if ( (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE ) || - (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE ) || - (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; - std::cout << "bad TRT, DIR, or UPT allocation" << std::endl; - exit(0); - } - - // register a write request to XRAM in TRT - m_transaction_tab.set(r_write_trt_index.read(), - false, // write request to XRAM - m_nline[(vci_addr_t)(r_write_address.read())], - 0, - 0, - 0, - false, // not a processor read - 0, // not a single word - 0, // word index - std::vector(m_words,0), - std::vector(m_words,0)); - // invalidate directory entry - DirectoryEntry entry; - entry.valid = false; - entry.dirty = false; - entry.tag = 0; - entry.is_cnt = false; - entry.lock = false; - entry.owner.srcid = 0; -#if L1_MULTI_CACHE - entry.owner.cache_id= 0; -#endif - entry.owner.inst = false; - entry.ptr = 0; - entry.count = 0; - size_t set = m_y[(vci_addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - m_cache_directory.write(set, way, entry); - -#if DEBUG_MEMC_WRITE -if( m_debug_write_fsm ) -{ - std::cout << " Invalidate the directory entry: @ = " - << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; -} -#endif - r_write_fsm = WRITE_BC_CC_SEND; - break; - } - ////////////////////// - case WRITE_BC_CC_SEND: // Post a coherence broadcast request to INIT_CMD FSM - { - if ( !r_write_to_init_cmd_multi_req.read() && !r_write_to_init_cmd_brdcast_req.read() ) - { - r_write_to_init_cmd_multi_req = false; - r_write_to_init_cmd_brdcast_req = true; - r_write_to_init_cmd_trdid = r_write_upt_index.read(); - r_write_to_init_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())]; - r_write_to_init_cmd_index = 0; - r_write_to_init_cmd_count = 0; - - for(size_t i=0; i Post a broadcast request to INIT_CMD FSM" << std::endl; -} -#endif - } - break; - } - /////////////////////// - case WRITE_BC_XRAM_REQ: // Post a put request to IXR_CMD FSM - { - if ( !r_write_to_ixr_cmd_req ) - { - r_write_to_ixr_cmd_req = true; - r_write_to_ixr_cmd_write = true; - r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())]; - r_write_to_ixr_cmd_trdid = r_write_trt_index.read(); - - for(size_t i=0; i Post a put request to IXR_CMD FSM" << std::endl; -} -#endif - } - break; - } - } // end switch r_write_fsm + } // end switch r_write_fsm /////////////////////////////////////////////////////////////////////// - // IXR_CMD FSM + // IXR_CMD FSM /////////////////////////////////////////////////////////////////////// // The IXR_CMD fsm controls the command packets to the XRAM : // - It sends a single cell VCI read request to the XRAM in case of MISS - // posted by the READ, WRITE or SC FSMs : the TRDID field contains + // posted by the READ, WRITE or SC FSMs : the TRDID field contains // the Transaction Tab index. // The VCI response is a multi-cell packet : the N cells contain // the N data words. // - It sends a multi-cell VCI write when the XRAM_RSP FSM, WRITE FSM - // or SC FSM request to save a dirty line to the XRAM. + // or SC FSM request to save a dirty line to the XRAM. // The VCI response is a single cell packet. - // This FSM handles requests from the READ, WRITE, SC & XRAM_RSP FSMs + // This FSM handles requests from the READ, WRITE, SC & XRAM_RSP FSMs // with a round-robin priority. //////////////////////////////////////////////////////////////////////// - switch ( r_ixr_cmd_fsm.read() ) + switch ( r_ixr_cmd_fsm.read() ) { - //////////////////////// + //////////////////////// case IXR_CMD_READ_IDLE: if ( r_write_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; @@ -2483,5 +2707,5 @@ else if ( r_read_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; break; - //////////////////////// + //////////////////////// case IXR_CMD_WRITE_IDLE: if ( r_sc_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_SC_NLINE; @@ -2490,5 +2714,5 @@ else if ( r_write_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; break; - //////////////////////// + //////////////////////// case IXR_CMD_SC_IDLE: if ( r_xram_rsp_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; @@ -2497,5 +2721,5 @@ else if ( r_sc_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_SC_NLINE; break; - //////////////////////// + //////////////////////// case IXR_CMD_XRAM_IDLE: if ( r_read_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; @@ -2506,7 +2730,7 @@ ///////////////////////// // send a get request to XRAM case IXR_CMD_READ_NLINE: - if ( p_vci_ixr.cmdack ) - { - r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + if ( p_vci_ixr.cmdack ) + { + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; r_read_to_ixr_cmd_req = false; @@ -2520,16 +2744,16 @@ break; ////////////////////////// - case IXR_CMD_WRITE_NLINE: // send a put or get command to XRAM - if ( p_vci_ixr.cmdack ) + case IXR_CMD_WRITE_NLINE: // send a put or get command to XRAM + if ( p_vci_ixr.cmdack ) { if( r_write_to_ixr_cmd_write.read()) { - if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) + if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) { r_ixr_cmd_cpt = 0; r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; r_write_to_ixr_cmd_req = false; - } - else + } + else { r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1; @@ -2542,8 +2766,8 @@ } #endif - } - else - { - r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + } + else + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; r_write_to_ixr_cmd_req = false; @@ -2559,15 +2783,15 @@ ////////////////////// case IXR_CMD_SC_NLINE: // send a put or get command to XRAM - if ( p_vci_ixr.cmdack ) + if ( p_vci_ixr.cmdack ) { if( r_sc_to_ixr_cmd_write.read()) { - if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) + if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) { r_ixr_cmd_cpt = 0; r_ixr_cmd_fsm = IXR_CMD_SC_IDLE; r_sc_to_ixr_cmd_req = false; - } - else + } + else { r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1; @@ -2580,8 +2804,8 @@ } #endif - } - else - { - r_ixr_cmd_fsm = IXR_CMD_SC_IDLE; + } + else + { + r_ixr_cmd_fsm = IXR_CMD_SC_IDLE; r_sc_to_ixr_cmd_req = false; @@ -2597,13 +2821,13 @@ //////////////////////// case IXR_CMD_XRAM_DATA: // send a put command to XRAM - if ( p_vci_ixr.cmdack ) - { - if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) + if ( p_vci_ixr.cmdack ) + { + if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) { r_ixr_cmd_cpt = 0; r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; r_xram_rsp_to_ixr_cmd_req = false; - } - else + } + else { r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1; @@ -2631,5 +2855,5 @@ // The FSM takes the lock protecting the TRT, and the corresponding // entry is erased. - // + // // - A response to a get request is a multi-cell VCI packet. // The Transaction Tab index is contained in the RTRDID field. @@ -2640,10 +2864,10 @@ /////////////////////////////////////////////////////////////////////////////// - switch ( r_ixr_rsp_fsm.read() ) + switch ( r_ixr_rsp_fsm.read() ) { ////////////////// - case IXR_RSP_IDLE: // test if it's a get or a put transaction - { - if ( p_vci_ixr.rspval.read() ) + case IXR_RSP_IDLE: // test if it's a get or a put transaction + { + if ( p_vci_ixr.rspval.read() ) { r_ixr_rsp_cpt = 0; @@ -2654,72 +2878,72 @@ #if DEBUG_MEMC_IXR_RSP -if( m_debug_ixr_rsp_fsm ) +if( m_debug_ixr_rsp_fsm ) { - std::cout << " Response from XRAM to a put transaction" << std::endl; + std::cout << " Response from XRAM to a put transaction" << std::endl; } #endif } - else // get transaction + else // get transaction { - r_ixr_rsp_fsm = IXR_RSP_TRT_READ; - -#if DEBUG_MEMC_IXR_RSP -if( m_debug_ixr_rsp_fsm ) -{ - std::cout << " Response from XRAM to a get transaction" << std::endl; -} -#endif - } - } - break; - } - //////////////////////// - case IXR_RSP_ACK: // Aknowledge the VCI response - { - if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; - -#if DEBUG_MEMC_IXR_RSP -if( m_debug_ixr_rsp_fsm ) -{ - std::cout << " " << std::endl; -} -#endif - break; - } - //////////////////////// - case IXR_RSP_TRT_ERASE: // erase the entry in the TRT - { - if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP ) - { - m_transaction_tab.erase(r_ixr_rsp_trt_index.read()); - r_ixr_rsp_fsm = IXR_RSP_IDLE; + r_ixr_rsp_fsm = IXR_RSP_TRT_READ; #if DEBUG_MEMC_IXR_RSP if( m_debug_ixr_rsp_fsm ) { - std::cout << " Erase TRT entry " - << r_ixr_rsp_trt_index.read() << std::endl; + std::cout << " Response from XRAM to a get transaction" << std::endl; } #endif + } } break; } + //////////////////////// + case IXR_RSP_ACK: // Aknowledge the VCI response + { + if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; + +#if DEBUG_MEMC_IXR_RSP +if( m_debug_ixr_rsp_fsm ) +{ + std::cout << " " << std::endl; +} +#endif + break; + } + //////////////////////// + case IXR_RSP_TRT_ERASE: // erase the entry in the TRT + { + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP ) + { + m_transaction_tab.erase(r_ixr_rsp_trt_index.read()); + r_ixr_rsp_fsm = IXR_RSP_IDLE; + +#if DEBUG_MEMC_IXR_RSP +if( m_debug_ixr_rsp_fsm ) +{ + std::cout << " Erase TRT entry " + << r_ixr_rsp_trt_index.read() << std::endl; +} +#endif + } + break; + } /////////////////////// - case IXR_RSP_TRT_READ: // write data in the TRT - { - if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) && p_vci_ixr.rspval ) + case IXR_RSP_TRT_READ: // write data in the TRT + { + if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) && p_vci_ixr.rspval ) { size_t index = r_ixr_rsp_trt_index.read(); - bool eop = p_vci_ixr.reop.read(); - data_t data = p_vci_ixr.rdata.read(); + bool eop = p_vci_ixr.reop.read(); + data_t data = p_vci_ixr.rdata.read(); bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); - assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || p_vci_ixr.rerror.read()) + assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || p_vci_ixr.rerror.read()) and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); - m_transaction_tab.write_rsp(index, - r_ixr_rsp_cpt.read(), - data, + m_transaction_tab.write_rsp(index, + r_ixr_rsp_cpt.read(), + data, error); r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1; - if ( eop ) + if ( eop ) { r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true; @@ -2751,6 +2975,6 @@ // a round-robin priority... // - // When a response is available, the corresponding TRT entry - // must be copied in a local buffer to be written in the cache. + // When a response is available, the corresponding TRT entry + // must be copied in a local buffer to be written in the cache. // The FSM takes the lock protecting the TRT, and the lock protecting the DIR. // It selects a cache slot and writes the line in the cache. @@ -2759,13 +2983,13 @@ // If there is no empty slot, a victim line is evicted, and // invalidate requests are sent to the L1 caches containing copies. - // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD + // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD // FSM to save the victim line to the XRAM, and register the write transaction // in the TRT (using the entry previously used by the read transaction). /////////////////////////////////////////////////////////////////////////////// - switch ( r_xram_rsp_fsm.read() ) + switch ( r_xram_rsp_fsm.read() ) { /////////////////// - case XRAM_RSP_IDLE: // scan the XRAM responses to get the TRT index (round robin) + case XRAM_RSP_IDLE: // scan the XRAM responses to get the TRT index (round robin) { size_t ptr = r_xram_rsp_trt_index.read(); @@ -2776,11 +3000,11 @@ if ( r_ixr_rsp_to_xram_rsp_rok[index] ) { - r_xram_rsp_trt_index = index; - r_ixr_rsp_to_xram_rsp_rok[index] = false; - r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; + r_xram_rsp_trt_index = index; + r_ixr_rsp_to_xram_rsp_rok[index] = false; + r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; #if DEBUG_MEMC_XRAM_RSP if( m_debug_xram_rsp_fsm ) -{ +{ std::cout << " Available cache line in TRT:" << " index = " << std::dec << index << std::endl; @@ -2790,16 +3014,26 @@ } } - break; + break; } /////////////////////// - case XRAM_RSP_DIR_LOCK: // Takes the lock on the directory - { - if( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) - { + case XRAM_RSP_DIR_LOCK: + // Takes the lock on the directory + // Takes the lock on TRT + // Copy the TRT entry in a local buffer + { + if (( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) && + ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP )) + { + // copy the TRT entry in the r_xram_rsp_trt_buf local buffer + size_t index = r_xram_rsp_trt_index.read(); + + TransactionTabEntry trt_entry(m_transaction_tab.read(index)); + r_xram_rsp_trt_buf.copy(trt_entry); // TRT entry local buffer + r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; #if DEBUG_MEMC_XRAM_RSP if( m_debug_xram_rsp_fsm ) -{ +{ std::cout << " Get access to directory" << std::endl; } @@ -2809,18 +3043,13 @@ } /////////////////////// - case XRAM_RSP_TRT_COPY: // Takes the lock on TRT - // Copy the TRT entry in a local buffer - // and select a victim cache line - { - if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) ) - { - // copy the TRT entry in the r_xram_rsp_trt_buf local buffer - size_t index = r_xram_rsp_trt_index.read(); - TransactionTabEntry trt_entry(m_transaction_tab.read(index)); - r_xram_rsp_trt_buf.copy(trt_entry); // TRT entry local buffer - + case XRAM_RSP_TRT_COPY: + // Select a victim cache line + { + if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) ) + { // selects & extracts a victim line from cache size_t way = 0; - size_t set = m_y[(vci_addr_t)(trt_entry.nline * m_words * 4)]; + size_t set = m_y[(vci_addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)]; + DirectoryEntry victim(m_cache_directory.select(set, way)); @@ -2828,6 +3057,7 @@ // copy the victim line in a local buffer - for (size_t i=0 ; i Select a slot: " - << " way = " << std::dec << way - << " / set = " << set + << " way = " << std::dec << way + << " / set = " << set << " / inval_required = " << inval << std::endl; } #endif } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " XRAM_RSP_TRT_COPY state" << std::endl + << "bad TRT allocation" << std::endl; + + exit(0); + } break; } ///////////////////////// - case XRAM_RSP_INVAL_LOCK: // check a possible pending inval - { - if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) + case XRAM_RSP_INVAL_LOCK: // check a possible pending inval + { + if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) { size_t index; @@ -2879,7 +3123,7 @@ } - else if (m_update_tab.is_full() && r_xram_rsp_victim_inval.read()) + else if (m_update_tab.is_full() && r_xram_rsp_victim_inval.read()) { - r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; #if DEBUG_MEMC_XRAM_RSP @@ -2891,6 +3135,6 @@ } #endif - } - else + } + else { r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; @@ -2907,5 +3151,5 @@ } ///////////////////////// - case XRAM_RSP_INVAL_WAIT: // returns to DIR_LOCK to retry + case XRAM_RSP_INVAL_WAIT: // returns to DIR_LOCK to retry { r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; @@ -2913,35 +3157,35 @@ } /////////////////////// - case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) - // and possibly set an inval request in UPT + case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) + // and possibly set an inval request in UPT { // signals generation - bool inst_read = (r_xram_rsp_trt_buf.trdid & 0x2) && r_xram_rsp_trt_buf.proc_read; + bool inst_read = (r_xram_rsp_trt_buf.trdid & 0x2) && r_xram_rsp_trt_buf.proc_read; bool cached_read = (r_xram_rsp_trt_buf.trdid & 0x1) && r_xram_rsp_trt_buf.proc_read; // update data size_t set = r_xram_rsp_victim_set.read(); size_t way = r_xram_rsp_victim_way.read(); - for(size_t i=0; i Directory update: " - << " way = " << std::dec << way - << " / set = " << set + << " way = " << std::dec << way + << " / set = " << set << " / count = " << entry.count << " / is_cnt = " << entry.is_cnt << std::endl; @@ -3004,5 +3248,5 @@ // If the victim is not dirty, we don't need another XRAM put transaction, - // and we canwe erase the TRT entry + // and we canwe erase the TRT entry if (!r_xram_rsp_victim_dirty.read()) m_transaction_tab.erase(r_xram_rsp_trt_index.read()); @@ -3017,8 +3261,8 @@ case XRAM_RSP_TRT_DIRTY: // set the TRT entry (write to XRAM) if the victim is dirty { - if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ) + if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ) { m_transaction_tab.set( r_xram_rsp_trt_index.read(), - false, // write to XRAM + false, // write to XRAM r_xram_rsp_victim_nline.read(), // line index 0, @@ -3035,5 +3279,5 @@ { std::cout << " Set TRT entry for the put transaction:" - << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl; + << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl; } #endif @@ -3047,10 +3291,10 @@ case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM { - if ( !r_xram_rsp_to_tgt_rsp_req.read() ) + if ( !r_xram_rsp_to_tgt_rsp_req.read() ) { r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; - for (size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + for (size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; @@ -3059,5 +3303,5 @@ if ( r_xram_rsp_victim_inval ) r_xram_rsp_fsm = XRAM_RSP_INVAL; - else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; else r_xram_rsp_fsm = XRAM_RSP_IDLE; @@ -3066,5 +3310,5 @@ if( m_debug_xram_rsp_fsm ) { - std::cout << " Request the TGT_RSP FSM to return data:" + std::cout << " Request the TGT_RSP FSM to return data:" << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 @@ -3076,14 +3320,14 @@ } //////////////////// - case XRAM_RSP_INVAL: // send invalidate request to INIT_CMD FSM - { - if( !r_xram_rsp_to_init_cmd_multi_req.read() && - !r_xram_rsp_to_init_cmd_brdcast_req.read() ) - { + case XRAM_RSP_INVAL: // send invalidate request to INIT_CMD FSM + { + if( !r_xram_rsp_to_init_cmd_multi_req.read() && + !r_xram_rsp_to_init_cmd_brdcast_req.read() ) + { bool multi_req = !r_xram_rsp_victim_is_cnt.read(); bool last_multi_req = multi_req && (r_xram_rsp_victim_count.read() == 1); bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1); - r_xram_rsp_to_init_cmd_multi_req = last_multi_req; + r_xram_rsp_to_init_cmd_multi_req = last_multi_req; r_xram_rsp_to_init_cmd_brdcast_req = r_xram_rsp_victim_is_cnt.read(); r_xram_rsp_to_init_cmd_nline = r_xram_rsp_victim_nline.read(); @@ -3098,5 +3342,5 @@ if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; - else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; else r_xram_rsp_fsm = XRAM_RSP_IDLE; @@ -3104,5 +3348,5 @@ if( m_debug_xram_rsp_fsm ) { - std::cout << " Send an inval request to INIT_CMD FSM:" + std::cout << " Send an inval request to INIT_CMD FSM:" << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl; } @@ -3112,7 +3356,7 @@ } ////////////////////////// - case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM - { - if ( !r_xram_rsp_to_ixr_cmd_req.read() ) + case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM + { + if ( !r_xram_rsp_to_ixr_cmd_req.read() ) { r_xram_rsp_to_ixr_cmd_req = true; @@ -3124,5 +3368,5 @@ bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read(); bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1); - if ( not_last_multi_req ) r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + if ( not_last_multi_req ) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; else r_xram_rsp_fsm = XRAM_RSP_IDLE; @@ -3130,5 +3374,5 @@ if( m_debug_xram_rsp_fsm ) { - std::cout << " Send the put request to IXR_CMD FSM:" + std::cout << " Send the put request to IXR_CMD FSM:" << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl; } @@ -3137,8 +3381,29 @@ break; } + ///////////////////////// - case XRAM_RSP_HEAP_ERASE: // erase the list of copies and sent invalidations - { - if( r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP ) + case XRAM_RSP_HEAP_REQ: + // Get the lock to the HEAP directory + { + if( r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP ) + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + +#if DEBUG_MEMC_XRAM_RSP + if( m_debug_xram_rsp_fsm ) + { + std::cout + << " Requesting HEAP lock " + << std::endl; + } +#endif + break; + } + + ///////////////////////// + case XRAM_RSP_HEAP_ERASE: // erase the list of copies and sent invalidations + { + if( r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP ) { HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read()); @@ -3157,11 +3422,11 @@ r_xram_rsp_to_init_cmd_multi_req = true; r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST; - } - else + } + else { r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; } - } - else + } + else { r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; @@ -3171,5 +3436,5 @@ if( m_debug_xram_rsp_fsm ) { - std::cout << " Erase the list of copies:" + std::cout << " Erase the list of copies:" << " srcid = " << std::dec << entry.owner.srcid << " / inst = " << std::dec << entry.owner.inst << std::endl; @@ -3180,5 +3445,5 @@ } ///////////////////////// - case XRAM_RSP_HEAP_LAST: // last member of the list + case XRAM_RSP_HEAP_LAST: // last member of the list { if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP ) @@ -3200,6 +3465,6 @@ last_entry.next = r_xram_rsp_next_ptr.read(); m_heap.unset_full(); - } - else + } + else { last_entry.next = free_pointer; @@ -3220,5 +3485,5 @@ } // /////////////////////// - case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error + case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error { m_transaction_tab.erase(r_xram_rsp_trt_index.read()); @@ -3237,7 +3502,7 @@ } //////////////////////// - case XRAM_RSP_ERROR_RSP: // Request an error response to TGT_RSP FSM - { - if ( !r_xram_rsp_to_tgt_rsp_req.read() ) + case XRAM_RSP_ERROR_RSP: // Request an error response to TGT_RSP FSM + { + if ( !r_xram_rsp_to_tgt_rsp_req.read() ) { r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; @@ -3265,5 +3530,5 @@ //////////////////////////////////////////////////////////////////////////////////// - // CLEANUP FSM + // CLEANUP FSM //////////////////////////////////////////////////////////////////////////////////// // The CLEANUP FSM handles the cleanup request from L1 caches. @@ -3271,576 +3536,671 @@ //////////////////////////////////////////////////////////////////////////////////// - - switch ( r_cleanup_fsm.read() ) + switch ( r_cleanup_fsm.read() ) { - ////////////////// - case CLEANUP_IDLE: - { - if ( p_vci_tgt_cleanup.cmdval.read() ) - { - if (p_vci_tgt_cleanup.srcid.read() >= m_initiators ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_IDLE state" << std::endl; - std::cout << "illegal srcid for cleanup request" << std::endl; - exit(0); - } - - bool reached = false; - for ( size_t index = 0 ; index < m_ncseg && !reached ; index++ ) - { - if ( m_cseg[index]->contains((addr_t)(p_vci_tgt_cleanup.address.read())) ) - reached = true; - } - // only write request to a mapped address that are not broadcast are handled - if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) && - ((p_vci_tgt_cleanup.address.read() & 0x3) == 0) && reached) - { - addr_t line =(((addr_t) p_vci_tgt_cleanup.be.read() << (vci_param::B*8))) | - (((addr_t) p_vci_tgt_cleanup.wdata.read())); - - r_cleanup_nline = line; - r_cleanup_srcid = p_vci_tgt_cleanup.srcid.read(); - r_cleanup_trdid = p_vci_tgt_cleanup.trdid.read(); - r_cleanup_pktid = p_vci_tgt_cleanup.pktid.read(); - r_cleanup_fsm = CLEANUP_DIR_LOCK; + ////////////////// + case CLEANUP_IDLE: + { + if ( p_vci_tgt_cleanup.cmdval.read() ) + { + if (p_vci_tgt_cleanup.srcid.read() >= m_initiators ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " CLEANUP_IDLE state" << std::endl; + std::cout << "illegal srcid for cleanup request" << std::endl; + exit(0); + } + + bool reached = false; + for ( size_t index = 0 ; index < m_ncseg && !reached ; index++ ) + { + if ( m_cseg[index]->contains((addr_t)(p_vci_tgt_cleanup.address.read())) ) + reached = true; + } + // only write request to a mapped address that are not broadcast are handled + if (( p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE ) && + (( p_vci_tgt_cleanup.address.read() & 0x3 ) == 0 ) && reached ) + { + addr_t line =(((addr_t) p_vci_tgt_cleanup.be.read() << (vci_param::B*8))) | + (((addr_t) p_vci_tgt_cleanup.wdata.read())); + + r_cleanup_nline = line; + r_cleanup_srcid = p_vci_tgt_cleanup.srcid.read(); + r_cleanup_trdid = p_vci_tgt_cleanup.trdid.read(); + r_cleanup_pktid = p_vci_tgt_cleanup.pktid.read(); + r_cleanup_fsm = CLEANUP_DIR_REQ; + + #if DEBUG_MEMC_CLEANUP + if( m_debug_cleanup_fsm ) + { + std::cout << " Cleanup request:" << std::hex + << " line addr = " << line * m_words * 4 + << " / owner_id = " << p_vci_tgt_cleanup.srcid.read() + << " / owner_ins = " << (p_vci_tgt_cleanup.trdid.read()&0x1) + << std::endl; + } + #endif + m_cpt_cleanup++; + } + } + break; + } + + ////////////////////// + case CLEANUP_DIR_REQ: + // Get the lock to the directory + { + if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) + { + r_cleanup_fsm = CLEANUP_DIR_LOCK; + } #if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Cleanup request:" << std::hex - << " line addr = " << line * m_words * 4 - << " / owner_id = " << p_vci_tgt_cleanup.srcid.read() - << " / owner_ins = " << (p_vci_tgt_cleanup.trdid.read()&0x1) - << std::endl; -} -#endif - m_cpt_cleanup++; - } - } - break; - } - ////////////////////// - case CLEANUP_DIR_LOCK: // test directory status - { - if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) - { - // Read the directory - size_t way = 0; - addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; - DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); - r_cleanup_is_cnt = entry.is_cnt; - r_cleanup_dirty = entry.dirty; - r_cleanup_tag = entry.tag; - r_cleanup_lock = entry.lock; - r_cleanup_way = way; - r_cleanup_copy = entry.owner.srcid; + if( m_debug_cleanup_fsm ) + { + std::cout + << " Requesting DIR lock " + << std::endl; + } +#endif + break; + } + + ////////////////////// + case CLEANUP_DIR_LOCK: // test directory status + { + if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) + { + // Read the directory + size_t way = 0; + addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; + DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); + r_cleanup_is_cnt = entry.is_cnt; + r_cleanup_dirty = entry.dirty; + r_cleanup_tag = entry.tag; + r_cleanup_lock = entry.lock; + r_cleanup_way = way; + r_cleanup_copy = entry.owner.srcid; #if L1_MULTI_CACHE - r_cleanup_copy_cache= entry.owner.cache_id; -#endif - r_cleanup_copy_inst = entry.owner.inst; - r_cleanup_count = entry.count; - r_cleanup_ptr = entry.ptr; - - if( entry.valid) // hit : the copy must be cleared - { - if ( (entry.count==1) || (entry.is_cnt) ) // no access to the heap - { - r_cleanup_fsm = CLEANUP_DIR_WRITE; - } - else // access to the heap - { - r_cleanup_fsm = CLEANUP_HEAP_LOCK; - } - } - else // miss : we must check the update table - { - r_cleanup_fsm = CLEANUP_UPT_LOCK; - } + r_cleanup_copy_cache = entry.owner.cache_id; +#endif + r_cleanup_copy_inst = entry.owner.inst; + r_cleanup_count = entry.count; + r_cleanup_ptr = entry.ptr; + + if( entry.valid) // hit : the copy must be cleared + { + if ( (entry.count==1) || (entry.is_cnt) ) // no access to the heap + { + r_cleanup_fsm = CLEANUP_DIR_WRITE; + } + else // access to the heap + { + r_cleanup_fsm = CLEANUP_HEAP_REQ; + } + } + else // miss : we must check the update table + { + r_cleanup_fsm = CLEANUP_UPT_LOCK; + } #if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Test directory status: " << std::hex + if( m_debug_cleanup_fsm ) + { + std::cout + << " Test directory status: " << std::hex << " line = " << r_cleanup_nline.read() * m_words * 4 << " / hit = " << entry.valid << " / dir_id = " << entry.owner.srcid << " / dir_ins = " << entry.owner.inst - << " / search_id = " << r_cleanup_srcid.read() + << " / search_id = " << r_cleanup_srcid.read() << " / search_ins = " << (r_cleanup_trdid.read()&0x1) << " / count = " << entry.count << " / is_cnt = " << entry.is_cnt << std::endl; -} -#endif - } - break; - } - /////////////////////// - case CLEANUP_DIR_WRITE: // update the directory entry without heap access - { - if ( r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_DIR_WRITE state" - << " bad DIR allocation" << std::endl; - exit(0); - } - - size_t way = r_cleanup_way.read(); - size_t set = m_y[(vci_addr_t)(r_cleanup_nline.read()*m_words*4)]; - bool cleanup_inst = r_cleanup_trdid.read() & 0x1; - bool match_srcid = ((r_cleanup_copy.read() == r_cleanup_srcid.read()) + } +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " CLEANUP_DIR_LOCK state" + << " bad DIR allocation" << std::endl; + + exit(0); + } + break; + } + + /////////////////////// + case CLEANUP_DIR_WRITE: + // Update the directory entry without heap access + { + if ( r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " CLEANUP_DIR_WRITE state" + << " bad DIR allocation" << std::endl; + exit(0); + } + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(vci_addr_t)(r_cleanup_nline.read()*m_words*4)]; + bool cleanup_inst = r_cleanup_trdid.read() & 0x1; + bool match_srcid = ((r_cleanup_copy.read() == r_cleanup_srcid.read()) #if L1_MULTI_CACHE - and (r_cleanup_copy_cache.read() == r_cleanup_pktid.read()) -#endif - ); - bool match_inst = (r_cleanup_copy_inst.read() == cleanup_inst); - bool match = match_srcid && match_inst; - - // update the cache directory (for the copies) - DirectoryEntry entry; - entry.valid = true; - entry.is_cnt = r_cleanup_is_cnt.read(); - entry.dirty = r_cleanup_dirty.read(); - entry.tag = r_cleanup_tag.read(); - entry.lock = r_cleanup_lock.read(); - entry.ptr = r_cleanup_ptr.read(); - - if ( r_cleanup_is_cnt.read() ) // counter mode - { - entry.count = r_cleanup_count.read() -1; - entry.owner.srcid = 0; + and (r_cleanup_copy_cache.read() == r_cleanup_pktid.read()) +#endif + ); + bool match_inst = (r_cleanup_copy_inst.read() == cleanup_inst); + bool match = match_srcid && match_inst; + + // update the cache directory (for the copies) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cleanup_is_cnt.read(); + entry.dirty = r_cleanup_dirty.read(); + entry.tag = r_cleanup_tag.read(); + entry.lock = r_cleanup_lock.read(); + entry.ptr = r_cleanup_ptr.read(); + + if ( r_cleanup_is_cnt.read() ) // counter mode + { + entry.count = r_cleanup_count.read() -1; + entry.owner.srcid = 0; #if L1_MULTI_CACHE - entry.owner.cache_id= 0; -#endif - entry.owner.inst = 0; - // response to the cache - r_cleanup_fsm = CLEANUP_RSP; - } - else // linked_list mode - { - if ( match ) // hit - { - entry.count = 0; // no more copy - entry.owner.srcid = 0; + entry.owner.cache_id= 0; +#endif + entry.owner.inst = 0; + // response to the cache + r_cleanup_fsm = CLEANUP_RSP; + } + else // linked_list mode + { + if ( match ) // hit + { + entry.count = 0; // no more copy + entry.owner.srcid = 0; #if L1_MULTI_CACHE - entry.owner.cache_id=0; -#endif - entry.owner.inst = 0; - r_cleanup_fsm = CLEANUP_RSP; - } - else // miss - { - entry.count = r_cleanup_count.read(); - entry.owner.srcid = r_cleanup_copy.read(); + entry.owner.cache_id=0; +#endif + entry.owner.inst = 0; + r_cleanup_fsm = CLEANUP_RSP; + } + else // miss + { + entry.count = r_cleanup_count.read(); + entry.owner.srcid = r_cleanup_copy.read(); #if L1_MULTI_CACHE - entry.owner.cache_id = r_cleanup_copy_cache.read(); -#endif - entry.owner.inst = r_cleanup_copy_inst.read(); - r_cleanup_fsm = CLEANUP_UPT_LOCK; - } - } - m_cache_directory.write(set, way, entry); + entry.owner.cache_id = r_cleanup_copy_cache.read(); +#endif + entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_fsm = CLEANUP_UPT_LOCK; + } + } + m_cache_directory.write(set, way, entry); #if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Update directory:" << std::hex - << " line = " << r_cleanup_nline.read() * m_words * 4 - << " / dir_id = " << entry.owner.srcid - << " / dir_ins = " << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -} -#endif - - break; - } - /////////////////////// - case CLEANUP_HEAP_LOCK: // two cases are handled in this state: - // - the matching copy is directly in the directory - // - the matching copy is the first copy in the heap - { - if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP ) - { - size_t way = r_cleanup_way.read(); - size_t set = m_y[(vci_addr_t)(r_cleanup_nline.read()*m_words*4)]; - HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read()); - bool last = (heap_entry.next == r_cleanup_ptr.read()); - bool cleanup_inst = r_cleanup_trdid.read() & 0x1; - - // match_dir computation - bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); - bool match_dir_inst = (r_cleanup_copy_inst.read() == cleanup_inst); - bool match_dir = match_dir_srcid and match_dir_inst; + if( m_debug_cleanup_fsm ) + { + std::cout + << " Update directory:" << std::hex + << " line = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + } +#endif + + break; + } + + /////////////////////// + case CLEANUP_HEAP_REQ: + // Get the lock to the HEAP directory + { + if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP ) + { + r_cleanup_fsm = CLEANUP_HEAP_LOCK; + } + +#if DEBUG_MEMC_CLEANUP + if( m_debug_cleanup_fsm ) + { + std::cout + << " Requesting HEAP lock " + << std::endl; + } +#endif + break; + } + + /////////////////////// + case CLEANUP_HEAP_LOCK: + // two cases are handled in this state: + // - the matching copy is directly in the directory + // - the matching copy is the first copy in the heap + { + if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP ) + { + size_t way = r_cleanup_way.read(); + size_t set = m_y[(vci_addr_t)(r_cleanup_nline.read()*m_words*4)]; + HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read()); + bool last = (heap_entry.next == r_cleanup_ptr.read()); + bool cleanup_inst = r_cleanup_trdid.read() & 0x1; + + // match_dir computation + bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_dir_inst = (r_cleanup_copy_inst.read() == cleanup_inst); + bool match_dir = match_dir_srcid and match_dir_inst; #if L1_MULTI_CACHE - match_dir = match_dir and (r_cleanup_copy_cache.read() == r_cleanup_pktid.read()); -#endif - - // match_heap computation - bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); - bool match_heap_inst = (heap_entry.owner.inst == cleanup_inst); - bool match_heap = match_heap_srcid and match_heap_inst; + match_dir = match_dir and (r_cleanup_copy_cache.read() == r_cleanup_pktid.read()); +#endif + + // match_heap computation + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == cleanup_inst); + bool match_heap = match_heap_srcid and match_heap_inst; #if L1_MULTI_CACHE - match_heap = match_heap and (heap_entry.owner.cache_id == r_cleanup_pktid.read()); -#endif - - r_cleanup_prev_ptr = r_cleanup_ptr.read(); - r_cleanup_prev_srcid = heap_entry.owner.srcid; + match_heap = match_heap and (heap_entry.owner.cache_id == r_cleanup_pktid.read()); +#endif + + r_cleanup_prev_ptr = r_cleanup_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; #if L1_MULTI_CACHE - r_cleanup_prev_cache_id = heap_entry.owner.cache_id; -#endif - r_cleanup_prev_inst = heap_entry.owner.inst; - - if (match_dir) // the matching copy is registered in the directory - { - // the copy registered in the directory must be replaced - // by the first copy registered in the heap - // and the corresponding entry must be freed - DirectoryEntry dir_entry; - dir_entry.valid = true; - dir_entry.is_cnt = r_cleanup_is_cnt.read(); - dir_entry.dirty = r_cleanup_dirty.read(); - dir_entry.tag = r_cleanup_tag.read(); - dir_entry.lock = r_cleanup_lock.read(); - dir_entry.ptr = heap_entry.next; - dir_entry.count = r_cleanup_count.read()-1; - dir_entry.owner.srcid = heap_entry.owner.srcid; + r_cleanup_prev_cache_id = heap_entry.owner.cache_id; +#endif + r_cleanup_prev_inst = heap_entry.owner.inst; + + if (match_dir) + // the matching copy is registered in the directory + { + // the copy registered in the directory must be replaced + // by the first copy registered in the heap + // and the corresponding entry must be freed + DirectoryEntry dir_entry; + dir_entry.valid = true; + dir_entry.is_cnt = r_cleanup_is_cnt.read(); + dir_entry.dirty = r_cleanup_dirty.read(); + dir_entry.tag = r_cleanup_tag.read(); + dir_entry.lock = r_cleanup_lock.read(); + dir_entry.ptr = heap_entry.next; + dir_entry.count = r_cleanup_count.read()-1; + dir_entry.owner.srcid = heap_entry.owner.srcid; #if L1_MULTI_CACHE - dir_entry.owner.cache_id = heap_entry.owner.cache_id; -#endif - dir_entry.owner.inst = heap_entry.owner.inst; - m_cache_directory.write(set,way,dir_entry); - r_cleanup_next_ptr = r_cleanup_ptr.read(); - r_cleanup_fsm = CLEANUP_HEAP_FREE; - } - else if (match_heap) // the matching copy is the first copy in the heap - { - // The first copy in heap must be freed - // and the copy registered in directory must point to the next copy in heap - DirectoryEntry dir_entry; - dir_entry.valid = true; - dir_entry.is_cnt = r_cleanup_is_cnt.read(); - dir_entry.dirty = r_cleanup_dirty.read(); - dir_entry.tag = r_cleanup_tag.read(); - dir_entry.lock = r_cleanup_lock.read(); - dir_entry.ptr = heap_entry.next; - dir_entry.count = r_cleanup_count.read()-1; - dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.cache_id = heap_entry.owner.cache_id; +#endif + dir_entry.owner.inst = heap_entry.owner.inst; + + m_cache_directory.write(set,way,dir_entry); + + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + else if (match_heap) + // the matching copy is the first copy in the heap + { + // The first copy in heap must be freed + // and the copy registered in directory must point to the next copy in heap + DirectoryEntry dir_entry; + dir_entry.valid = true; + dir_entry.is_cnt = r_cleanup_is_cnt.read(); + dir_entry.dirty = r_cleanup_dirty.read(); + dir_entry.tag = r_cleanup_tag.read(); + dir_entry.lock = r_cleanup_lock.read(); + dir_entry.ptr = heap_entry.next; + dir_entry.count = r_cleanup_count.read()-1; + dir_entry.owner.srcid = r_cleanup_copy.read(); #if L1_MULTI_CACHE - dir_entry.owner.cache_id = r_cleanup_copy_cache.read(); -#endif - dir_entry.owner.inst = r_cleanup_copy_inst.read(); - m_cache_directory.write(set,way,dir_entry); - r_cleanup_next_ptr = r_cleanup_ptr.read(); - r_cleanup_fsm = CLEANUP_HEAP_FREE; - } - else if(!last) // The matching copy is in the heap, but is not the first copy - { - // The directory entry must be modified to decrement count - DirectoryEntry dir_entry; - dir_entry.valid = true; - dir_entry.is_cnt = r_cleanup_is_cnt.read(); - dir_entry.dirty = r_cleanup_dirty.read(); - dir_entry.tag = r_cleanup_tag.read(); - dir_entry.lock = r_cleanup_lock.read(); - dir_entry.ptr = r_cleanup_ptr.read(); - dir_entry.count = r_cleanup_count.read()-1; - dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.cache_id = r_cleanup_copy_cache.read(); +#endif + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + + m_cache_directory.write(set,way,dir_entry); + + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + else if(!last) + // The matching copy is in the heap, but is not the first copy + { + // The directory entry must be modified to decrement count + DirectoryEntry dir_entry; + dir_entry.valid = true; + dir_entry.is_cnt = r_cleanup_is_cnt.read(); + dir_entry.dirty = r_cleanup_dirty.read(); + dir_entry.tag = r_cleanup_tag.read(); + dir_entry.lock = r_cleanup_lock.read(); + dir_entry.ptr = r_cleanup_ptr.read(); + dir_entry.count = r_cleanup_count.read()-1; + dir_entry.owner.srcid = r_cleanup_copy.read(); #if L1_MULTI_CACHE - dir_entry.owner.cache_id = r_cleanup_copy_cache.read(); -#endif - dir_entry.owner.inst = r_cleanup_copy_inst.read(); - m_cache_directory.write(set,way,dir_entry); - r_cleanup_next_ptr = heap_entry.next; - r_cleanup_fsm = CLEANUP_HEAP_SEARCH; - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_LOCK state" - << " hit but copy not found" << std::endl; - exit(0); - } + dir_entry.owner.cache_id = r_cleanup_copy_cache.read(); +#endif + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + + m_cache_directory.write(set,way,dir_entry); + + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " CLEANUP_HEAP_LOCK state" + << " hit but copy not found" << std::endl; + exit(0); + } #if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Checks matching:" + if( m_debug_cleanup_fsm ) + { + std::cout + << " Checks matching:" << " line = " << r_cleanup_nline.read() * m_words * 4 << " / dir_id = " << r_cleanup_copy.read() << " / dir_ins = " << r_cleanup_copy_inst.read() << " / heap_id = " << heap_entry.owner.srcid - << " / heap_ins = " << heap_entry.owner.inst - << " / search_id = " << r_cleanup_srcid.read() - << " / search_ins = " << (r_cleanup_trdid.read()&0x1) << std::endl; -} -#endif - } - break; - } - ///////////////////////// - case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy - // is in the heap, but is not the first in the linked list - { - if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_SEARCH state" - << " bad HEAP allocation" << std::endl; - exit(0); - } - - HeapEntry heap_entry = m_heap.read(r_cleanup_next_ptr.read()); - bool last = (heap_entry.next == r_cleanup_next_ptr.read()); - bool cleanup_inst = r_cleanup_trdid.read() & 0x1; - bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); - bool match_heap_inst = (heap_entry.owner.inst == cleanup_inst); - bool match_heap = match_heap_srcid && match_heap_inst; -#if L1_MULTI_CACHE - match_heap = match_heap and (heap_entry.owner.cache_id == r_cleanup_pktid.read()); -#endif - -#if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Cheks matching:" - << " line = " << r_cleanup_nline.read() * m_words * 4 - << " / heap_id = " << heap_entry.owner.srcid - << " / heap_ins = " << heap_entry.owner.inst - << " / search_id = " << r_cleanup_srcid.read() - << " / search_ins = " << (r_cleanup_trdid.read()&0x1) - << " / last = " << last << std::endl; -} -#endif - if(match_heap) // the matching copy must be removed - { - r_cleanup_ptr = heap_entry.next; // reuse ressources - r_cleanup_fsm = CLEANUP_HEAP_CLEAN; - } - else - { - if ( last ) - { - std::cout << "VCI_MEM_CACHE_ERROR " << name() - << " CLEANUP_HEAP_SEARCH state" - << " cleanup hit but copy not found" << std::endl; - exit(0); - } - else // test the next in the linked list - { - r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); - r_cleanup_prev_srcid = heap_entry.owner.srcid; -#if L1_MULTI_CACHE - r_cleanup_prev_cache_id = heap_entry.owner.cache_id; -#endif - r_cleanup_prev_inst = heap_entry.owner.inst; - r_cleanup_next_ptr = heap_entry.next; - r_cleanup_fsm = CLEANUP_HEAP_SEARCH; - -#if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Matching copy not found, search next:" - << " line = " << r_cleanup_nline.read() * m_words * 4 - << " / heap_id = " << heap_entry.owner.srcid << " / heap_ins = " << heap_entry.owner.inst << " / search_id = " << r_cleanup_srcid.read() << " / search_ins = " << (r_cleanup_trdid.read()&0x1) << std::endl; -} -#endif - } - } - break; - } - //////////////////////// - case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list - { - if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_HEAP_CLEAN state" - << "Bad HEAP allocation" << std::endl; - exit(0); - } - - bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); - HeapEntry heap_entry; - heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); + } +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " CLEANUP_HEAP_LOCK state" + << " bad HEAP allocation" << std::endl; + + exit(0); + } + break; + } + + ///////////////////////// + case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy + // is in the heap, but is not the first in the linked list + { + if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " CLEANUP_HEAP_SEARCH state" + << " bad HEAP allocation" << std::endl; + exit(0); + } + + HeapEntry heap_entry = m_heap.read(r_cleanup_next_ptr.read()); + bool last = (heap_entry.next == r_cleanup_next_ptr.read()); + bool cleanup_inst = r_cleanup_trdid.read() & 0x1; + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == cleanup_inst); + bool match_heap = match_heap_srcid && match_heap_inst; #if L1_MULTI_CACHE - heap_entry.owner.cache_id = r_cleanup_prev_cache_id.read(); -#endif - heap_entry.owner.inst = r_cleanup_prev_inst.read(); - if(last) // this is the last entry of the list of copies - { - heap_entry.next = r_cleanup_prev_ptr.read(); - } - else // this is not the last entry - { - heap_entry.next = r_cleanup_ptr.read(); - } - m_heap.write(r_cleanup_prev_ptr.read(),heap_entry); - r_cleanup_fsm = CLEANUP_HEAP_FREE; + match_heap = match_heap and (heap_entry.owner.cache_id == r_cleanup_pktid.read()); +#endif #if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Remove the copy in the linked list" << std::endl; -} -#endif - break; - } - /////////////////////// - case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed - // and becomes the head of the list of free entries - { - if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP ) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " CLEANUP_HEAP_CLEAN state" << std::endl; - std::cout << "Bad HEAP allocation" << std::endl; - exit(0); - } - - HeapEntry heap_entry; - heap_entry.owner.srcid = 0; + if( m_debug_cleanup_fsm ) + { + std::cout << " Cheks matching:" + << " line = " << r_cleanup_nline.read() * m_words * 4 + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << (r_cleanup_trdid.read()&0x1) + << " / last = " << last << std::endl; + } +#endif + if(match_heap) // the matching copy must be removed + { + r_cleanup_ptr = heap_entry.next; // reuse ressources + r_cleanup_fsm = CLEANUP_HEAP_CLEAN; + } + else + { + if ( last ) + { + std::cout << "VCI_MEM_CACHE_ERROR " << name() + << " CLEANUP_HEAP_SEARCH state" + << " cleanup hit but copy not found" << std::endl; + exit(0); + } + else // test the next in the linked list + { + r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; #if L1_MULTI_CACHE - heap_entry.owner.cache_id = 0; -#endif - heap_entry.owner.inst = false; - - if(m_heap.is_full()) heap_entry.next = r_cleanup_next_ptr.read(); - else heap_entry.next = m_heap.next_free_ptr(); - m_heap.write(r_cleanup_next_ptr.read(),heap_entry); - m_heap.write_free_ptr(r_cleanup_next_ptr.read()); - m_heap.unset_full(); + r_cleanup_prev_cache_id = heap_entry.owner.cache_id; +#endif + r_cleanup_prev_inst = heap_entry.owner.inst; + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + +#if DEBUG_MEMC_CLEANUP + if( m_debug_cleanup_fsm ) + { + std::cout << " Matching copy not found, search next:" + << " line = " << r_cleanup_nline.read() * m_words * 4 + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << (r_cleanup_trdid.read()&0x1) << std::endl; + } +#endif + } + } + break; + } + + //////////////////////// + case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list + { + if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " CLEANUP_HEAP_CLEAN state" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + + bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); + HeapEntry heap_entry; + heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); +#if L1_MULTI_CACHE + heap_entry.owner.cache_id = r_cleanup_prev_cache_id.read(); +#endif + heap_entry.owner.inst = r_cleanup_prev_inst.read(); + + if(last) // this is the last entry of the list of copies + { + heap_entry.next = r_cleanup_prev_ptr.read(); + } + else // this is not the last entry + { + heap_entry.next = r_cleanup_ptr.read(); + } + + m_heap.write(r_cleanup_prev_ptr.read(),heap_entry); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + +#if DEBUG_MEMC_CLEANUP + if( m_debug_cleanup_fsm ) + { + std::cout << " Remove the copy in the linked list" << std::endl; + } +#endif + break; + } + + /////////////////////// + case CLEANUP_HEAP_FREE: + // The heap entry pointed by r_cleanup_next_ptr is freed + // and becomes the head of the list of free entries + { + if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP ) + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() + << " CLEANUP_HEAP_CLEAN state" << std::endl + << "Bad HEAP allocation" << std::endl; + + exit(0); + } + + HeapEntry heap_entry; + heap_entry.owner.srcid = 0; +#if L1_MULTI_CACHE + heap_entry.owner.cache_id = 0; +#endif + heap_entry.owner.inst = false; + + if(m_heap.is_full()) + { + heap_entry.next = r_cleanup_next_ptr.read(); + } + else + { + heap_entry.next = m_heap.next_free_ptr(); + } + + m_heap.write(r_cleanup_next_ptr.read(),heap_entry); + m_heap.write_free_ptr(r_cleanup_next_ptr.read()); + m_heap.unset_full(); + + r_cleanup_fsm = CLEANUP_RSP; + +#if DEBUG_MEMC_CLEANUP + if( m_debug_cleanup_fsm ) + { + std::cout << " Update the list of free entries" << std::endl; + } +#endif + break; + } + + ////////////////////// + case CLEANUP_UPT_LOCK: + { + if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP ) + { + size_t index = 0; + bool hit_inval; + hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index); + + if ( !hit_inval ) // no pending inval + { + +#if DEBUG_MEMC_CLEANUP + if( m_debug_cleanup_fsm ) + { + std::cout << " Unexpected cleanup with no corresponding UPT entry:" + << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl; + } +#endif r_cleanup_fsm = CLEANUP_RSP; + } + else // pending inval + { + r_cleanup_write_srcid = m_update_tab.srcid(index); + r_cleanup_write_trdid = m_update_tab.trdid(index); + r_cleanup_write_pktid = m_update_tab.pktid(index); + r_cleanup_need_rsp = m_update_tab.need_rsp(index); + r_cleanup_fsm = CLEANUP_UPT_WRITE; + } + r_cleanup_index.write(index) ; + } + break; + } + + /////////////////////// + case CLEANUP_UPT_WRITE: // decrement response counter + { + size_t count = 0; + m_update_tab.decrement(r_cleanup_index.read(), count); + if ( count == 0 ) + { + m_update_tab.clear(r_cleanup_index.read()); #if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Update the list of free entries" << std::endl; -} -#endif - break; - } - ////////////////////// - case CLEANUP_UPT_LOCK: - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP ) - { - size_t index = 0; - bool hit_inval; - hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index); - - if ( !hit_inval ) // no pending inval - { - -#if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Unexpected cleanup with no corresponding UPT entry:" - << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl; -} -#endif - r_cleanup_fsm = CLEANUP_RSP; - } - else // pending inval - { - r_cleanup_write_srcid = m_update_tab.srcid(index); - r_cleanup_write_trdid = m_update_tab.trdid(index); - r_cleanup_write_pktid = m_update_tab.pktid(index); - r_cleanup_need_rsp = m_update_tab.need_rsp(index); - r_cleanup_fsm = CLEANUP_UPT_WRITE; - } - r_cleanup_index.write(index) ; - } - break; - } - /////////////////////// - case CLEANUP_UPT_WRITE: // decrement response counter - { - size_t count = 0; - m_update_tab.decrement(r_cleanup_index.read(), count); - if ( count == 0 ) - { - m_update_tab.clear(r_cleanup_index.read()); - -#if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Decrement response counter in UPT:" + if( m_debug_cleanup_fsm ) + { + std::cout << " Decrement response counter in UPT:" << " UPT_index = " << r_cleanup_index.read() << " rsp_count = " << count << std::endl; -} -#endif - if( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP ; - else r_cleanup_fsm = CLEANUP_RSP; - } - else - { - r_cleanup_fsm = CLEANUP_RSP ; - } - break; - } - /////////////////////// - case CLEANUP_WRITE_RSP: // Response to a previous write on the direct network - { - if( !r_cleanup_to_tgt_rsp_req.read() ) - { - r_cleanup_to_tgt_rsp_req = true; - r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); - r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); - r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); - r_cleanup_fsm = CLEANUP_RSP; + } +#endif + if( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP ; + else r_cleanup_fsm = CLEANUP_RSP; + } + else + { + r_cleanup_fsm = CLEANUP_RSP ; + } + break; + } + + /////////////////////// + case CLEANUP_WRITE_RSP: // Response to a previous write on the direct network + { + if( !r_cleanup_to_tgt_rsp_req.read() ) + { + r_cleanup_to_tgt_rsp_req = true; + r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); + r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); + r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); + r_cleanup_fsm = CLEANUP_RSP; #if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Send a response to a cleanup request:" + if( m_debug_cleanup_fsm ) + { + std::cout << " Send a response to a cleanup request:" << " rsrcid = " << std::dec << r_cleanup_write_srcid.read() << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read() << std::endl; -} -#endif - } - break; - } - ///////////////// - case CLEANUP_RSP: // Response to a cleanup on the coherence network - { - if ( p_vci_tgt_cleanup.rspack.read() ) - { - r_cleanup_fsm = CLEANUP_IDLE; + } +#endif + } + break; + } + + ///////////////// + case CLEANUP_RSP: // Response to a cleanup on the coherence network + { + if ( p_vci_tgt_cleanup.rspack.read() ) + { + r_cleanup_fsm = CLEANUP_IDLE; #if DEBUG_MEMC_CLEANUP -if( m_debug_cleanup_fsm ) -{ - std::cout << " Send the response to a cleanup request:" + if( m_debug_cleanup_fsm ) + { + std::cout << " Send the response to a cleanup request:" << " rsrcid = " << std::dec << r_cleanup_write_srcid.read() << " / rtrdid = " << r_cleanup_write_trdid.read() << std::endl; -} -#endif - } - break; - } + } +#endif + } + break; + } } // end switch cleanup fsm //////////////////////////////////////////////////////////////////////////////////// - // SC FSM + // SC FSM //////////////////////////////////////////////////////////////////////////////////// - // The SC FSM handles the SC (Store Conditionnal) atomic commands, + // The SC FSM handles the SC (Store Conditionnal) atomic commands, // that are handled as "compare-and-swap instructions. - // - // This command contains two or four flits: + // + // This command contains two or four flits: // - In case of 32 bits atomic access, the first flit contains the value read // by a previous LL instruction, the second flit contains the value to be writen. // - In case of 64 bits atomic access, the 2 first flits contains the value read // by a previous LL instruction, the 2 next flits contains the value to be writen. - // + // // The target address is cachable. If it is replicated in other L1 caches // than the writer, a coherence operation is done. - // + // // It access the directory to check hit / miss. // - In case of miss, the SC FSM must register a GET transaction in TRT. - // If a read transaction to the XRAM for this line already exists, + // If a read transaction to the XRAM for this line already exists, // or if the transaction table is full, it goes to the WAIT state // to release the locks and try again. When the GET transaction has been @@ -3850,10 +4210,10 @@ /////////////////////////////////////////////////////////////////////////////////// - switch ( r_sc_fsm.read() ) + switch ( r_sc_fsm.read() ) { ///////////// - case SC_IDLE: // fill the local rdata buffers - { - if( m_cmd_sc_addr_fifo.rok() ) + case SC_IDLE: // fill the local rdata buffers + { + if( m_cmd_sc_addr_fifo.rok() ) { @@ -3862,6 +4222,6 @@ { std::cout << " SC command: " << std::hex - << " srcid = " << std::dec << m_cmd_sc_srcid_fifo.read() - << " addr = " << std::hex << m_cmd_sc_addr_fifo.read() + << " srcid = " << std::dec << m_cmd_sc_srcid_fifo.read() + << " addr = " << std::hex << m_cmd_sc_addr_fifo.read() << " wdata = " << m_cmd_sc_wdata_fifo.read() << " eop = " << std::dec << m_cmd_sc_eop_fifo.read() @@ -3872,6 +4232,6 @@ { m_cpt_sc++; - r_sc_fsm = SC_DIR_LOCK; - } + r_sc_fsm = SC_DIR_REQ; + } else // we keep the last word in the FIFO { @@ -3887,5 +4247,5 @@ if( r_sc_cpt.read()>3 ) // more than 4 flits... { - std::cout << "VCI_MEM_CACHE ERROR in SC_IDLE state : illegal SC command" + std::cout << "VCI_MEM_CACHE ERROR in SC_IDLE state : illegal SC command" << std::endl; exit(0); @@ -3896,11 +4256,31 @@ r_sc_cpt = r_sc_cpt.read()+1; - } + } break; } + + ///////////////// + case SC_DIR_REQ: + { + if( r_alloc_dir_fsm.read() == ALLOC_DIR_SC ) + { + r_sc_fsm = SC_DIR_LOCK; + } + +#if DEBUG_MEMC_SC + if( m_debug_sc_fsm ) + { + std::cout + << " Requesting DIR lock " + << std::endl; + } +#endif + break; + } + ///////////////// case SC_DIR_LOCK: // Read the directory { - if( r_alloc_dir_fsm.read() == ALLOC_DIR_SC ) + if( r_alloc_dir_fsm.read() == ALLOC_DIR_SC ) { size_t way = 0; @@ -3919,6 +4299,6 @@ r_sc_count = entry.count; - if ( entry.valid ) r_sc_fsm = SC_DIR_HIT_READ; - else r_sc_fsm = SC_MISS_TRT_LOCK; + if ( entry.valid ) r_sc_fsm = SC_DIR_HIT_READ; + else r_sc_fsm = SC_MISS_TRT_LOCK; #if DEBUG_MEMC_SC @@ -3927,5 +4307,5 @@ std::cout << " Directory acces" << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() - << " / hit = " << std::dec << entry.valid + << " / hit = " << std::dec << entry.valid << " / count = " << entry.count << " / is_cnt = " << entry.is_cnt << std::endl; @@ -3933,4 +4313,14 @@ #endif } + else + { + std::cout + << "VCI_MEM_CACHE ERROR " << name() + << " SC_DIR_LOCK state" << std::endl + << "Bad DIR allocation" << std::endl; + + exit(0); + } + break; } @@ -3939,15 +4329,15 @@ // and check data change in cache { - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; // update directory (lock & dirty bits) DirectoryEntry entry; - entry.valid = true; + entry.valid = true; entry.is_cnt = r_sc_is_cnt.read(); - entry.dirty = true; - entry.lock = true; - entry.tag = r_sc_tag.read(); + entry.dirty = true; + entry.lock = true; + entry.tag = r_sc_tag.read(); entry.owner.srcid = r_sc_copy.read(); #if L1_MULTI_CACHE @@ -3965,9 +4355,9 @@ ok &= ( r_sc_rdata[1] == m_cache_data[way][set][word+1] ); - // to avoid livelock, force the atomic access to fail pseudo-randomly + // to avoid livelock, force the atomic access to fail pseudo-randomly bool forced_fail = ( (r_sc_lfsr % (64) == 0) && RANDOMIZE_SC ); r_sc_lfsr = (r_sc_lfsr >> 1) ^ ((-(r_sc_lfsr & 1)) & 0xd0000001); - if( ok and not forced_fail ) // no data change + if( ok and not forced_fail ) // no data change { r_sc_fsm = SC_DIR_HIT_WRITE; @@ -3976,10 +4366,10 @@ { r_sc_fsm = SC_RSP_FAIL; - } + } #if DEBUG_MEMC_SC if( m_debug_sc_fsm ) { - std::cout << " Test if SC success:" + std::cout << " Test if SC success:" << " / expected value = " << r_sc_rdata[0].read() << " / actual value = " << m_cache_data[way][set][word] @@ -3990,18 +4380,18 @@ } ////////////////////// - case SC_DIR_HIT_WRITE: // test if a CC transaction is required + case SC_DIR_HIT_WRITE: // test if a CC transaction is required // write data in cache if no CC request { // test coherence request - if(r_sc_count.read()) // replicated line + if(r_sc_count.read()) // replicated line { if ( r_sc_is_cnt.read() ) { - r_sc_fsm = SC_BC_TRT_LOCK; // broadcast invalidate required + r_sc_fsm = SC_BC_TRT_LOCK; // broadcast invalidate required } - else if( !r_sc_to_init_cmd_multi_req.read() && + else if( !r_sc_to_init_cmd_multi_req.read() && !r_sc_to_init_cmd_brdcast_req.read() ) { - r_sc_fsm = SC_UPT_LOCK; // multi update required + r_sc_fsm = SC_UPT_LOCK; // multi update required } else @@ -4009,10 +4399,10 @@ r_sc_fsm = SC_WAIT; } - } - else // no copies - { - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + } + else // no copies + { + size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; // cache update @@ -4022,9 +4412,9 @@ // monitor - if ( m_monitor_ok ) + if ( m_monitor_ok ) { vci_addr_t address = m_cmd_sc_addr_fifo.read(); - char buf[80]; - snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); + char buf[80]; + snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); check_monitor( buf, address, r_sc_wdata.read() ); if ( r_sc_cpt.read()==4 ) @@ -4036,5 +4426,5 @@ if( m_debug_sc_fsm ) { - std::cout << " Update cache:" + std::cout << " Update cache:" << " way = " << std::dec << way << " / set = " << set @@ -4052,5 +4442,5 @@ // releases locks to retry later if UPT full { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_SC ) + if ( r_alloc_upt_fsm.read() == ALLOC_UPT_SC ) { bool wok = false; @@ -4059,8 +4449,8 @@ size_t trdid = m_cmd_sc_trdid_fifo.read(); size_t pktid = m_cmd_sc_pktid_fifo.read(); - addr_t nline = m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + addr_t nline = m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; size_t nb_copies = r_sc_count.read(); - wok = m_update_tab.set(true, // it's an update transaction + wok = m_update_tab.set(true, // it's an update transaction false, // it's not a broadcast true, // it needs a response @@ -4074,7 +4464,7 @@ { // cache update - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; m_cache_data[way][set][word] = r_sc_wdata.read(); @@ -4083,9 +4473,9 @@ // monitor - if ( m_monitor_ok ) - { + if ( m_monitor_ok ) + { vci_addr_t address = m_cmd_sc_addr_fifo.read(); - char buf[80]; - snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); + char buf[80]; + snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); check_monitor( buf, address, r_sc_wdata.read() ); if ( r_sc_cpt.read()==4 ) @@ -4104,7 +4494,7 @@ if( m_debug_sc_fsm ) { - std::cout << " Register multi-update transaction in UPT" + std::cout << " Register multi-update transaction in UPT" << " / wok = " << wok - << " / nline = " << std::hex << nline + << " / nline = " << std::hex << nline << " / count = " << nb_copies << std::endl; } @@ -4114,5 +4504,5 @@ } ///////////// - case SC_WAIT: // release all locks and retry from beginning + case SC_WAIT: // release all locks and retry from beginning { @@ -4123,11 +4513,11 @@ } #endif - r_sc_fsm = SC_DIR_LOCK; + r_sc_fsm = SC_DIR_REQ; break; } ////////////////// - case SC_UPT_HEAP_LOCK: // lock the heap - { - if( r_alloc_heap_fsm.read() == ALLOC_HEAP_SC ) + case SC_UPT_HEAP_LOCK: // lock the heap + { + if( r_alloc_heap_fsm.read() == ALLOC_HEAP_SC ) { @@ -4143,5 +4533,5 @@ } //////////////// - case SC_UPT_REQ: // send a first update request to INIT_CMD FSM + case SC_UPT_REQ: // send a first update request to INIT_CMD FSM { assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_SC) and @@ -4160,6 +4550,6 @@ r_sc_to_init_cmd_is_long = true; r_sc_to_init_cmd_wdata_high = m_cmd_sc_wdata_fifo.read(); - } - else + } + else { r_sc_to_init_cmd_is_long = false; @@ -4181,6 +4571,6 @@ r_sc_to_init_cmd_multi_req = true; r_sc_cpt = 0; - } - else // several copies + } + else // several copies { r_sc_fsm = SC_UPT_NEXT; @@ -4190,8 +4580,8 @@ if( m_debug_sc_fsm ) { - std::cout << " Send the first update request to INIT_CMD FSM " + std::cout << " Send the first update request to INIT_CMD FSM " << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() << " / wdata = " << std::hex << r_sc_wdata.read() - << " / srcid = " << std::dec << r_sc_copy.read() + << " / srcid = " << std::dec << r_sc_copy.read() << " / inst = " << std::dec << r_sc_copy_inst.read() << std::endl; } @@ -4201,5 +4591,5 @@ } ///////////////// - case SC_UPT_NEXT: // send a multi-update request to INIT_CMD FSM + case SC_UPT_NEXT: // send a multi-update request to INIT_CMD FSM { assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_SC) @@ -4224,11 +4614,11 @@ cmd_sc_fifo_get = true; r_sc_cpt = 0; - } - } + } + } #if DEBUG_MEMC_SC if( m_debug_sc_fsm ) { - std::cout << " Send the next update request to INIT_CMD FSM " + std::cout << " Send the next update request to INIT_CMD FSM " << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() << " / wdata = " << std::hex << r_sc_wdata.read() @@ -4240,25 +4630,25 @@ } ///////////////////// - case SC_BC_TRT_LOCK: // check the TRT to register a PUT transaction - { - if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) + case SC_BC_TRT_LOCK: // check the TRT to register a PUT transaction + { + if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) { if( !r_sc_to_ixr_cmd_req ) // we can transfer the request to IXR_CMD FSM { // fill the data buffer - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; for(size_t i = 0; i Register a broadcast inval transaction in UPT" - << " / nline = " << nline - << " / count = " << nb_copies - << " / upt_index = " << index << std::endl; + << " / nline = " << nline + << " / count = " << nb_copies + << " / upt_index = " << index << std::endl; } #endif @@ -4358,11 +4748,11 @@ // set TRT m_transaction_tab.set(r_sc_trt_index.read(), - false, // PUT request to XRAM + false, // PUT request to XRAM m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())], 0, 0, 0, - false, // not a processor read - 0, + false, // not a processor read + 0, 0, std::vector(m_words,0), @@ -4371,9 +4761,9 @@ // invalidate directory entry DirectoryEntry entry; - entry.valid = false; - entry.dirty = false; - entry.tag = 0; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; entry.is_cnt = false; - entry.lock = false; + entry.lock = false; entry.count = 0; entry.owner.srcid = 0; @@ -4383,6 +4773,6 @@ entry.owner.inst = false; entry.ptr = 0; - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t way = r_sc_way.read(); m_cache_directory.write(set, way, entry); @@ -4397,6 +4787,6 @@ } #endif - } - else + } + else { assert(false and "LOCK ERROR in SC_FSM, STATE = SC_BC_DIR_INVAL"); @@ -4408,5 +4798,5 @@ { if ( !r_sc_to_init_cmd_multi_req.read() && - !r_sc_to_init_cmd_brdcast_req.read()) + !r_sc_to_init_cmd_brdcast_req.read()) { r_sc_to_init_cmd_multi_req = false; @@ -4424,5 +4814,5 @@ case SC_BC_XRAM_REQ: // request the IXR FSM to start a put transaction { - if ( !r_sc_to_ixr_cmd_req ) + if ( !r_sc_to_ixr_cmd_req ) { r_sc_to_ixr_cmd_req = true; @@ -4442,6 +4832,6 @@ } #endif - } - else + } + else { std::cout << "MEM_CACHE, SC_BC_XRAM_REQ state : request should not have been previously set" @@ -4453,13 +4843,13 @@ case SC_RSP_FAIL: // request TGT_RSP FSM to send a failure response { - if( !r_sc_to_tgt_rsp_req ) - { - cmd_sc_fifo_get = true; + if( !r_sc_to_tgt_rsp_req ) + { + cmd_sc_fifo_get = true; r_sc_cpt = 0; - r_sc_to_tgt_rsp_req = true; - r_sc_to_tgt_rsp_data = 1; - r_sc_to_tgt_rsp_srcid = m_cmd_sc_srcid_fifo.read(); - r_sc_to_tgt_rsp_trdid = m_cmd_sc_trdid_fifo.read(); - r_sc_to_tgt_rsp_pktid = m_cmd_sc_pktid_fifo.read(); + r_sc_to_tgt_rsp_req = true; + r_sc_to_tgt_rsp_data = 1; + r_sc_to_tgt_rsp_srcid = m_cmd_sc_srcid_fifo.read(); + r_sc_to_tgt_rsp_trdid = m_cmd_sc_trdid_fifo.read(); + r_sc_to_tgt_rsp_pktid = m_cmd_sc_pktid_fifo.read(); r_sc_fsm = SC_IDLE; @@ -4476,13 +4866,13 @@ case SC_RSP_SUCCESS: // request TGT_RSP FSM to send a success response { - if( !r_sc_to_tgt_rsp_req ) + if( !r_sc_to_tgt_rsp_req ) { cmd_sc_fifo_get = true; r_sc_cpt = 0; - r_sc_to_tgt_rsp_req = true; - r_sc_to_tgt_rsp_data = 0; - r_sc_to_tgt_rsp_srcid = m_cmd_sc_srcid_fifo.read(); - r_sc_to_tgt_rsp_trdid = m_cmd_sc_trdid_fifo.read(); - r_sc_to_tgt_rsp_pktid = m_cmd_sc_pktid_fifo.read(); + r_sc_to_tgt_rsp_req = true; + r_sc_to_tgt_rsp_data = 0; + r_sc_to_tgt_rsp_srcid = m_cmd_sc_srcid_fifo.read(); + r_sc_to_tgt_rsp_trdid = m_cmd_sc_trdid_fifo.read(); + r_sc_to_tgt_rsp_pktid = m_cmd_sc_pktid_fifo.read(); r_sc_fsm = SC_IDLE; @@ -4499,5 +4889,5 @@ case SC_MISS_TRT_LOCK: // cache miss : request access to transaction Table { - if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) + if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) { size_t index = 0; @@ -4511,8 +4901,8 @@ if( m_debug_sc_fsm ) { - std::cout << " Check TRT state" + std::cout << " Check TRT state" << " / hit_read = " << hit_read << " / hit_write = " << hit_write - << " / wok = " << wok + << " / wok = " << wok << " / index = " << index << std::endl; } @@ -4522,6 +4912,6 @@ { r_sc_fsm = SC_WAIT; - } - else + } + else { r_sc_trt_index = index; @@ -4532,7 +4922,7 @@ } //////////////////// - case SC_MISS_TRT_SET: // register the GET transaction in TRT - { - if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) + case SC_MISS_TRT_SET: // register the GET transaction in TRT + { + if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) { std::vector be_vector; @@ -4540,6 +4930,6 @@ be_vector.clear(); data_vector.clear(); - for ( size_t i=0; i Register a GET transaction in TRT" << std::hex - << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] + << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] << " / trt_index = " << r_sc_trt_index.read() << std::endl; } @@ -4571,7 +4961,7 @@ } ////////////////////// - case SC_MISS_XRAM_REQ: // request the IXR_CMD FSM to fetch the missing line - { - if ( !r_sc_to_ixr_cmd_req ) + case SC_MISS_XRAM_REQ: // request the IXR_CMD FSM to fetch the missing line + { + if ( !r_sc_to_ixr_cmd_req ) { r_sc_to_ixr_cmd_req = true; @@ -4596,5 +4986,5 @@ ////////////////////////////////////////////////////////////////////////////// - // INIT_CMD FSM + // INIT_CMD FSM ////////////////////////////////////////////////////////////////////////////// // The INIT_CMD fsm controls the VCI CMD initiator port on the coherence @@ -4603,52 +4993,52 @@ // It implements a round-robin priority between the three possible client FSMs // XRAM_RSP, WRITE and SC. Each FSM can request two types of services: - // - r_xram_rsp_to_init_cmd_multi_req : multi-inval - // r_xram_rsp_to_init_cmd_brdcast_req : broadcast-inval - // - r_write_to_init_cmd_multi_req : multi-update - // r_write_to_init_cmd_brdcast_req : broadcast-inval - // - r_sc_to_init_cmd_multi_req : multi-update + // - r_xram_rsp_to_init_cmd_multi_req : multi-inval + // r_xram_rsp_to_init_cmd_brdcast_req : broadcast-inval + // - r_write_to_init_cmd_multi_req : multi-update + // r_write_to_init_cmd_brdcast_req : broadcast-inval + // - r_sc_to_init_cmd_multi_req : multi-update // r_sc_to_init_cmd_brdcast_req : broadcast-inval // - // An inval request is a single cell VCI write command containing the + // An inval request is a single cell VCI write command containing the // index of the line to be invalidated. - // An update request is a multi-cells VCI write command : The first cell - // contains the index of the cache line to be updated. The second cell contains + // An update request is a multi-cells VCI write command : The first cell + // contains the index of the cache line to be updated. The second cell contains // the index of the first modified word in the line. The following cells // contain the data. /////////////////////////////////////////////////////////////////////////////// - switch ( r_init_cmd_fsm.read() ) + switch ( r_init_cmd_fsm.read() ) { - //////////////////////// - case INIT_CMD_UPDT_IDLE: // XRAM_RSP FSM has highest priority + //////////////////////// + case INIT_CMD_UPDT_IDLE: // XRAM_RSP FSM has highest priority { if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() || - r_xram_rsp_to_init_cmd_multi_req.read() ) + r_xram_rsp_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_INVAL_NLINE; m_cpt_inval++; - } - else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) + } + else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) { r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST; m_cpt_inval++; - } + } else if ( m_write_to_init_cmd_inst_fifo.rok() || - r_write_to_init_cmd_multi_req.read() ) + r_write_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_UPDT_NLINE; m_cpt_update++; - } + } else if ( r_write_to_init_cmd_brdcast_req.read() ) { r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST; m_cpt_inval++; - } + } else if ( m_sc_to_init_cmd_inst_fifo.rok() || - r_sc_to_init_cmd_multi_req.read() ) + r_sc_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE; m_cpt_update++; - } + } else if( r_sc_to_init_cmd_brdcast_req.read() ) { @@ -4659,35 +5049,35 @@ } ///////////////////////// - case INIT_CMD_INVAL_IDLE: // WRITE FSM has highest priority + case INIT_CMD_INVAL_IDLE: // WRITE FSM has highest priority { if ( m_write_to_init_cmd_inst_fifo.rok() || - r_write_to_init_cmd_multi_req.read() ) + r_write_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_UPDT_NLINE; m_cpt_update++; - } + } else if ( r_write_to_init_cmd_brdcast_req.read() ) { r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST; m_cpt_inval++; - } + } else if ( m_sc_to_init_cmd_inst_fifo.rok() || - r_sc_to_init_cmd_multi_req.read() ) + r_sc_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE; m_cpt_update++; - } + } else if( r_sc_to_init_cmd_brdcast_req.read() ) { r_init_cmd_fsm = INIT_CMD_SC_BRDCAST; m_cpt_inval++; - } + } else if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() || - r_xram_rsp_to_init_cmd_multi_req.read() ) + r_xram_rsp_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_INVAL_NLINE; m_cpt_inval++; - } - else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) + } + else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) { r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST; @@ -4697,34 +5087,34 @@ } ////////////////////////// - case INIT_CMD_SC_UPDT_IDLE: // SC FSM has highest priority + case INIT_CMD_SC_UPDT_IDLE: // SC FSM has highest priority { if ( m_sc_to_init_cmd_inst_fifo.rok() || - r_sc_to_init_cmd_multi_req.read() ) + r_sc_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE; m_cpt_update++; - } + } else if( r_sc_to_init_cmd_brdcast_req.read() ) { r_init_cmd_fsm = INIT_CMD_SC_BRDCAST; m_cpt_inval++; - } + } else if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() || - r_xram_rsp_to_init_cmd_multi_req.read() ) + r_xram_rsp_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_INVAL_NLINE; m_cpt_inval++; - } - else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) + } + else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) { r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST; m_cpt_inval++; - } + } else if ( m_write_to_init_cmd_inst_fifo.rok() || - r_write_to_init_cmd_multi_req.read() ) + r_write_to_init_cmd_multi_req.read() ) { r_init_cmd_fsm = INIT_CMD_UPDT_NLINE; m_cpt_update++; - } + } else if ( r_write_to_init_cmd_brdcast_req.read() ) { @@ -4735,9 +5125,9 @@ } ////////////////////////// - case INIT_CMD_INVAL_NLINE: // send a multi-inval (from XRAM_RSP) + case INIT_CMD_INVAL_NLINE: // send a multi-inval (from XRAM_RSP) { if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ) { - if ( p_vci_ini.cmdack ) + if ( p_vci_ini.cmdack ) { m_cpt_inval_mult++; @@ -4745,6 +5135,6 @@ xram_rsp_to_init_cmd_fifo_get = true; } - } - else + } + else { if( r_xram_rsp_to_init_cmd_multi_req.read() ) r_xram_rsp_to_init_cmd_multi_req = false; @@ -4754,7 +5144,7 @@ } /////////////////////////// - case INIT_CMD_XRAM_BRDCAST: // send a broadcast-inval (from XRAM_RSP) - { - if ( p_vci_ini.cmdack ) + case INIT_CMD_XRAM_BRDCAST: // send a broadcast-inval (from XRAM_RSP) + { + if ( p_vci_ini.cmdack ) { m_cpt_inval_brdcast++; @@ -4765,7 +5155,7 @@ } //////////////////////////// - case INIT_CMD_WRITE_BRDCAST: // send a broadcast-inval (from WRITE FSM) - { - if( p_vci_ini.cmdack ) + case INIT_CMD_WRITE_BRDCAST: // send a broadcast-inval (from WRITE FSM) + { + if( p_vci_ini.cmdack ) { @@ -4773,5 +5163,5 @@ if( m_debug_init_cmd_fsm ) { - std::cout << " Broadcast-Inval for line " + std::cout << " Broadcast-Inval for line " << r_write_to_init_cmd_nline.read() << std::endl; } @@ -4786,5 +5176,5 @@ case INIT_CMD_UPDT_NLINE: // send nline for a multi-update (from WRITE FSM) { - if ( m_write_to_init_cmd_inst_fifo.rok() ) + if ( m_write_to_init_cmd_inst_fifo.rok() ) { if ( p_vci_ini.cmdack ) @@ -4794,6 +5184,6 @@ // write_to_init_cmd_fifo_get = true; } - } - else + } + else { if ( r_write_to_init_cmd_multi_req.read() ) r_write_to_init_cmd_multi_req = false; @@ -4812,12 +5202,12 @@ case INIT_CMD_UPDT_DATA: // send the data for a multi-update (from WRITE FSM) { - if ( p_vci_ini.cmdack ) - { - if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ) + if ( p_vci_ini.cmdack ) + { + if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ) { r_init_cmd_fsm = INIT_CMD_UPDT_NLINE; write_to_init_cmd_fifo_get = true; - } - else + } + else { r_init_cmd_cpt = r_init_cmd_cpt.read() + 1; @@ -4827,7 +5217,7 @@ } ///////////////////////// - case INIT_CMD_SC_BRDCAST: // send a broadcast-inval (from SC FSM) - { - if( p_vci_ini.cmdack ) + case INIT_CMD_SC_BRDCAST: // send a broadcast-inval (from SC FSM) + { + if( p_vci_ini.cmdack ) { m_cpt_inval_brdcast++; @@ -4847,6 +5237,6 @@ r_init_cmd_fsm = INIT_CMD_SC_UPDT_INDEX; } - } - else + } + else { if( r_sc_to_init_cmd_multi_req.read() ) r_sc_to_init_cmd_multi_req = false; @@ -4862,13 +5252,13 @@ } /////////////////////////// - case INIT_CMD_SC_UPDT_DATA: // send first data for a multi-update (from SC FSM) - { - if ( p_vci_ini.cmdack ) + case INIT_CMD_SC_UPDT_DATA: // send first data for a multi-update (from SC FSM) + { + if ( p_vci_ini.cmdack ) { if ( r_sc_to_init_cmd_is_long.read() ) { r_init_cmd_fsm = INIT_CMD_SC_UPDT_DATA_HIGH; - } - else + } + else { sc_to_init_cmd_fifo_get = true; @@ -4881,5 +5271,5 @@ case INIT_CMD_SC_UPDT_DATA_HIGH: // send second data for a multi-update (from SC FSM) { - if ( p_vci_ini.cmdack ) + if ( p_vci_ini.cmdack ) { sc_to_init_cmd_fifo_get = true; @@ -4891,5 +5281,5 @@ ///////////////////////////////////////////////////////////////////// - // TGT_RSP FSM + // TGT_RSP FSM ///////////////////////////////////////////////////////////////////// // The TGT_RSP fsm sends the responses on the VCI target port @@ -4904,12 +5294,12 @@ ///////////////////////////////////////////////////////////////////// - switch ( r_tgt_rsp_fsm.read() ) + switch ( r_tgt_rsp_fsm.read() ) { /////////////////////// - case TGT_RSP_READ_IDLE: // write requests have the highest priority + case TGT_RSP_READ_IDLE: // write requests have the highest priority { if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; - else if ( r_xram_rsp_to_tgt_rsp_req ) + else if ( r_xram_rsp_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_XRAM; @@ -4918,5 +5308,5 @@ else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if ( r_read_to_tgt_rsp_req ) + else if ( r_read_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_READ; @@ -4926,8 +5316,8 @@ } //////////////////////// - case TGT_RSP_WRITE_IDLE: // sc requests have the highest priority + case TGT_RSP_WRITE_IDLE: // sc requests have the highest priority { if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; - else if ( r_xram_rsp_to_tgt_rsp_req ) + else if ( r_xram_rsp_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_XRAM; @@ -4936,5 +5326,5 @@ else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if ( r_read_to_tgt_rsp_req ) + else if ( r_read_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_READ; @@ -4946,7 +5336,7 @@ } /////////////////////// - case TGT_RSP_SC_IDLE: // xram_rsp requests have the highest priority - { - if ( r_xram_rsp_to_tgt_rsp_req ) + case TGT_RSP_SC_IDLE: // xram_rsp requests have the highest priority + { + if ( r_xram_rsp_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_XRAM; @@ -4955,5 +5345,5 @@ else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if ( r_read_to_tgt_rsp_req ) + else if ( r_read_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_READ; @@ -4965,10 +5355,10 @@ } /////////////////////// - case TGT_RSP_XRAM_IDLE: // init requests have the highest priority + case TGT_RSP_XRAM_IDLE: // init requests have the highest priority { if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if ( r_read_to_tgt_rsp_req ) + else if ( r_read_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_READ; @@ -4977,5 +5367,5 @@ else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; - else if ( r_xram_rsp_to_tgt_rsp_req ) + else if ( r_xram_rsp_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_XRAM; @@ -4985,8 +5375,8 @@ } /////////////////////// - case TGT_RSP_INIT_IDLE: // cleanup requests have the highest priority + case TGT_RSP_INIT_IDLE: // cleanup requests have the highest priority { if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if ( r_read_to_tgt_rsp_req ) + else if ( r_read_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_READ; @@ -4995,5 +5385,5 @@ else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; - else if ( r_xram_rsp_to_tgt_rsp_req ) + else if ( r_xram_rsp_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_XRAM; @@ -5004,7 +5394,7 @@ } /////////////////////// - case TGT_RSP_CLEANUP_IDLE: // read requests have the highest priority - { - if ( r_read_to_tgt_rsp_req ) + case TGT_RSP_CLEANUP_IDLE: // read requests have the highest priority + { + if ( r_read_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_READ; @@ -5013,5 +5403,5 @@ else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; - else if ( r_xram_rsp_to_tgt_rsp_req ) + else if ( r_xram_rsp_to_tgt_rsp_req ) { r_tgt_rsp_fsm = TGT_RSP_XRAM; @@ -5023,7 +5413,7 @@ } ////////////////// - case TGT_RSP_READ: // send the response to a read - { - if ( p_vci_tgt.rspack ) + case TGT_RSP_READ: // send the response to a read + { + if ( p_vci_tgt.rspack ) { @@ -5038,10 +5428,10 @@ } #endif - if ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ) + if ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ) { r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; r_read_to_tgt_rsp_req = false; - } - else + } + else { r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; @@ -5051,7 +5441,7 @@ } /////////////////// - case TGT_RSP_WRITE: // send the write acknowledge - { - if ( p_vci_tgt.rspack ) + case TGT_RSP_WRITE: // send the write acknowledge + { + if ( p_vci_tgt.rspack ) { @@ -5070,7 +5460,7 @@ } /////////////////// - case TGT_RSP_CLEANUP: // pas clair pour moi (AG) - { - if ( p_vci_tgt.rspack ) + case TGT_RSP_CLEANUP: // pas clair pour moi (AG) + { + if ( p_vci_tgt.rspack ) { @@ -5089,7 +5479,7 @@ } ////////////////// - case TGT_RSP_SC: // send one atomic word response - { - if ( p_vci_tgt.rspack ) + case TGT_RSP_SC: // send one atomic word response + { + if ( p_vci_tgt.rspack ) { @@ -5109,7 +5499,7 @@ /////////////////////// - case TGT_RSP_XRAM: // send the response after XRAM access - { - if ( p_vci_tgt.rspack ) + case TGT_RSP_XRAM: // send the response after XRAM access + { + if ( p_vci_tgt.rspack ) { @@ -5124,12 +5514,12 @@ } #endif - if ( (r_tgt_rsp_cpt.read() == + if ( (r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) - || r_xram_rsp_to_tgt_rsp_rerror.read() ) + || r_xram_rsp_to_tgt_rsp_rerror.read() ) { r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; r_xram_rsp_to_tgt_rsp_req = false; - } - else + } + else { r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; @@ -5139,7 +5529,7 @@ } ////////////////// - case TGT_RSP_INIT: // send the write response after coherence transaction - { - if ( p_vci_tgt.rspack ) + case TGT_RSP_INIT: // send the write response after coherence transaction + { + if ( p_vci_tgt.rspack ) { @@ -5160,8 +5550,8 @@ //////////////////////////////////////////////////////////////////////////////////// - // ALLOC_UPT FSM + // ALLOC_UPT FSM //////////////////////////////////////////////////////////////////////////////////// // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT). - // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP > CLEANUP + // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP > CLEANUP // - The WRITE FSM initiates update transactions and sets new entry in UPT. // - The XRAM_RSP FSM initiates inval transactions and sets new entry in UPT. @@ -5171,18 +5561,25 @@ ///////////////////////////////////////////////////////////////////////////////////// - switch ( r_alloc_upt_fsm.read() ) + switch ( r_alloc_upt_fsm.read() ) { //////////////////////// case ALLOC_UPT_INIT_RSP: - if ( (r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK) && - (r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR) ) - { - if ((r_write_fsm.read() == WRITE_UPT_LOCK) || - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_WRITE; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if ((r_sc_fsm.read() == SC_UPT_LOCK) || - (r_sc_fsm.read() == SC_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_SC; + if (( r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK ) && + ( r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR )) + { + if (( r_write_fsm.read() == WRITE_UPT_LOCK ) || + ( r_write_fsm.read() == WRITE_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if ( r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; + + else if ( r_cleanup_fsm.read() == CLEANUP_UPT_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; + + else if (( r_sc_fsm.read() == SC_UPT_LOCK ) || + ( r_sc_fsm.read() == SC_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_SC; } break; @@ -5190,12 +5587,19 @@ ///////////////////// case ALLOC_UPT_WRITE: - if ( (r_write_fsm.read() != WRITE_UPT_LOCK) && - (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) - { - if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if ((r_sc_fsm.read() == SC_UPT_LOCK) || - (r_sc_fsm.read() == SC_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_SC; - else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP; + if (( r_write_fsm.read() != WRITE_UPT_LOCK ) && + ( r_write_fsm.read() != WRITE_BC_UPT_LOCK )) + { + if ( r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; + + else if ( r_cleanup_fsm.read() == CLEANUP_UPT_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; + + else if (( r_sc_fsm.read() == SC_UPT_LOCK ) || + ( r_sc_fsm.read() == SC_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_SC; + + else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP; } break; @@ -5203,12 +5607,19 @@ //////////////////////// case ALLOC_UPT_XRAM_RSP: - if (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) - { - if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if ((r_sc_fsm.read() == SC_UPT_LOCK) || - (r_sc_fsm.read() == SC_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_SC; - else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP; - else if ((r_write_fsm.read() == WRITE_UPT_LOCK) || - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_WRITE; + if (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) + { + if ( r_cleanup_fsm.read() == CLEANUP_UPT_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; + + else if (( r_sc_fsm.read() == SC_UPT_LOCK ) || + ( r_sc_fsm.read() == SC_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_SC; + + else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP; + + else if (( r_write_fsm.read() == WRITE_UPT_LOCK ) || + ( r_write_fsm.read() == WRITE_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; } break; @@ -5218,23 +5629,37 @@ if(r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) { - if ((r_sc_fsm.read() == SC_UPT_LOCK) || - (r_sc_fsm.read() == SC_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_SC; - else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP; - else if ((r_write_fsm.read() == WRITE_UPT_LOCK) || - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_WRITE; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; + if (( r_sc_fsm.read() == SC_UPT_LOCK ) || + ( r_sc_fsm.read() == SC_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_SC; + + else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP; + + else if (( r_write_fsm.read() == WRITE_UPT_LOCK ) || + ( r_write_fsm.read() == WRITE_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if ( r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; } break; - + ////////////////////////// case ALLOC_UPT_SC: - if( (r_sc_fsm.read() != SC_UPT_LOCK) && - (r_sc_fsm.read() != SC_BC_UPT_LOCK)) - { - if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP; - else if ((r_write_fsm.read() == WRITE_UPT_LOCK) || - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_WRITE; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; + if (( r_sc_fsm.read() != SC_UPT_LOCK ) && + ( r_sc_fsm.read() != SC_BC_UPT_LOCK )) + { + if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP; + + else if (( r_write_fsm.read() == WRITE_UPT_LOCK ) || + ( r_write_fsm.read() == WRITE_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if ( r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; + + else if ( r_cleanup_fsm.read() == CLEANUP_UPT_LOCK ) + r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; } break; @@ -5243,5 +5668,5 @@ //////////////////////////////////////////////////////////////////////////////////// - // ALLOC_DIR FSM + // ALLOC_DIR FSM //////////////////////////////////////////////////////////////////////////////////// // The ALLOC_DIR FSM allocates the access to the directory and @@ -5251,22 +5676,43 @@ ///////////////////////////////////////////////////////////////////////////////////// - switch ( r_alloc_dir_fsm.read() ) + switch ( r_alloc_dir_fsm.read() ) { + case ALLOC_DIR_RESET: + // Initializes the directory one SET each cycle. All the WAYS of a SET are + // initialize in parallel + + r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1); + + if (r_alloc_dir_reset_cpt.read() == (m_sets - 1)) { + m_cache_directory.init(); + + r_alloc_dir_fsm = ALLOC_DIR_READ; + } + break; + //////////////////// case ALLOC_DIR_READ: - if ( ( (r_read_fsm.read() != READ_DIR_LOCK) && - (r_read_fsm.read() != READ_TRT_LOCK) && - (r_read_fsm.read() != READ_HEAP_LOCK)) + if ((( r_read_fsm.read() != READ_DIR_REQ ) && + ( r_read_fsm.read() != READ_DIR_LOCK ) && + ( r_read_fsm.read() != READ_TRT_LOCK ) && + ( r_read_fsm.read() != READ_HEAP_REQ )) || - ( (r_read_fsm.read() == READ_HEAP_LOCK) && - (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) ) + (( r_read_fsm.read() == READ_HEAP_REQ ) && + ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ )) || - ( (r_read_fsm.read() == READ_TRT_LOCK) && - (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) ) ) - { - if (r_write_fsm.read() == WRITE_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_WRITE; - else if (r_sc_fsm.read() == SC_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_SC; - else if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + (( r_read_fsm.read() == READ_TRT_LOCK ) && + ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ))) + { + if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_sc_fsm.read() == SC_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_SC; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; } break; @@ -5274,23 +5720,31 @@ ///////////////////// case ALLOC_DIR_WRITE: - if ( ((r_write_fsm.read() != WRITE_DIR_LOCK) && - (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) && - (r_write_fsm.read() != WRITE_DIR_READ) && - (r_write_fsm.read() != WRITE_DIR_HIT) && - (r_write_fsm.read() != WRITE_BC_TRT_LOCK) && - (r_write_fsm.read() != WRITE_BC_UPT_LOCK) && - (r_write_fsm.read() != WRITE_UPT_LOCK) && - (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) + if ((( r_write_fsm.read() != WRITE_DIR_REQ ) && + ( r_write_fsm.read() != WRITE_DIR_LOCK ) && + ( r_write_fsm.read() != WRITE_DIR_READ ) && + ( r_write_fsm.read() != WRITE_DIR_HIT ) && + ( r_write_fsm.read() != WRITE_BC_TRT_LOCK ) && + ( r_write_fsm.read() != WRITE_BC_UPT_LOCK ) && + ( r_write_fsm.read() != WRITE_MISS_TRT_LOCK ) && + ( r_write_fsm.read() != WRITE_UPT_LOCK ) && + ( r_write_fsm.read() != WRITE_UPT_HEAP_LOCK )) || - ( (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) && - (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) ) + (( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK ) && + ( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE )) || - ( (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) && - (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) ) ) - { - if (r_sc_fsm.read() == SC_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_SC; - else if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; - else if (r_read_fsm.read() == READ_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_READ; + (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) && + ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ))) + { + if ( r_sc_fsm.read() == SC_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_SC; + + else if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if ( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if ( r_read_fsm.read() == READ_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_READ; } break; @@ -5298,23 +5752,31 @@ //////////////////// case ALLOC_DIR_SC: - if ( ((r_sc_fsm.read() != SC_DIR_LOCK) && - (r_sc_fsm.read() != SC_DIR_HIT_READ ) && - (r_sc_fsm.read() != SC_DIR_HIT_WRITE ) && -// (r_sc_fsm.read() != SC_MISS_TRT_LOCK ) && - (r_sc_fsm.read() != SC_BC_TRT_LOCK) && - (r_sc_fsm.read() != SC_BC_UPT_LOCK) && - (r_sc_fsm.read() != SC_UPT_LOCK) && - (r_sc_fsm.read() != SC_UPT_HEAP_LOCK)) + if ((( r_sc_fsm.read() != SC_DIR_REQ ) && + ( r_sc_fsm.read() != SC_DIR_LOCK ) && + ( r_sc_fsm.read() != SC_DIR_HIT_READ ) && + ( r_sc_fsm.read() != SC_DIR_HIT_WRITE ) && + ( r_sc_fsm.read() != SC_BC_TRT_LOCK ) && + ( r_sc_fsm.read() != SC_BC_UPT_LOCK ) && + ( r_sc_fsm.read() != SC_MISS_TRT_LOCK ) && + ( r_sc_fsm.read() != SC_UPT_LOCK ) && + ( r_sc_fsm.read() != SC_UPT_HEAP_LOCK )) || - ( (r_sc_fsm.read() == SC_UPT_HEAP_LOCK) && - (r_alloc_heap_fsm.read() == ALLOC_HEAP_SC) ) + (( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) && + ( r_alloc_heap_fsm.read() == ALLOC_HEAP_SC )) || - ( (r_sc_fsm.read() == SC_MISS_TRT_LOCK ) && - (r_alloc_trt_fsm.read() == ALLOC_TRT_SC) ) ) - { - if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; - else if (r_read_fsm.read() == READ_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_READ; - else if (r_write_fsm.read() == WRITE_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_WRITE; + (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) && + ( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ))) + { + if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if ( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if ( r_read_fsm.read() == READ_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if ( r_write_fsm.read() == WRITE_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; } break; @@ -5322,23 +5784,40 @@ /////////////////////// case ALLOC_DIR_CLEANUP: - if ( (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) && - (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) ) - { - if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; - else if (r_read_fsm.read() == READ_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_READ; - else if (r_write_fsm.read() == WRITE_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_WRITE; - else if (r_sc_fsm.read() == SC_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_SC; + if (( r_cleanup_fsm.read() != CLEANUP_DIR_REQ ) && + ( r_cleanup_fsm.read() != CLEANUP_DIR_LOCK ) && + ( r_cleanup_fsm.read() != CLEANUP_HEAP_REQ ) && + ( r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK )) + { + if ( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if ( r_read_fsm.read() == READ_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if ( r_write_fsm.read() == WRITE_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if ( r_sc_fsm.read() == SC_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_SC; } break; + //////////////////////// case ALLOC_DIR_XRAM_RSP: - if ( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) && - (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) && - (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) - { - if (r_read_fsm.read() == READ_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_READ; - else if (r_write_fsm.read() == WRITE_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_WRITE; - else if (r_sc_fsm.read() == SC_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_SC; - else if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + if (( r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK ) && + ( r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY ) && + ( r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK )) + { + if ( r_read_fsm.read() == READ_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if ( r_write_fsm.read() == WRITE_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if ( r_sc_fsm.read() == SC_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_SC; + + else if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; } break; @@ -5347,5 +5826,5 @@ //////////////////////////////////////////////////////////////////////////////////// - // ALLOC_TRT FSM + // ALLOC_TRT FSM //////////////////////////////////////////////////////////////////////////////////// // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer) @@ -5355,72 +5834,118 @@ /////////////////////////////////////////////////////////////////////////////////// - switch (r_alloc_trt_fsm) + switch ( r_alloc_trt_fsm.read() ) { - //////////////////// case ALLOC_TRT_READ: - if ( r_read_fsm.read() != READ_TRT_LOCK ) - { - if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) || - (r_sc_fsm.read() == SC_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_SC; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) ) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + if ( r_read_fsm.read() != READ_TRT_LOCK ) + { + if (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) || + ( r_write_fsm.read() == WRITE_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) || + ( r_sc_fsm.read() == SC_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_SC; + + else if (( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) && + ( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP )) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if (( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE ) || + ( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ )) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; } break; - ///////////////////// + + ///////////////////// case ALLOC_TRT_WRITE: - if ( (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) && - (r_write_fsm.read() != WRITE_BC_TRT_LOCK) && - (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) - { - if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) || - (r_sc_fsm.read() == SC_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_SC; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if (r_read_fsm.read() == READ_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_READ; + if (( r_write_fsm.read() != WRITE_MISS_TRT_LOCK ) && + ( r_write_fsm.read() != WRITE_BC_TRT_LOCK ) && + ( r_write_fsm.read() != WRITE_BC_UPT_LOCK )) + { + if (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) || + ( r_sc_fsm.read() == SC_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_SC; + + else if (( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) && + ( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP )) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if (( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE ) || + ( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ )) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if ( r_read_fsm.read() == READ_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_READ; } break; - //////////////////// + + //////////////////// case ALLOC_TRT_SC: - if ( (r_sc_fsm.read() != SC_MISS_TRT_LOCK) && - (r_sc_fsm.read() != SC_BC_TRT_LOCK) && - (r_sc_fsm.read() != SC_BC_UPT_LOCK)) - { - if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if (r_read_fsm.read() == READ_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_READ; - else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_WRITE; + if (( r_sc_fsm.read() != SC_MISS_TRT_LOCK ) && + ( r_sc_fsm.read() != SC_BC_TRT_LOCK ) && + ( r_sc_fsm.read() != SC_BC_UPT_LOCK )) + { + if (( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) && + ( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP )) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if (( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE ) || + ( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ )) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if ( r_read_fsm.read() == READ_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) || + ( r_write_fsm.read() == WRITE_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; } break; - //////////////////////// + + //////////////////////// case ALLOC_TRT_XRAM_RSP: - if ( (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) && - (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) && - (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) { - if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if (r_read_fsm.read() == READ_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_READ; - else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) || - (r_sc_fsm.read() == SC_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_SC; + if ((( r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK ) || + ( r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP )) && + ( r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY ) && + ( r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT ) && + ( r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK )) + { + if (( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE ) || + ( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ )) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if ( r_read_fsm.read() == READ_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) || + ( r_write_fsm.read() == WRITE_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) || + ( r_sc_fsm.read() == SC_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_SC; } break; - //////////////////////// + + //////////////////////// case ALLOC_TRT_IXR_RSP: - if ( (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) && - (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) { - if (r_read_fsm.read() == READ_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_READ; - else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if ((r_sc_fsm.read() == SC_MISS_TRT_LOCK) || - (r_sc_fsm.read() == SC_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_SC; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + if (( r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE ) && + ( r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ )) + { + if ( r_read_fsm.read() == READ_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) || + ( r_write_fsm.read() == WRITE_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) || + ( r_sc_fsm.read() == SC_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_SC; + + else if (( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) && + ( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP )) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; } break; @@ -5429,5 +5954,5 @@ //////////////////////////////////////////////////////////////////////////////////// - // ALLOC_HEAP FSM + // ALLOC_HEAP FSM //////////////////////////////////////////////////////////////////////////////////// // The ALLOC_HEAP FSM allocates the access to the heap @@ -5437,15 +5962,36 @@ ///////////////////////////////////////////////////////////////////////////////////// - switch ( r_alloc_heap_fsm.read() ) + switch ( r_alloc_heap_fsm.read() ) { //////////////////// + case ALLOC_HEAP_RESET: + // Initializes the heap one ENTRY each cycle. + + r_alloc_heap_reset_cpt.write(r_alloc_heap_reset_cpt.read() + 1); + + if(r_alloc_heap_reset_cpt.read() == (m_heap_size-1)) { + m_heap.init(); + + r_alloc_heap_fsm = ALLOC_HEAP_READ; + } + break; + + //////////////////// case ALLOC_HEAP_READ: - if ( (r_read_fsm.read() != READ_HEAP_LOCK) && - (r_read_fsm.read() != READ_HEAP_ERASE) ) - { - if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; - else if (r_sc_fsm.read() == SC_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_SC; - else if (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + if (( r_read_fsm.read() != READ_HEAP_REQ ) && + ( r_read_fsm.read() != READ_HEAP_LOCK ) && + ( r_read_fsm.read() != READ_HEAP_ERASE )) + { + if ( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if ( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_SC; + + else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if ( r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; } break; @@ -5453,12 +5999,19 @@ ///////////////////// case ALLOC_HEAP_WRITE: - if ( (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) && - (r_write_fsm.read() != WRITE_UPT_REQ) && - (r_write_fsm.read() != WRITE_UPT_NEXT) ) - { - if (r_sc_fsm.read() == SC_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_SC; - else if (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; - else if (r_read_fsm.read() == READ_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_READ; + if (( r_write_fsm.read() != WRITE_UPT_HEAP_LOCK ) && + ( r_write_fsm.read() != WRITE_UPT_REQ ) && + ( r_write_fsm.read() != WRITE_UPT_NEXT )) + { + if ( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_SC; + + else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if ( r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if ( r_read_fsm.read() == READ_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; } break; @@ -5466,12 +6019,19 @@ //////////////////// case ALLOC_HEAP_SC: - if ( (r_sc_fsm.read() != SC_UPT_HEAP_LOCK) && - (r_sc_fsm.read() != SC_UPT_REQ ) && - (r_sc_fsm.read() != SC_UPT_NEXT) ) - { - if (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; - else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; - else if (r_read_fsm.read() == READ_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_READ; - else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + if (( r_sc_fsm.read() != SC_UPT_HEAP_LOCK ) && + ( r_sc_fsm.read() != SC_UPT_REQ ) && + ( r_sc_fsm.read() != SC_UPT_NEXT )) + { + if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if ( r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if ( r_read_fsm.read() == READ_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if ( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; } break; @@ -5479,22 +6039,40 @@ /////////////////////// case ALLOC_HEAP_CLEANUP: - if ( (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) && - (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH)&& - (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN) ) - { - if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; - else if (r_read_fsm.read() == READ_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_READ; - else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; - else if (r_sc_fsm.read() == SC_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_SC; + if (( r_cleanup_fsm.read() != CLEANUP_HEAP_REQ ) && + ( r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK ) && + ( r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH ) && + ( r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN )) + { + if ( r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if ( r_read_fsm.read() == READ_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if ( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if ( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_SC; } break; + //////////////////////// case ALLOC_HEAP_XRAM_RSP: - if ( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE ) - { - if (r_read_fsm.read() == READ_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_READ; - else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; - else if (r_sc_fsm.read() == SC_UPT_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_SC; - else if (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + if (( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ ) && + ( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE )) + { + if ( r_read_fsm.read() == READ_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if ( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if ( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_SC; + + else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + } break; @@ -5504,5 +6082,5 @@ //////////////////////////////////////////////////////////////////////////////////// - // TGT_CMD to READ FIFO + // TGT_CMD to READ FIFO //////////////////////////////////////////////////////////////////////////////////// @@ -5531,5 +6109,5 @@ } ///////////////////////////////////////////////////////////////////// - // TGT_CMD to WRITE FIFO + // TGT_CMD to WRITE FIFO ///////////////////////////////////////////////////////////////////// @@ -5564,5 +6142,5 @@ } //////////////////////////////////////////////////////////////////////////////////// - // TGT_CMD to SC FIFO + // TGT_CMD to SC FIFO //////////////////////////////////////////////////////////////////////////////////// @@ -5570,5 +6148,5 @@ if ( cmd_sc_fifo_get ) { m_cmd_sc_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read())); - m_cmd_sc_eop_fifo.put_and_get(p_vci_tgt.eop.read()); + m_cmd_sc_eop_fifo.put_and_get(p_vci_tgt.eop.read()); m_cmd_sc_srcid_fifo.put_and_get(p_vci_tgt.srcid.read()); m_cmd_sc_trdid_fifo.put_and_get(p_vci_tgt.trdid.read()); @@ -5577,5 +6155,5 @@ } else { m_cmd_sc_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read())); - m_cmd_sc_eop_fifo.simple_put(p_vci_tgt.eop.read()); + m_cmd_sc_eop_fifo.simple_put(p_vci_tgt.eop.read()); m_cmd_sc_srcid_fifo.simple_put(p_vci_tgt.srcid.read()); m_cmd_sc_trdid_fifo.simple_put(p_vci_tgt.trdid.read()); @@ -5594,5 +6172,5 @@ } //////////////////////////////////////////////////////////////////////////////////// - // WRITE to INIT_CMD FIFO + // WRITE to INIT_CMD FIFO //////////////////////////////////////////////////////////////////////////////////// @@ -5621,5 +6199,5 @@ } //////////////////////////////////////////////////////////////////////////////////// - // XRAM_RSP to INIT_CMD FIFO + // XRAM_RSP to INIT_CMD FIFO //////////////////////////////////////////////////////////////////////////////////// @@ -5648,5 +6226,5 @@ } //////////////////////////////////////////////////////////////////////////////////// - // SC to INIT_CMD FIFO + // SC to INIT_CMD FIFO //////////////////////////////////////////////////////////////////////////////////// @@ -5704,5 +6282,5 @@ p_vci_ixr.trdid = r_read_to_ixr_cmd_trdid.read(); p_vci_ixr.eop = true; - } + } else if ( r_ixr_cmd_fsm.read() == IXR_CMD_SC_NLINE ) { if(r_sc_to_ixr_cmd_write.read()){ @@ -5723,5 +6301,5 @@ p_vci_ixr.eop = true; } - } + } else if ( r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE ) { if(r_write_to_ixr_cmd_write.read()){ @@ -5742,5 +6320,5 @@ p_vci_ixr.eop = true; } - } + } else if ( r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA ) { p_vci_ixr.cmd = vci_param::CMD_WRITE; @@ -5757,5 +6335,5 @@ p_vci_ixr.wdata = 0; p_vci_ixr.trdid = 0; - p_vci_ixr.eop = false; + p_vci_ixr.eop = false; } @@ -5765,5 +6343,5 @@ if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) && - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) ) p_vci_ixr.rspack = true; else p_vci_ixr.rspack = false; @@ -5808,5 +6386,5 @@ p_vci_tgt.rtrdid = 0; p_vci_tgt.rerror = 0; - p_vci_tgt.reop = false; + p_vci_tgt.reop = false; break; case TGT_RSP_READ: @@ -5825,5 +6403,5 @@ p_vci_tgt.rtrdid = r_write_to_tgt_rsp_trdid.read(); p_vci_tgt.rpktid = r_write_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); + p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); p_vci_tgt.reop = true; break; @@ -5853,7 +6431,7 @@ p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); p_vci_tgt.rerror = r_xram_rsp_to_tgt_rsp_rerror.read(); - p_vci_tgt.reop = (( r_tgt_rsp_cpt.read() - == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) - || r_xram_rsp_to_tgt_rsp_rerror.read()); + p_vci_tgt.reop = (( r_tgt_rsp_cpt.read() + == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) + || r_xram_rsp_to_tgt_rsp_rerror.read()); break; case TGT_RSP_INIT: @@ -5864,5 +6442,5 @@ p_vci_tgt.rpktid = r_init_rsp_to_tgt_rsp_pktid.read(); p_vci_tgt.rerror = 0; // Can be a SC rsp - p_vci_tgt.reop = true; + p_vci_tgt.reop = true; break; } // end switch r_tgt_rsp_fsm @@ -6143,4 +6721,3 @@ // End: -// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 - +// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2