- Timestamp:
- Dec 10, 2012, 6:24:37 PM (12 years ago)
- Location:
- trunk/modules/vci_mem_cache_v4/caba/source
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
r212 r283 7 7 #include "arithmetics.h" 8 8 9 #define L1_MULTI_CACHE 19 #define L1_MULTI_CACHE 0 10 10 //#define RANDOM_EVICTION 11 11 -
trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
r273 r283 529 529 GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type 530 530 GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids 531 #if L1_MULTI_CACHE 531 532 GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids 533 #endif 532 534 533 535 // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry) … … 640 642 GenericFifo<bool> m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type 641 643 GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo; // fifo for srcids 644 #if L1_MULTI_CACHE 642 645 GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids 646 #endif 643 647 644 648 // Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry) … … 696 700 GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type 697 701 GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids 702 #if L1_MULTI_CACHE 698 703 GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids 704 #endif 699 705 700 706 // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) -
trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r277 r283 6487 6487 p_vci_ini.plen = 4; 6488 6488 p_vci_ini.trdid = r_xram_rsp_to_init_cmd_trdid.read(); 6489 #if L1_MULTI_CACHE 6489 6490 p_vci_ini.pktid = m_xram_rsp_to_init_cmd_cache_id_fifo.read(); 6491 #endif 6490 6492 p_vci_ini.eop = true; 6491 6493 break; … … 6531 6533 p_vci_ini.eop = false; 6532 6534 p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); 6535 #if L1_MULTI_CACHE 6533 6536 p_vci_ini.pktid = m_write_to_init_cmd_cache_id_fifo.read(); 6537 #endif 6534 6538 break; 6535 6539 case INIT_CMD_UPDT_INDEX: … … 6547 6551 p_vci_ini.plen = 4 * (r_write_to_init_cmd_count.read() + 2); 6548 6552 p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); 6553 #if L1_MULTI_CACHE 6549 6554 p_vci_ini.pktid = m_write_to_init_cmd_cache_id_fifo.read(); 6555 #endif 6550 6556 p_vci_ini.eop = false; 6551 6557 break; … … 6566 6572 p_vci_ini.plen = 4 * (r_write_to_init_cmd_count.read() + 2); 6567 6573 p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); 6574 #if L1_MULTI_CACHE 6568 6575 p_vci_ini.pktid = m_write_to_init_cmd_cache_id_fifo.read(); 6576 #endif 6569 6577 p_vci_ini.eop = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ); 6570 6578 break; … … 6603 6611 p_vci_ini.eop = false; 6604 6612 p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); 6613 #if L1_MULTI_CACHE 6605 6614 p_vci_ini.pktid = m_sc_to_init_cmd_cache_id_fifo.read(); 6615 #endif 6606 6616 break; 6607 6617 case INIT_CMD_SC_UPDT_INDEX: … … 6623 6633 } 6624 6634 p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); 6635 #if L1_MULTI_CACHE 6625 6636 p_vci_ini.pktid = m_sc_to_init_cmd_cache_id_fifo.read(); 6637 #endif 6626 6638 p_vci_ini.eop = false; 6627 6639 break; … … 6639 6651 p_vci_ini.be = 0xF; 6640 6652 p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); 6653 #if L1_MULTI_CACHE 6641 6654 p_vci_ini.pktid = m_sc_to_init_cmd_cache_id_fifo.read(); 6655 #endif 6642 6656 if(r_sc_to_init_cmd_is_long.read()){ 6643 6657 p_vci_ini.plen = 4 * 4; … … 6662 6676 p_vci_ini.plen = 4 * 4; 6663 6677 p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); 6678 #if L1_MULTI_CACHE 6664 6679 p_vci_ini.pktid = m_sc_to_init_cmd_cache_id_fifo.read(); 6680 #endif 6665 6681 p_vci_ini.eop = true; 6666 6682 break;
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