Index: trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h (revision 283) +++ trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h (revision 284) @@ -7,5 +7,11 @@ #include "arithmetics.h" +// !!! +// The L1_MULTI_CACHE mechanism does no longer work with the new pktid encoding +// of TSAR. Turning the define below to a non null value will cause the memcache +// to behave in an unpredicted way. +// TODO Either remove the mechanism from the mem cache or update its behaviour. #define L1_MULTI_CACHE 0 + //#define RANDOM_EVICTION Index: trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 283) +++ trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 284) @@ -27,4 +27,5 @@ * Maintainers: alain eric.guthmuller@polytechnique.edu * cesar.fuguet-tortolero@lip6.fr + * alexandre.joannou@lip6.fr * * Modifications done by Christophe Choichillon on the 7/04/2009: @@ -80,5 +81,5 @@ TGT_CMD_READ, TGT_CMD_WRITE, - TGT_CMD_ATOMIC + TGT_CMD_CAS }; @@ -87,5 +88,5 @@ TGT_RSP_READ_IDLE, TGT_RSP_WRITE_IDLE, - TGT_RSP_SC_IDLE, + TGT_RSP_CAS_IDLE, TGT_RSP_XRAM_IDLE, TGT_RSP_INIT_IDLE, @@ -93,5 +94,5 @@ TGT_RSP_READ, TGT_RSP_WRITE, - TGT_RSP_SC, + TGT_RSP_CAS, TGT_RSP_XRAM, TGT_RSP_INIT, @@ -109,10 +110,10 @@ INIT_CMD_UPDT_INDEX, INIT_CMD_UPDT_DATA, - INIT_CMD_SC_UPDT_IDLE, - INIT_CMD_SC_BRDCAST, - INIT_CMD_SC_UPDT_NLINE, - INIT_CMD_SC_UPDT_INDEX, - INIT_CMD_SC_UPDT_DATA, - INIT_CMD_SC_UPDT_DATA_HIGH + INIT_CMD_CAS_UPDT_IDLE, + INIT_CMD_CAS_BRDCAST, + INIT_CMD_CAS_UPDT_NLINE, + INIT_CMD_CAS_UPDT_INDEX, + INIT_CMD_CAS_UPDT_DATA, + INIT_CMD_CAS_UPDT_DATA_HIGH }; @@ -199,34 +200,34 @@ IXR_CMD_READ_IDLE, IXR_CMD_WRITE_IDLE, - IXR_CMD_SC_IDLE, + IXR_CMD_CAS_IDLE, IXR_CMD_XRAM_IDLE, IXR_CMD_READ_NLINE, IXR_CMD_WRITE_NLINE, - IXR_CMD_SC_NLINE, + IXR_CMD_CAS_NLINE, IXR_CMD_XRAM_DATA }; - /* States of the SC fsm */ - enum sc_fsm_state_e{ - SC_IDLE, - SC_DIR_REQ, - SC_DIR_LOCK, - SC_DIR_HIT_READ, - SC_DIR_HIT_WRITE, - SC_UPT_LOCK, - SC_UPT_HEAP_LOCK, - SC_UPT_REQ, - SC_UPT_NEXT, - SC_BC_TRT_LOCK, - SC_BC_UPT_LOCK, - SC_BC_DIR_INVAL, - SC_BC_CC_SEND, - SC_BC_XRAM_REQ, - SC_RSP_FAIL, - SC_RSP_SUCCESS, - SC_MISS_TRT_LOCK, - SC_MISS_TRT_SET, - SC_MISS_XRAM_REQ, - SC_WAIT + /* States of the CAS fsm */ + enum cas_fsm_state_e{ + CAS_IDLE, + CAS_DIR_REQ, + CAS_DIR_LOCK, + CAS_DIR_HIT_READ, + CAS_DIR_HIT_WRITE, + CAS_UPT_LOCK, + CAS_UPT_HEAP_LOCK, + CAS_UPT_REQ, + CAS_UPT_NEXT, + CAS_BC_TRT_LOCK, + CAS_BC_UPT_LOCK, + CAS_BC_DIR_INVAL, + CAS_BC_CC_SEND, + CAS_BC_XRAM_REQ, + CAS_RSP_FAIL, + CAS_RSP_SUCCESS, + CAS_MISS_TRT_LOCK, + CAS_MISS_TRT_SET, + CAS_MISS_XRAM_REQ, + CAS_WAIT }; @@ -253,5 +254,5 @@ ALLOC_DIR_READ, ALLOC_DIR_WRITE, - ALLOC_DIR_SC, + ALLOC_DIR_CAS, ALLOC_DIR_CLEANUP, ALLOC_DIR_XRAM_RSP @@ -262,5 +263,5 @@ ALLOC_TRT_READ, ALLOC_TRT_WRITE, - ALLOC_TRT_SC, + ALLOC_TRT_CAS, ALLOC_TRT_XRAM_RSP, ALLOC_TRT_IXR_RSP @@ -273,5 +274,5 @@ ALLOC_UPT_INIT_RSP, ALLOC_UPT_CLEANUP, - ALLOC_UPT_SC + ALLOC_UPT_CAS }; @@ -281,7 +282,35 @@ ALLOC_HEAP_READ, ALLOC_HEAP_WRITE, - ALLOC_HEAP_SC, + ALLOC_HEAP_CAS, ALLOC_HEAP_CLEANUP, ALLOC_HEAP_XRAM_RSP + }; + + /* transaction type, pktid field */ + enum transaction_type_e + { + // b3 unused + // b2 READ / NOT READ + // Si READ + // b1 DATA / INS + // b0 UNC / MISS + // Si NOT READ + // b1 accÚs table llsc type SW / other + // b2 WRITE/CAS/LL/SC + TYPE_READ_DATA_UNC = 0x0, + TYPE_READ_DATA_MISS = 0x1, + TYPE_READ_INS_UNC = 0x2, + TYPE_READ_INS_MISS = 0x3, + TYPE_WRITE = 0x4, + TYPE_CAS = 0x5, + TYPE_LL = 0x6, + TYPE_SC = 0x7 + }; + + /* SC return values */ + enum sc_status_type_e + { + SC_SUCCESS = 0x00000000, + SC_FAIL = 0x00000001 }; @@ -296,5 +325,5 @@ bool m_debug_read_fsm; bool m_debug_write_fsm; - bool m_debug_sc_fsm; + bool m_debug_cas_fsm; bool m_debug_cleanup_fsm; bool m_debug_ixr_cmd_fsm; @@ -326,4 +355,5 @@ uint32_t m_cpt_ll; // Number of LL transactions uint32_t m_cpt_sc; // Number of SC transactions + uint32_t m_cpt_cas; // Number of CAS transactions size_t m_prev_count; @@ -429,11 +459,11 @@ GenericFifo m_cmd_write_be_fifo; - // Fifo between TGT_CMD fsm and SC fsm - GenericFifo m_cmd_sc_addr_fifo; - GenericFifo m_cmd_sc_eop_fifo; - GenericFifo m_cmd_sc_srcid_fifo; - GenericFifo m_cmd_sc_trdid_fifo; - GenericFifo m_cmd_sc_pktid_fifo; - GenericFifo m_cmd_sc_wdata_fifo; + // Fifo between TGT_CMD fsm and CAS fsm + GenericFifo m_cmd_cas_addr_fifo; + GenericFifo m_cmd_cas_eop_fifo; + GenericFifo m_cmd_cas_srcid_fifo; + GenericFifo m_cmd_cas_trdid_fifo; + GenericFifo m_cmd_cas_pktid_fifo; + GenericFifo m_cmd_cas_wdata_fifo; sc_signal r_tgt_cmd_fsm; @@ -594,59 +624,59 @@ /////////////////////////////////////////////////////// - // Registers controlled by SC fsm + // Registers controlled by CAS fsm /////////////////////////////////////////////////////// - sc_signal r_sc_fsm; // FSM state - sc_signal r_sc_wdata; // write data word - sc_signal * r_sc_rdata; // read data word - sc_signal r_sc_lfsr; // lfsr for random introducing - sc_signal r_sc_cpt; // size of command - sc_signal r_sc_copy; // Srcid of the first copy - sc_signal r_sc_copy_cache; // Srcid of the first copy - sc_signal r_sc_copy_inst; // Type of the first copy - sc_signal r_sc_count; // number of copies - sc_signal r_sc_ptr; // pointer to the heap - sc_signal r_sc_next_ptr; // next pointer to the heap - sc_signal r_sc_is_cnt; // is_cnt bit (in directory) - sc_signal r_sc_dirty; // dirty bit (in directory) - sc_signal r_sc_way; // way in directory - sc_signal r_sc_set; // set in directory - sc_signal r_sc_tag; // cache line tag (in directory) - sc_signal r_sc_trt_index; // Transaction Table index - sc_signal r_sc_upt_index; // Update Table index - - // Buffer between SC fsm and INIT_CMD fsm (XRAM read) - sc_signal r_sc_to_ixr_cmd_req; // valid request - sc_signal r_sc_to_ixr_cmd_nline; // cache line index - sc_signal r_sc_to_ixr_cmd_trdid; // index in Transaction Table - sc_signal r_sc_to_ixr_cmd_write; // write request - sc_signal * r_sc_to_ixr_cmd_data; // cache line data - - - // Buffer between SC fsm and TGT_RSP fsm - sc_signal r_sc_to_tgt_rsp_req; // valid request - sc_signal r_sc_to_tgt_rsp_data; // read data word - sc_signal r_sc_to_tgt_rsp_srcid; // Transaction srcid - sc_signal r_sc_to_tgt_rsp_trdid; // Transaction trdid - sc_signal r_sc_to_tgt_rsp_pktid; // Transaction pktid - - // Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches) - sc_signal r_sc_to_init_cmd_multi_req; // valid request - sc_signal r_sc_to_init_cmd_brdcast_req; // brdcast request - sc_signal r_sc_to_init_cmd_nline; // cache line index - sc_signal r_sc_to_init_cmd_trdid; // index in Update Table - sc_signal r_sc_to_init_cmd_wdata; // data (one word) - sc_signal r_sc_to_init_cmd_is_long; // it is a 64 bits SC - sc_signal r_sc_to_init_cmd_wdata_high; // data high (one word) - sc_signal r_sc_to_init_cmd_index; // index of the word in line - GenericFifo m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type - GenericFifo m_sc_to_init_cmd_srcid_fifo; // fifo for srcids + sc_signal r_cas_fsm; // FSM state + sc_signal r_cas_wdata; // write data word + sc_signal * r_cas_rdata; // read data word + sc_signal r_cas_lfsr; // lfsr for random introducing + sc_signal r_cas_cpt; // size of command + sc_signal r_cas_copy; // Srcid of the first copy + sc_signal r_cas_copy_cache; // Srcid of the first copy + sc_signal r_cas_copy_inst; // Type of the first copy + sc_signal r_cas_count; // number of copies + sc_signal r_cas_ptr; // pointer to the heap + sc_signal r_cas_next_ptr; // next pointer to the heap + sc_signal r_cas_is_cnt; // is_cnt bit (in directory) + sc_signal r_cas_dirty; // dirty bit (in directory) + sc_signal r_cas_way; // way in directory + sc_signal r_cas_set; // set in directory + sc_signal r_cas_tag; // cache line tag (in directory) + sc_signal r_cas_trt_index; // Transaction Table index + sc_signal r_cas_upt_index; // Update Table index + + // Buffer between CAS fsm and INIT_CMD fsm (XRAM read) + sc_signal r_cas_to_ixr_cmd_req; // valid request + sc_signal r_cas_to_ixr_cmd_nline; // cache line index + sc_signal r_cas_to_ixr_cmd_trdid; // index in Transaction Table + sc_signal r_cas_to_ixr_cmd_write; // write request + sc_signal * r_cas_to_ixr_cmd_data; // cache line data + + + // Buffer between CAS fsm and TGT_RSP fsm + sc_signal r_cas_to_tgt_rsp_req; // valid request + sc_signal r_cas_to_tgt_rsp_data; // read data word + sc_signal r_cas_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_cas_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_cas_to_tgt_rsp_pktid; // Transaction pktid + + // Buffer between CAS fsm and INIT_CMD fsm (Update/Invalidate L1 caches) + sc_signal r_cas_to_init_cmd_multi_req; // valid request + sc_signal r_cas_to_init_cmd_brdcast_req; // brdcast request + sc_signal r_cas_to_init_cmd_nline; // cache line index + sc_signal r_cas_to_init_cmd_trdid; // index in Update Table + sc_signal r_cas_to_init_cmd_wdata; // data (one word) + sc_signal r_cas_to_init_cmd_is_long; // it is a 64 bits CAS + sc_signal r_cas_to_init_cmd_wdata_high; // data high (one word) + sc_signal r_cas_to_init_cmd_index; // index of the word in line + GenericFifo m_cas_to_init_cmd_inst_fifo; // fifo for the L1 type + GenericFifo m_cas_to_init_cmd_srcid_fifo; // fifo for srcids #if L1_MULTI_CACHE - GenericFifo m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids + GenericFifo m_cas_to_init_cmd_cache_id_fifo; // fifo for srcids #endif - // Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry) - sc_signal r_sc_to_init_rsp_req; // valid request - sc_signal r_sc_to_init_rsp_upt_index; // index in update table + // Buffer between CAS fsm and INIT_RSP fsm (Decrement UPT entry) + sc_signal r_cas_to_init_rsp_req; // valid request + sc_signal r_cas_to_init_rsp_upt_index; // index in update table //////////////////////////////////////////////////// Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 283) +++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 284) @@ -27,4 +27,5 @@ * Maintainers: alain eric.guthmuller@polytechnique.edu * cesar.fuguet-tortolero@lip6.fr + * alexandre.joannou@lip6.fr */ @@ -41,5 +42,5 @@ #define DEBUG_MEMC_READ 1 // detailed trace of READ FSM #define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM -#define DEBUG_MEMC_SC 1 // detailed trace of SC FSM +#define DEBUG_MEMC_CAS 1 // detailed trace of CAS FSM #define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_RSP FSM #define DEBUG_MEMC_IXR_RSP 1 // detailed trace of IXR_RSP FSM @@ -51,5 +52,5 @@ #define DEBUG_MEMC_CLEANUP 1 // detailed trace of CLEANUP FSM -#define RANDOMIZE_SC 1 +#define RANDOMIZE_CAS 1 namespace soclib { namespace caba { @@ -59,10 +60,10 @@ "TGT_CMD_READ", "TGT_CMD_WRITE", - "TGT_CMD_ATOMIC" + "TGT_CMD_CAS" }; const char *tgt_rsp_fsm_str[] = { "TGT_RSP_READ_IDLE", "TGT_RSP_WRITE_IDLE", - "TGT_RSP_SC_IDLE", + "TGT_RSP_CAS_IDLE", "TGT_RSP_XRAM_IDLE", "TGT_RSP_INIT_IDLE", @@ -70,5 +71,5 @@ "TGT_RSP_READ", "TGT_RSP_WRITE", - "TGT_RSP_SC", + "TGT_RSP_CAS", "TGT_RSP_XRAM", "TGT_RSP_INIT", @@ -84,10 +85,10 @@ "INIT_CMD_UPDT_INDEX", "INIT_CMD_UPDT_DATA", - "INIT_CMD_SC_UPDT_IDLE", - "INIT_CMD_SC_BRDCAST", - "INIT_CMD_SC_UPDT_NLINE", - "INIT_CMD_SC_UPDT_INDEX", - "INIT_CMD_SC_UPDT_DATA", - "INIT_CMD_SC_UPDT_DATA_HIGH" + "INIT_CMD_CAS_UPDT_IDLE", + "INIT_CMD_CAS_BRDCAST", + "INIT_CMD_CAS_UPDT_NLINE", + "INIT_CMD_CAS_UPDT_INDEX", + "INIT_CMD_CAS_UPDT_DATA", + "INIT_CMD_CAS_UPDT_DATA_HIGH" }; const char *init_rsp_fsm_str[] = { @@ -162,32 +163,32 @@ "IXR_CMD_READ_IDLE", "IXR_CMD_WRITE_IDLE", - "IXR_CMD_SC_IDLE", + "IXR_CMD_CAS_IDLE", "IXR_CMD_XRAM_IDLE", "IXR_CMD_READ_NLINE", "IXR_CMD_WRITE_NLINE", - "IXR_CMD_SC_NLINE", + "IXR_CMD_CAS_NLINE", "IXR_CMD_XRAM_DATA" }; - const char *sc_fsm_str[] = { - "SC_IDLE", - "SC_DIR_REQ", - "SC_DIR_LOCK", - "SC_DIR_HIT_READ", - "SC_DIR_HIT_WRITE", - "SC_UPT_LOCK", - "SC_UPT_HEAP_LOCK", - "SC_UPT_REQ", - "SC_UPT_NEXT", - "SC_BC_TRT_LOCK", - "SC_BC_UPT_LOCK", - "SC_BC_DIR_INVAL", - "SC_BC_CC_SEND", - "SC_BC_XRAM_REQ", - "SC_RSP_FAIL", - "SC_RSP_SUCCESS", - "SC_MISS_TRT_LOCK", - "SC_MISS_TRT_SET", - "SC_MISS_XRAM_REQ", - "SC_WAIT" + const char *cas_fsm_str[] = { + "CAS_IDLE", + "CAS_DIR_REQ", + "CAS_DIR_LOCK", + "CAS_DIR_HIT_READ", + "CAS_DIR_HIT_WRITE", + "CAS_UPT_LOCK", + "CAS_UPT_HEAP_LOCK", + "CAS_UPT_REQ", + "CAS_UPT_NEXT", + "CAS_BC_TRT_LOCK", + "CAS_BC_UPT_LOCK", + "CAS_BC_DIR_INVAL", + "CAS_BC_CC_SEND", + "CAS_BC_XRAM_REQ", + "CAS_RSP_FAIL", + "CAS_RSP_SUCCESS", + "CAS_MISS_TRT_LOCK", + "CAS_MISS_TRT_SET", + "CAS_MISS_XRAM_REQ", + "CAS_WAIT" }; const char *cleanup_fsm_str[] = { @@ -210,5 +211,5 @@ "ALLOC_DIR_READ", "ALLOC_DIR_WRITE", - "ALLOC_DIR_SC", + "ALLOC_DIR_CAS", "ALLOC_DIR_CLEANUP", "ALLOC_DIR_XRAM_RSP" @@ -217,5 +218,5 @@ "ALLOC_TRT_READ", "ALLOC_TRT_WRITE", - "ALLOC_TRT_SC", + "ALLOC_TRT_CAS", "ALLOC_TRT_XRAM_RSP", "ALLOC_TRT_IXR_RSP" @@ -226,5 +227,5 @@ "ALLOC_UPT_INIT_RSP", "ALLOC_UPT_CLEANUP", - "ALLOC_UPT_SC" + "ALLOC_UPT_CAS" }; const char *alloc_heap_fsm_str[] = { @@ -232,5 +233,5 @@ "ALLOC_HEAP_READ", "ALLOC_HEAP_WRITE", - "ALLOC_HEAP_SC", + "ALLOC_HEAP_CAS", "ALLOC_HEAP_CLEANUP", "ALLOC_HEAP_XRAM_RSP" @@ -314,10 +315,10 @@ m_cmd_write_be_fifo("m_cmd_write_be_fifo",8), - m_cmd_sc_addr_fifo("m_cmd_sc_addr_fifo",4), - m_cmd_sc_eop_fifo("m_cmd_sc_eop_fifo",4), - m_cmd_sc_srcid_fifo("m_cmd_sc_srcid_fifo",4), - m_cmd_sc_trdid_fifo("m_cmd_sc_trdid_fifo",4), - m_cmd_sc_pktid_fifo("m_cmd_sc_pktid_fifo",4), - m_cmd_sc_wdata_fifo("m_cmd_sc_wdata_fifo",4), + m_cmd_cas_addr_fifo("m_cmd_cas_addr_fifo",4), + m_cmd_cas_eop_fifo("m_cmd_cas_eop_fifo",4), + m_cmd_cas_srcid_fifo("m_cmd_cas_srcid_fifo",4), + m_cmd_cas_trdid_fifo("m_cmd_cas_trdid_fifo",4), + m_cmd_cas_pktid_fifo("m_cmd_cas_pktid_fifo",4), + m_cmd_cas_wdata_fifo("m_cmd_cas_wdata_fifo",4), r_tgt_cmd_fsm("r_tgt_cmd_fsm"), @@ -339,10 +340,10 @@ r_cleanup_fsm("r_cleanup_fsm"), - r_sc_fsm("r_sc_fsm"), - - m_sc_to_init_cmd_inst_fifo("m_sc_to_init_cmd_inst_fifo",8), - m_sc_to_init_cmd_srcid_fifo("m_sc_to_init_cmd_srcid_fifo",8), + r_cas_fsm("r_cas_fsm"), + + m_cas_to_init_cmd_inst_fifo("m_cas_to_init_cmd_inst_fifo",8), + m_cas_to_init_cmd_srcid_fifo("m_cas_to_init_cmd_srcid_fifo",8), #if L1_MULTI_CACHE - m_sc_to_init_cmd_cache_id_fifo("m_sc_to_init_cmd_cache_id_fifo",8), + m_cas_to_init_cmd_cache_id_fifo("m_cas_to_init_cmd_cache_id_fifo",8), #endif @@ -443,7 +444,7 @@ r_write_to_ixr_cmd_data = new sc_signal[nwords]; - // Allocation for SC FSM - r_sc_to_ixr_cmd_data = new sc_signal[nwords]; - r_sc_rdata = new sc_signal[2]; + // Allocation for CAS FSM + r_cas_to_ixr_cmd_data = new sc_signal[nwords]; + r_cas_rdata = new sc_signal[2]; @@ -515,5 +516,5 @@ << " | " << read_fsm_str[r_read_fsm] << " | " << write_fsm_str[r_write_fsm] - << " | " << sc_fsm_str[r_sc_fsm] + << " | " << cas_fsm_str[r_cas_fsm] << " | " << cleanup_fsm_str[r_cleanup_fsm] << std::endl; std::cout << " " << init_cmd_fsm_str[r_init_cmd_fsm] @@ -549,5 +550,6 @@ << "- CLEANUP RATE = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl << "- LL RATE = " << (double) m_cpt_ll/m_cpt_cycles << std::endl - << "- SC RATE = " << (double) m_cpt_sc/m_cpt_cycles << std::endl; + << "- SC RATE = " << (double) m_cpt_sc/m_cpt_cycles << std::endl + << "- CAS RATE = " << (double) m_cpt_cas/m_cpt_cycles << std::endl; } @@ -596,5 +598,5 @@ r_read_fsm = READ_IDLE; r_write_fsm = WRITE_IDLE; - r_sc_fsm = SC_IDLE; + r_cas_fsm = CAS_IDLE; r_cleanup_fsm = CLEANUP_IDLE; r_alloc_dir_fsm = ALLOC_DIR_RESET; @@ -613,5 +615,5 @@ m_debug_read_fsm = false; m_debug_write_fsm = false; - m_debug_sc_fsm = false; + m_debug_cas_fsm = false; m_debug_cleanup_fsm = false; m_debug_ixr_cmd_fsm = false; @@ -640,10 +642,10 @@ m_cmd_write_data_fifo.init(); - m_cmd_sc_addr_fifo.init(); - m_cmd_sc_srcid_fifo.init(); - m_cmd_sc_trdid_fifo.init(); - m_cmd_sc_pktid_fifo.init(); - m_cmd_sc_wdata_fifo.init(); - m_cmd_sc_eop_fifo.init(); + m_cmd_cas_addr_fifo.init() ; + m_cmd_cas_srcid_fifo.init() ; + m_cmd_cas_trdid_fifo.init() ; + m_cmd_cas_pktid_fifo.init() ; + m_cmd_cas_wdata_fifo.init() ; + m_cmd_cas_eop_fifo.init() ; r_read_to_tgt_rsp_req = false; @@ -662,19 +664,19 @@ #endif - r_cleanup_to_tgt_rsp_req = false; - - r_init_rsp_to_tgt_rsp_req = false; - - r_sc_to_tgt_rsp_req = false; - r_sc_cpt = 0; - r_sc_lfsr = -1; - r_sc_to_ixr_cmd_req = false; - r_sc_to_init_cmd_multi_req = false; - r_sc_to_init_cmd_brdcast_req = false; - - m_sc_to_init_cmd_inst_fifo.init(); - m_sc_to_init_cmd_srcid_fifo.init(); + r_cleanup_to_tgt_rsp_req = false; + + r_init_rsp_to_tgt_rsp_req = false; + + r_cas_to_tgt_rsp_req = false; + r_cas_cpt = 0 ; + r_cas_lfsr = -1 ; + r_cas_to_ixr_cmd_req = false; + r_cas_to_init_cmd_multi_req = false; + r_cas_to_init_cmd_brdcast_req = false; + + m_cas_to_init_cmd_inst_fifo.init(); + m_cas_to_init_cmd_srcid_fifo.init(); #if L1_MULTI_CACHE - m_sc_to_init_cmd_cache_id_fifo.init(); + m_cas_to_init_cmd_cache_id_fifo.init(); #endif @@ -717,4 +719,5 @@ m_cpt_ll = 0; m_cpt_sc = 0; + m_cpt_cas = 0; m_cpt_trt_full = 0; m_cpt_trt_rb = 0; @@ -729,6 +732,6 @@ bool cmd_write_fifo_get = false; - bool cmd_sc_fifo_put = false; - bool cmd_sc_fifo_get = false; + bool cmd_cas_fifo_put = false; + bool cmd_cas_fifo_get = false; bool write_to_init_cmd_fifo_put = false; @@ -750,11 +753,11 @@ #endif - bool sc_to_init_cmd_fifo_put = false; - bool sc_to_init_cmd_fifo_get = false; - bool sc_to_init_cmd_fifo_inst = false; - size_t sc_to_init_cmd_fifo_srcid = 0; + bool cas_to_init_cmd_fifo_put = false; + bool cas_to_init_cmd_fifo_get = false; + bool cas_to_init_cmd_fifo_inst = false; + size_t cas_to_init_cmd_fifo_srcid = 0; #if L1_MULTI_CACHE - size_t sc_to_init_cmd_fifo_cache_id = 0; + size_t cas_to_init_cmd_fifo_cache_id = 0; #endif @@ -766,5 +769,5 @@ m_debug_read_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; m_debug_write_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_sc_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_cas_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; m_debug_cleanup_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; m_debug_ixr_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; @@ -784,5 +787,5 @@ << " - READ FSM = " << read_fsm_str[r_read_fsm] << std::endl << " - WRITE FSM = " << write_fsm_str[r_write_fsm] << std::endl - << " - SC FSM = " << sc_fsm_str[r_sc_fsm] << std::endl + << " - CAS FSM = " << cas_fsm_str[r_cas_fsm] << std::endl << " - CLEANUP FSM = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl << " - IXR_CMD FSM = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << std::endl @@ -801,10 +804,13 @@ // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors // - // There is 3 types of accepted commands : - // - READ : a READ request has a length of 1 VCI cell. It can be a single word - // or an entire cache line, depending on the PLEN value. - // - WRITE : a WRITE request has a maximum length of 16 cells, and can only - // concern words in a same line. - // - SC : The SC request has a length of 2 cells or 4 cells. + // There are 5 types of accepted commands : + // - READ : A READ request has a length of 1 VCI cell. It can be a single word + // or an entire cache line, depending on the PLEN value. + // - WRITE : A WRITE request has a maximum length of 16 cells, and can only + // concern words in a same line. + // - CAS : A CAS request has a length of 2 cells or 4 cells. + // - LL : An LL request has a length of 1 cell. + // - SC : An SC request has a length of 2 cells. First cell contains the + // acces key, second cell the data to write in case of success. //////////////////////////////////////////////////////////////////////////////////// @@ -849,13 +855,50 @@ if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) { + // check that the pktid is either : + // TYPE_READ_DATA_UNC + // TYPE_READ_DATA_MISS + // TYPE_READ_INS_UNC + // TYPE_READ_INS_MISS + // ==> bit2 must be zero with the TSAR encoding + // ==> mask = 0b0100 = 0x4 + assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) && + "The type specified in the pktid field is incompatible with the READ CMD"); r_tgt_cmd_fsm = TGT_CMD_READ; } else if ( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) { + // check that the pktid is TYPE_WRITE + // ==> TYPE_WRITE = X100 with the TSAR encoding + // ==> mask = 0b0111 = 0x7 + assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) && + "The type specified in the pktid field is incompatible with the WRITE CMD"); r_tgt_cmd_fsm = TGT_CMD_WRITE; } - else if ( p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND ) - { - r_tgt_cmd_fsm = TGT_CMD_ATOMIC; + else if ( p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ ) + { + // check that the pktid is TYPE_LL + // ==> TYPE_LL = X110 with the TSAR encoding + // ==> mask = 0b0111 = 0x7 + assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) && + "The type specified in the pktid field is incompatible with the LL CMD"); + assert(false && "TODO : LL not implemented"); //TODO + //r_tgt_cmd_fsm = TGT_CMD_READ; + } + else if ( p_vci_tgt.cmd.read() == vci_param::CMD_NOP ) + { + // check that the pktid is either : + // TYPE_CAS + // TYPE_SC + // ==> TYPE_CAS = X101 with the TSAR encoding + // ==> TYPE_SC = X111 with the TSAR encoding + // ==> mask = 0b0101 = 0x5 + assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5 ) && + "The type specified in the pktid field is incompatible with the NOP CMD"); + + if(p_vci_tgt.pktid.read() == TYPE_CAS) + r_tgt_cmd_fsm = TGT_CMD_CAS; + else // TYPE_SC + assert(false && "TODO : SC not implemented"); //TODO + //r_tgt_cmd_fsm = TGT_CMD_WRITE; } else @@ -901,4 +944,5 @@ << " srcid = " << std::dec << p_vci_tgt.srcid.read() << " trdid = " << p_vci_tgt.trdid.read() + << " pktid = " << p_vci_tgt.pktid.read() << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; } @@ -922,4 +966,5 @@ << " srcid = " << std::dec << p_vci_tgt.srcid.read() << " trdid = " << p_vci_tgt.trdid.read() + << " pktid = " << p_vci_tgt.pktid.read() << " wdata = " << std::hex << p_vci_tgt.wdata.read() << " be = " << p_vci_tgt.be.read() @@ -933,16 +978,16 @@ //////////////////// - case TGT_CMD_ATOMIC: + case TGT_CMD_CAS: if ( (p_vci_tgt.plen.read() != 8) && (p_vci_tgt.plen.read() != 16) ) { std::cout - << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_ATOMIC state" + << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" << std::endl - << "illegal format for sc command " << std::endl; + << "illegal format for CAS command " << std::endl; exit(0); } - if ( p_vci_tgt.cmdval && m_cmd_sc_addr_fifo.wok() ) + if ( p_vci_tgt.cmdval && m_cmd_cas_addr_fifo.wok() ) { @@ -950,8 +995,9 @@ if( m_debug_tgt_cmd_fsm ) { - std::cout << " Pushing command into cmd_sc_fifo:" + std::cout << " Pushing command into cmd_cas_fifo:" << " address = " << std::hex << p_vci_tgt.address.read() << " srcid = " << std::dec << p_vci_tgt.srcid.read() << " trdid = " << p_vci_tgt.trdid.read() + << " pktid = " << p_vci_tgt.pktid.read() << " wdata = " << std::hex << p_vci_tgt.wdata.read() << " be = " << p_vci_tgt.be.read() @@ -959,5 +1005,5 @@ } #endif - cmd_sc_fifo_put = true; + cmd_cas_fifo_put = true; if( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE; } @@ -1202,5 +1248,8 @@ r_read_ptr = entry.ptr; // pointer to the heap - bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1); + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); if( entry.valid ) // hit { @@ -1256,6 +1305,12 @@ { // signals generation - bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2); - bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1); + // check if this is an instruction read, this means pktid is either + // TYPE_READ_INS_UNC 0bX010 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool inst_read = (m_cmd_read_pktid_fifo.read() & 0x2); + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); bool is_cnt = r_read_is_cnt.read(); @@ -1458,5 +1513,5 @@ heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); #endif - heap_entry.owner.inst = (m_cmd_read_trdid_fifo.read() & 0x2); + heap_entry.owner.inst = (m_cmd_read_pktid_fifo.read() & 0x2); if(r_read_count.read() == 1) // creation of a new linked list @@ -2687,12 +2742,12 @@ // The IXR_CMD fsm controls the command packets to the XRAM : // - It sends a single cell VCI read request to the XRAM in case of MISS - // posted by the READ, WRITE or SC FSMs : the TRDID field contains + // posted by the READ, WRITE or CAS FSMs : the TRDID field contains // the Transaction Tab index. // The VCI response is a multi-cell packet : the N cells contain // the N data words. // - It sends a multi-cell VCI write when the XRAM_RSP FSM, WRITE FSM - // or SC FSM request to save a dirty line to the XRAM. + // or CAS FSM request to save a dirty line to the XRAM. // The VCI response is a single cell packet. - // This FSM handles requests from the READ, WRITE, SC & XRAM_RSP FSMs + // This FSM handles requests from the READ, WRITE, CAS & XRAM_RSP FSMs // with a round-robin priority. //////////////////////////////////////////////////////////////////////// @@ -2703,5 +2758,5 @@ case IXR_CMD_READ_IDLE: if ( r_write_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; - else if ( r_sc_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_SC_NLINE; + else if ( r_cas_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE; else if ( r_xram_rsp_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; else if ( r_read_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; @@ -2709,5 +2764,5 @@ //////////////////////// case IXR_CMD_WRITE_IDLE: - if ( r_sc_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_SC_NLINE; + if ( r_cas_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE; else if ( r_xram_rsp_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; else if ( r_read_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; @@ -2715,9 +2770,9 @@ break; //////////////////////// - case IXR_CMD_SC_IDLE: + case IXR_CMD_CAS_IDLE: if ( r_xram_rsp_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; else if ( r_read_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; else if ( r_write_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; - else if ( r_sc_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_SC_NLINE; + else if ( r_cas_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE; break; //////////////////////// @@ -2725,5 +2780,5 @@ if ( r_read_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; else if ( r_write_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; - else if ( r_sc_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_SC_NLINE; + else if ( r_cas_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE; else if ( r_xram_rsp_to_ixr_cmd_req ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; break; @@ -2782,14 +2837,14 @@ break; ////////////////////// - case IXR_CMD_SC_NLINE: // send a put or get command to XRAM + case IXR_CMD_CAS_NLINE: // send a put or get command to XRAM if ( p_vci_ixr.cmdack ) { - if( r_sc_to_ixr_cmd_write.read()) + if( r_cas_to_ixr_cmd_write.read()) { if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) { r_ixr_cmd_cpt = 0; - r_ixr_cmd_fsm = IXR_CMD_SC_IDLE; - r_sc_to_ixr_cmd_req = false; + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; } else @@ -2801,5 +2856,5 @@ if( m_debug_ixr_cmd_fsm ) { - std::cout << " Send a put request to xram" << std::endl; + std::cout << " Send a put request to xram" << std::endl; } #endif @@ -2807,11 +2862,11 @@ else { - r_ixr_cmd_fsm = IXR_CMD_SC_IDLE; - r_sc_to_ixr_cmd_req = false; + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; #if DEBUG_MEMC_IXR_CMD if( m_debug_ixr_cmd_fsm ) { - std::cout << " Send a get request to xram" << std::endl; + std::cout << " Send a get request to xram" << std::endl; } #endif @@ -3161,6 +3216,13 @@ { // signals generation - bool inst_read = (r_xram_rsp_trt_buf.trdid & 0x2) && r_xram_rsp_trt_buf.proc_read; - bool cached_read = (r_xram_rsp_trt_buf.trdid & 0x1) && r_xram_rsp_trt_buf.proc_read; + // check if this is an instruction read, this means pktid is either + // TYPE_READ_INS_UNC 0bX010 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) && r_xram_rsp_trt_buf.proc_read; + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) && r_xram_rsp_trt_buf.proc_read; + // update data size_t set = r_xram_rsp_victim_set.read(); @@ -4186,7 +4248,7 @@ //////////////////////////////////////////////////////////////////////////////////// - // SC FSM + // CAS FSM //////////////////////////////////////////////////////////////////////////////////// - // The SC FSM handles the SC (Store Conditionnal) atomic commands, + // The CAS FSM handles the CAS (Store Conditionnal) atomic commands, // that are handled as "compare-and-swap instructions. // @@ -4201,59 +4263,59 @@ // // It access the directory to check hit / miss. - // - In case of miss, the SC FSM must register a GET transaction in TRT. + // - In case of miss, the CAS FSM must register a GET transaction in TRT. // If a read transaction to the XRAM for this line already exists, // or if the transaction table is full, it goes to the WAIT state // to release the locks and try again. When the GET transaction has been // launched, it goes to the WAIT state and try again. - // The SC request is not consumed in the FIFO until a HIT is obtained. + // The CAS request is not consumed in the FIFO until a HIT is obtained. // - In case of hit... /////////////////////////////////////////////////////////////////////////////////// - switch ( r_sc_fsm.read() ) + switch ( r_cas_fsm.read() ) { ///////////// - case SC_IDLE: // fill the local rdata buffers - { - if( m_cmd_sc_addr_fifo.rok() ) - { - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + case CAS_IDLE: // fill the local rdata buffers + { + if( m_cmd_cas_addr_fifo.rok() ) + { + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " SC command: " << std::hex - << " srcid = " << std::dec << m_cmd_sc_srcid_fifo.read() - << " addr = " << std::hex << m_cmd_sc_addr_fifo.read() - << " wdata = " << m_cmd_sc_wdata_fifo.read() - << " eop = " << std::dec << m_cmd_sc_eop_fifo.read() - << " cpt = " << std::dec << r_sc_cpt.read() << std::endl; + std::cout << " CAS command: " << std::hex + << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read() + << " addr = " << std::hex << m_cmd_cas_addr_fifo.read() + << " wdata = " << m_cmd_cas_wdata_fifo.read() + << " eop = " << std::dec << m_cmd_cas_eop_fifo.read() + << " cpt = " << std::dec << r_cas_cpt.read() << std::endl; } #endif - if( m_cmd_sc_eop_fifo.read() ) + if( m_cmd_cas_eop_fifo.read() ) { - m_cpt_sc++; - r_sc_fsm = SC_DIR_REQ; + m_cpt_cas++; + r_cas_fsm = CAS_DIR_REQ; } else // we keep the last word in the FIFO { - cmd_sc_fifo_get = true; + cmd_cas_fifo_get = true; } // We fill the two buffers - if ( r_sc_cpt.read() < 2 ) // 32 bits access - r_sc_rdata[r_sc_cpt.read()] = m_cmd_sc_wdata_fifo.read(); - - if((r_sc_cpt.read() == 1) && m_cmd_sc_eop_fifo.read()) - r_sc_wdata = m_cmd_sc_wdata_fifo.read(); - - if( r_sc_cpt.read()>3 ) // more than 4 flits... + if ( r_cas_cpt.read() < 2 ) // 32 bits access + r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); + + if((r_cas_cpt.read() == 1) && m_cmd_cas_eop_fifo.read()) + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + + if( r_cas_cpt.read()>3 ) // more than 4 flits... { - std::cout << "VCI_MEM_CACHE ERROR in SC_IDLE state : illegal SC command" + std::cout << "VCI_MEM_CACHE ERROR in CAS_IDLE state : illegal CAS command" << std::endl; exit(0); } - if ( r_sc_cpt.read()==2 ) - r_sc_wdata = m_cmd_sc_wdata_fifo.read(); - - r_sc_cpt = r_sc_cpt.read()+1; + if ( r_cas_cpt.read()==2 ) + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + + r_cas_cpt = r_cas_cpt.read()+1; } break; @@ -4261,16 +4323,16 @@ ///////////////// - case SC_DIR_REQ: - { - if( r_alloc_dir_fsm.read() == ALLOC_DIR_SC ) - { - r_sc_fsm = SC_DIR_LOCK; - } - -#if DEBUG_MEMC_SC - if( m_debug_sc_fsm ) + case CAS_DIR_REQ: + { + if( r_alloc_dir_fsm.read() == ALLOC_DIR_CAS ) + { + r_cas_fsm = CAS_DIR_LOCK; + } + +#if DEBUG_MEMC_CAS + if( m_debug_cas_fsm ) { std::cout - << " Requesting DIR lock " + << " Requesting DIR lock " << std::endl; } @@ -4280,31 +4342,31 @@ ///////////////// - case SC_DIR_LOCK: // Read the directory - { - if( r_alloc_dir_fsm.read() == ALLOC_DIR_SC ) + case CAS_DIR_LOCK: // Read the directory + { + if( r_alloc_dir_fsm.read() == ALLOC_DIR_CAS ) { size_t way = 0; - DirectoryEntry entry(m_cache_directory.read(m_cmd_sc_addr_fifo.read(), way)); - - r_sc_is_cnt = entry.is_cnt; - r_sc_dirty = entry.dirty; - r_sc_tag = entry.tag; - r_sc_way = way; - r_sc_copy = entry.owner.srcid; + DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way)); + + r_cas_is_cnt = entry.is_cnt; + r_cas_dirty = entry.dirty; + r_cas_tag = entry.tag; + r_cas_way = way; + r_cas_copy = entry.owner.srcid; #if L1_MULTI_CACHE - r_sc_copy_cache = entry.owner.cache_id; -#endif - r_sc_copy_inst = entry.owner.inst; - r_sc_ptr = entry.ptr; - r_sc_count = entry.count; - - if ( entry.valid ) r_sc_fsm = SC_DIR_HIT_READ; - else r_sc_fsm = SC_MISS_TRT_LOCK; - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + r_cas_copy_cache = entry.owner.cache_id; +#endif + r_cas_copy_inst = entry.owner.inst; + r_cas_ptr = entry.ptr; + r_cas_count = entry.count; + + if ( entry.valid ) r_cas_fsm = CAS_DIR_HIT_READ; + else r_cas_fsm = CAS_MISS_TRT_LOCK; + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Directory acces" - << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() + std::cout << " Directory acces" + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() << " / hit = " << std::dec << entry.valid << " / count = " << entry.count @@ -4317,5 +4379,5 @@ std::cout << "VCI_MEM_CACHE ERROR " << name() - << " SC_DIR_LOCK state" << std::endl + << " CAS_DIR_LOCK state" << std::endl << "Bad DIR allocation" << std::endl; @@ -4326,51 +4388,51 @@ } ///////////////////// - case SC_DIR_HIT_READ: // update directory for lock and dirty bit + case CAS_DIR_HIT_READ: // update directory for lock and dirty bit // and check data change in cache { - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t way = r_cas_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; // update directory (lock & dirty bits) DirectoryEntry entry; entry.valid = true; - entry.is_cnt = r_sc_is_cnt.read(); + entry.is_cnt = r_cas_is_cnt.read(); entry.dirty = true; entry.lock = true; - entry.tag = r_sc_tag.read(); - entry.owner.srcid = r_sc_copy.read(); + entry.tag = r_cas_tag.read(); + entry.owner.srcid = r_cas_copy.read(); #if L1_MULTI_CACHE - entry.owner.cache_id = r_sc_copy_cache.read(); -#endif - entry.owner.inst = r_sc_copy_inst.read(); - entry.count = r_sc_count.read(); - entry.ptr = r_sc_ptr.read(); + entry.owner.cache_id = r_cas_copy_cache.read(); +#endif + entry.owner.inst = r_cas_copy_inst.read(); + entry.count = r_cas_count.read(); + entry.ptr = r_cas_ptr.read(); m_cache_directory.write(set, way, entry); // read data in cache & check data change - bool ok = ( r_sc_rdata[0].read() == m_cache_data[way][set][word] ); - if ( r_sc_cpt.read()==4 ) // 64 bits SC - ok &= ( r_sc_rdata[1] == m_cache_data[way][set][word+1] ); + bool ok = ( r_cas_rdata[0].read() == m_cache_data[way][set][word] ); + if ( r_cas_cpt.read()==4 ) // 64 bits CAS + ok &= ( r_cas_rdata[1] == m_cache_data[way][set][word+1] ); // to avoid livelock, force the atomic access to fail pseudo-randomly - bool forced_fail = ( (r_sc_lfsr % (64) == 0) && RANDOMIZE_SC ); - r_sc_lfsr = (r_sc_lfsr >> 1) ^ ((-(r_sc_lfsr & 1)) & 0xd0000001); + bool forced_fail = ( (r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS ); + r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((-(r_cas_lfsr & 1)) & 0xd0000001); if( ok and not forced_fail ) // no data change { - r_sc_fsm = SC_DIR_HIT_WRITE; + r_cas_fsm = CAS_DIR_HIT_WRITE; } else // return failure { - r_sc_fsm = SC_RSP_FAIL; - } - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + r_cas_fsm = CAS_RSP_FAIL; + } + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Test if SC success:" - << " / expected value = " << r_sc_rdata[0].read() + std::cout << " Test if CAS success:" + << " / expected value = " << r_cas_rdata[0].read() << " / actual value = " << m_cache_data[way][set][word] << " / forced_fail = " << forced_fail << std::endl; @@ -4380,56 +4442,56 @@ } ////////////////////// - case SC_DIR_HIT_WRITE: // test if a CC transaction is required + case CAS_DIR_HIT_WRITE: // test if a CC transaction is required // write data in cache if no CC request { // test coherence request - if(r_sc_count.read()) // replicated line - { - if ( r_sc_is_cnt.read() ) + if(r_cas_count.read()) // replicated line + { + if ( r_cas_is_cnt.read() ) { - r_sc_fsm = SC_BC_TRT_LOCK; // broadcast invalidate required + r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required } - else if( !r_sc_to_init_cmd_multi_req.read() && - !r_sc_to_init_cmd_brdcast_req.read() ) + else if( !r_cas_to_init_cmd_multi_req.read() && + !r_cas_to_init_cmd_brdcast_req.read() ) { - r_sc_fsm = SC_UPT_LOCK; // multi update required + r_cas_fsm = CAS_UPT_LOCK; // multi update required } else { - r_sc_fsm = SC_WAIT; + r_cas_fsm = CAS_WAIT; } } else // no copies { - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t way = r_cas_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; // cache update - m_cache_data[way][set][word] = r_sc_wdata.read(); - if(r_sc_cpt.read()==4) - m_cache_data[way][set][word+1] = m_cmd_sc_wdata_fifo.read(); + m_cache_data[way][set][word] = r_cas_wdata.read(); + if(r_cas_cpt.read()==4) + m_cache_data[way][set][word+1] = m_cmd_cas_wdata_fifo.read(); // monitor if ( m_monitor_ok ) { - vci_addr_t address = m_cmd_sc_addr_fifo.read(); + vci_addr_t address = m_cmd_cas_addr_fifo.read(); char buf[80]; - snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); - check_monitor( buf, address, r_sc_wdata.read() ); - if ( r_sc_cpt.read()==4 ) - check_monitor( buf, address+4, m_cmd_sc_wdata_fifo.read() ); + snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read()); + check_monitor( buf, address, r_cas_wdata.read() ); + if ( r_cas_cpt.read()==4 ) + check_monitor( buf, address+4, m_cmd_cas_wdata_fifo.read() ); } - r_sc_fsm = SC_RSP_SUCCESS; - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + r_cas_fsm = CAS_RSP_SUCCESS; + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Update cache:" + std::cout << " Update cache:" << " way = " << std::dec << way << " / set = " << set << " / word = " << word - << " / value = " << r_sc_wdata.read() - << " / count = " << r_sc_count.read() << std::endl; + << " / value = " << r_cas_wdata.read() + << " / count = " << r_cas_count.read() << std::endl; } #endif @@ -4438,17 +4500,17 @@ } ///////////////// - case SC_UPT_LOCK: // try to register the transaction in UPT + case CAS_UPT_LOCK: // try to register the transaction in UPT // and write data in cache if successful registration // releases locks to retry later if UPT full { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_SC ) + if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CAS ) { bool wok = false; size_t index = 0; - size_t srcid = m_cmd_sc_srcid_fifo.read(); - size_t trdid = m_cmd_sc_trdid_fifo.read(); - size_t pktid = m_cmd_sc_pktid_fifo.read(); - addr_t nline = m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t nb_copies = r_sc_count.read(); + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); wok = m_update_tab.set(true, // it's an update transaction @@ -4464,35 +4526,35 @@ { // cache update - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - - m_cache_data[way][set][word] = r_sc_wdata.read(); - if(r_sc_cpt.read()==4) - m_cache_data[way][set][word+1] = m_cmd_sc_wdata_fifo.read(); + size_t way = r_cas_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + + m_cache_data[way][set][word] = r_cas_wdata.read(); + if(r_cas_cpt.read()==4) + m_cache_data[way][set][word+1] = m_cmd_cas_wdata_fifo.read(); // monitor if ( m_monitor_ok ) { - vci_addr_t address = m_cmd_sc_addr_fifo.read(); + vci_addr_t address = m_cmd_cas_addr_fifo.read(); char buf[80]; - snprintf(buf, 80, "SC_DIR_HIT_WRITE srcid %d", m_cmd_sc_srcid_fifo.read()); - check_monitor( buf, address, r_sc_wdata.read() ); - if ( r_sc_cpt.read()==4 ) - check_monitor( buf, address+4, m_cmd_sc_wdata_fifo.read() ); + snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read()); + check_monitor( buf, address, r_cas_wdata.read() ); + if ( r_cas_cpt.read()==4 ) + check_monitor( buf, address+4, m_cmd_cas_wdata_fifo.read() ); } - r_sc_upt_index = index; - r_sc_fsm = SC_UPT_HEAP_LOCK; + r_cas_upt_index = index; + r_cas_fsm = CAS_UPT_HEAP_LOCK; } else // releases the locks protecting UPT and DIR UPT full { - r_sc_fsm = SC_WAIT; + r_cas_fsm = CAS_WAIT; } -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Register multi-update transaction in UPT" + std::cout << " Register multi-update transaction in UPT" << " / wok = " << wok << " / nline = " << std::hex << nline @@ -4504,85 +4566,85 @@ } ///////////// - case SC_WAIT: // release all locks and retry from beginning - { - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + case CAS_WAIT: // release all locks and retry from beginning + { + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Release all locks" << std::endl; + std::cout << " Release all locks" << std::endl; } #endif - r_sc_fsm = SC_DIR_REQ; + r_cas_fsm = CAS_DIR_REQ; break; } ////////////////// - case SC_UPT_HEAP_LOCK: // lock the heap - { - if( r_alloc_heap_fsm.read() == ALLOC_HEAP_SC ) - { - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + case CAS_UPT_HEAP_LOCK: // lock the heap + { + if( r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS ) + { + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Get access to the heap" << std::endl; + std::cout << " Get access to the heap" << std::endl; } #endif - r_sc_fsm = SC_UPT_REQ; + r_cas_fsm = CAS_UPT_REQ; } break; } //////////////// - case SC_UPT_REQ: // send a first update request to INIT_CMD FSM - { - assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_SC) and + case CAS_UPT_REQ: // send a first update request to INIT_CMD FSM + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and "VCI_MEM_CACHE ERROR : bad HEAP allocation"); - if( !r_sc_to_init_cmd_multi_req.read() && !r_sc_to_init_cmd_brdcast_req.read() ) - { - r_sc_to_init_cmd_brdcast_req = false; - r_sc_to_init_cmd_trdid = r_sc_upt_index.read(); - r_sc_to_init_cmd_nline = m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - r_sc_to_init_cmd_index = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - r_sc_to_init_cmd_wdata = r_sc_wdata.read(); - - if(r_sc_cpt.read() == 4) + if( !r_cas_to_init_cmd_multi_req.read() && !r_cas_to_init_cmd_brdcast_req.read() ) + { + r_cas_to_init_cmd_brdcast_req = false; + r_cas_to_init_cmd_trdid = r_cas_upt_index.read(); + r_cas_to_init_cmd_nline = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_init_cmd_index = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_init_cmd_wdata = r_cas_wdata.read(); + + if(r_cas_cpt.read() == 4) { - r_sc_to_init_cmd_is_long = true; - r_sc_to_init_cmd_wdata_high = m_cmd_sc_wdata_fifo.read(); + r_cas_to_init_cmd_is_long = true; + r_cas_to_init_cmd_wdata_high = m_cmd_cas_wdata_fifo.read(); } else { - r_sc_to_init_cmd_is_long = false; - r_sc_to_init_cmd_wdata_high = 0; + r_cas_to_init_cmd_is_long = false; + r_cas_to_init_cmd_wdata_high = 0; } // We put the first copy in the fifo - sc_to_init_cmd_fifo_put = true; - sc_to_init_cmd_fifo_inst = r_sc_copy_inst.read(); - sc_to_init_cmd_fifo_srcid = r_sc_copy.read(); + cas_to_init_cmd_fifo_put = true; + cas_to_init_cmd_fifo_inst = r_cas_copy_inst.read(); + cas_to_init_cmd_fifo_srcid = r_cas_copy.read(); #if L1_MULTI_CACHE - sc_to_init_cmd_fifo_cache_id= r_sc_copy_cache.read(); -#endif - if(r_sc_count.read() == 1) // one single copy + cas_to_init_cmd_fifo_cache_id= r_cas_copy_cache.read(); +#endif + if(r_cas_count.read() == 1) // one single copy { - r_sc_fsm = SC_IDLE; // Response will be sent after receiving + r_cas_fsm = CAS_IDLE; // Response will be sent after receiving // update responses - cmd_sc_fifo_get = true; - r_sc_to_init_cmd_multi_req = true; - r_sc_cpt = 0; + cmd_cas_fifo_get = true; + r_cas_to_init_cmd_multi_req = true; + r_cas_cpt = 0; } else // several copies { - r_sc_fsm = SC_UPT_NEXT; + r_cas_fsm = CAS_UPT_NEXT; } -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Send the first update request to INIT_CMD FSM " - << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() - << " / wdata = " << std::hex << r_sc_wdata.read() - << " / srcid = " << std::dec << r_sc_copy.read() - << " / inst = " << std::dec << r_sc_copy_inst.read() << std::endl; + std::cout << " Send the first update request to INIT_CMD FSM " + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / wdata = " << std::hex << r_cas_wdata.read() + << " / srcid = " << std::dec << r_cas_copy.read() + << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl; } #endif @@ -4591,36 +4653,36 @@ } ///////////////// - case SC_UPT_NEXT: // send a multi-update request to INIT_CMD FSM - { - assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_SC) + case CAS_UPT_NEXT: // send a multi-update request to INIT_CMD FSM + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and "VCI_MEM_CACHE ERROR : bad HEAP allocation"); - HeapEntry entry = m_heap.read(r_sc_ptr.read()); - sc_to_init_cmd_fifo_srcid = entry.owner.srcid; + HeapEntry entry = m_heap.read(r_cas_ptr.read()); + cas_to_init_cmd_fifo_srcid = entry.owner.srcid; #if L1_MULTI_CACHE - sc_to_init_cmd_fifo_cache_id = entry.owner.cache_id; -#endif - sc_to_init_cmd_fifo_inst = entry.owner.inst; - sc_to_init_cmd_fifo_put = true; - - if( m_sc_to_init_cmd_inst_fifo.wok() ) // request accepted by INIT_CMD FSM - { - r_sc_ptr = entry.next; - if( entry.next == r_sc_ptr.read() ) // last copy + cas_to_init_cmd_fifo_cache_id = entry.owner.cache_id; +#endif + cas_to_init_cmd_fifo_inst = entry.owner.inst; + cas_to_init_cmd_fifo_put = true; + + if( m_cas_to_init_cmd_inst_fifo.wok() ) // request accepted by INIT_CMD FSM + { + r_cas_ptr = entry.next; + if( entry.next == r_cas_ptr.read() ) // last copy { - r_sc_to_init_cmd_multi_req = true; - r_sc_fsm = SC_IDLE; // Response will be sent after receiving + r_cas_to_init_cmd_multi_req = true; + r_cas_fsm = CAS_IDLE; // Response will be sent after receiving // all update responses - cmd_sc_fifo_get = true; - r_sc_cpt = 0; + cmd_cas_fifo_get = true; + r_cas_cpt = 0; } } -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Send the next update request to INIT_CMD FSM " - << " / address = " << std::hex << m_cmd_sc_addr_fifo.read() - << " / wdata = " << std::hex << r_sc_wdata.read() + std::cout << " Send the next update request to INIT_CMD FSM " + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / wdata = " << std::hex << r_cas_wdata.read() << " / srcid = " << std::dec << entry.owner.srcid << " / inst = " << std::dec << entry.owner.inst << std::endl; @@ -4630,27 +4692,27 @@ } ///////////////////// - case SC_BC_TRT_LOCK: // check the TRT to register a PUT transaction - { - if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) - { - if( !r_sc_to_ixr_cmd_req ) // we can transfer the request to IXR_CMD FSM + case CAS_BC_TRT_LOCK: // check the TRT to register a PUT transaction + { + if( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS ) + { + if( !r_cas_to_ixr_cmd_req ) // we can transfer the request to IXR_CMD FSM { // fill the data buffer - size_t way = r_sc_way.read(); - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t word = m_x[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; + size_t way = r_cas_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; for(size_t i = 0; i Register a broadcast inval transaction in UPT" + std::cout << " Register a broadcast inval transaction in UPT" << " / nline = " << nline << " / count = " << nb_copies @@ -4734,5 +4796,5 @@ else // releases the lock protecting UPT { - r_sc_fsm = SC_WAIT; + r_cas_fsm = CAS_WAIT; } } @@ -4740,14 +4802,14 @@ } ////////////////// - case SC_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry - { - if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) && - (r_alloc_upt_fsm.read() == ALLOC_UPT_SC ) && - (r_alloc_dir_fsm.read() == ALLOC_DIR_SC )) + case CAS_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry + { + if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS ) && + (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS ) && + (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS )) { // set TRT - m_transaction_tab.set(r_sc_trt_index.read(), + m_transaction_tab.set(r_cas_trt_index.read(), false, // PUT request to XRAM - m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())], + m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())], 0, 0, @@ -4773,15 +4835,15 @@ entry.owner.inst = false; entry.ptr = 0; - size_t set = m_y[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - size_t way = r_sc_way.read(); + size_t set = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t way = r_cas_way.read(); m_cache_directory.write(set, way, entry); - r_sc_fsm = SC_BC_CC_SEND; - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + r_cas_fsm = CAS_BC_CC_SEND; + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Register the PUT in TRT and invalidate DIR entry" - << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())] + std::cout << " Register the PUT in TRT and invalidate DIR entry" + << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())] << " / set = " << std::dec << set << " / way = " << way << std::endl; } @@ -4790,44 +4852,44 @@ else { - assert(false and "LOCK ERROR in SC_FSM, STATE = SC_BC_DIR_INVAL"); + assert(false and "LOCK ERROR in CAS_FSM, STATE = CAS_BC_DIR_INVAL"); } break; } /////////////////// - case SC_BC_CC_SEND: // Request the broadcast inval to INIT_CMD FSM - { - if ( !r_sc_to_init_cmd_multi_req.read() && - !r_sc_to_init_cmd_brdcast_req.read()) - { - r_sc_to_init_cmd_multi_req = false; - r_sc_to_init_cmd_brdcast_req = true; - r_sc_to_init_cmd_trdid = r_sc_upt_index.read(); - r_sc_to_init_cmd_nline = m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - r_sc_to_init_cmd_index = 0; - r_sc_to_init_cmd_wdata = 0; - - r_sc_fsm = SC_BC_XRAM_REQ; + case CAS_BC_CC_SEND: // Request the broadcast inval to INIT_CMD FSM + { + if ( !r_cas_to_init_cmd_multi_req.read() && + !r_cas_to_init_cmd_brdcast_req.read()) + { + r_cas_to_init_cmd_multi_req = false; + r_cas_to_init_cmd_brdcast_req = true; + r_cas_to_init_cmd_trdid = r_cas_upt_index.read(); + r_cas_to_init_cmd_nline = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_init_cmd_index = 0; + r_cas_to_init_cmd_wdata = 0; + + r_cas_fsm = CAS_BC_XRAM_REQ; } break; } //////////////////// - case SC_BC_XRAM_REQ: // request the IXR FSM to start a put transaction - { - if ( !r_sc_to_ixr_cmd_req ) - { - r_sc_to_ixr_cmd_req = true; - r_sc_to_ixr_cmd_write = true; - r_sc_to_ixr_cmd_nline = m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]; - r_sc_to_ixr_cmd_trdid = r_sc_trt_index.read(); - r_sc_fsm = SC_IDLE; - cmd_sc_fifo_get = true; - r_sc_cpt = 0; - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + case CAS_BC_XRAM_REQ: // request the IXR FSM to start a put transaction + { + if ( !r_cas_to_ixr_cmd_req ) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_write = true; + r_cas_to_ixr_cmd_nline = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_ixr_cmd_trdid = r_cas_trt_index.read(); + r_cas_fsm = CAS_IDLE; + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex - << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] - << " / trt_index = " << r_sc_trt_index.read() << std::endl; + std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex + << " / nline = " << m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()] + << " / trt_index = " << r_cas_trt_index.read() << std::endl; } #endif @@ -4835,5 +4897,5 @@ else { - std::cout << "MEM_CACHE, SC_BC_XRAM_REQ state : request should not have been previously set" + std::cout << "MEM_CACHE, CAS_BC_XRAM_REQ state : request should not have been previously set" << std::endl; } @@ -4841,21 +4903,21 @@ } ///////////////// - case SC_RSP_FAIL: // request TGT_RSP FSM to send a failure response - { - if( !r_sc_to_tgt_rsp_req ) - { - cmd_sc_fifo_get = true; - r_sc_cpt = 0; - r_sc_to_tgt_rsp_req = true; - r_sc_to_tgt_rsp_data = 1; - r_sc_to_tgt_rsp_srcid = m_cmd_sc_srcid_fifo.read(); - r_sc_to_tgt_rsp_trdid = m_cmd_sc_trdid_fifo.read(); - r_sc_to_tgt_rsp_pktid = m_cmd_sc_pktid_fifo.read(); - r_sc_fsm = SC_IDLE; - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response + { + if( !r_cas_to_tgt_rsp_req ) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 1; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Request TGT_RSP to send a failure response" << std::endl; + std::cout << " Request TGT_RSP to send a failure response" << std::endl; } #endif @@ -4864,21 +4926,21 @@ } //////////////////// - case SC_RSP_SUCCESS: // request TGT_RSP FSM to send a success response - { - if( !r_sc_to_tgt_rsp_req ) - { - cmd_sc_fifo_get = true; - r_sc_cpt = 0; - r_sc_to_tgt_rsp_req = true; - r_sc_to_tgt_rsp_data = 0; - r_sc_to_tgt_rsp_srcid = m_cmd_sc_srcid_fifo.read(); - r_sc_to_tgt_rsp_trdid = m_cmd_sc_trdid_fifo.read(); - r_sc_to_tgt_rsp_pktid = m_cmd_sc_pktid_fifo.read(); - r_sc_fsm = SC_IDLE; - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + case CAS_RSP_SUCCESS: // request TGT_RSP FSM to send a success response + { + if( !r_cas_to_tgt_rsp_req ) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 0; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Request TGT_RSP to send a success response" << std::endl; + std::cout << " Request TGT_RSP to send a success response" << std::endl; } #endif @@ -4887,19 +4949,19 @@ } ///////////////////// - case SC_MISS_TRT_LOCK: // cache miss : request access to transaction Table - { - if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) + case CAS_MISS_TRT_LOCK: // cache miss : request access to transaction Table + { + if( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS ) { size_t index = 0; bool hit_read = m_transaction_tab.hit_read( - m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()],index); + m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()],index); bool hit_write = m_transaction_tab.hit_write( - m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]); + m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()]); bool wok = !m_transaction_tab.full(index); -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Check TRT state" + std::cout << " Check TRT state" << " / hit_read = " << hit_read << " / hit_write = " << hit_write @@ -4911,10 +4973,10 @@ if ( hit_read || !wok || hit_write ) // missing line already requested or no space in TRT { - r_sc_fsm = SC_WAIT; + r_cas_fsm = CAS_WAIT; } else { - r_sc_trt_index = index; - r_sc_fsm = SC_MISS_TRT_SET; + r_cas_trt_index = index; + r_cas_fsm = CAS_MISS_TRT_SET; } } @@ -4922,7 +4984,7 @@ } //////////////////// - case SC_MISS_TRT_SET: // register the GET transaction in TRT - { - if( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ) + case CAS_MISS_TRT_SET: // register the GET transaction in TRT + { + if( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS ) { std::vector be_vector; @@ -4936,10 +4998,10 @@ } - m_transaction_tab.set(r_sc_trt_index.read(), + m_transaction_tab.set(r_cas_trt_index.read(), true, // read request - m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()], - m_cmd_sc_srcid_fifo.read(), - m_cmd_sc_trdid_fifo.read(), - m_cmd_sc_pktid_fifo.read(), + m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()], + m_cmd_cas_srcid_fifo.read(), + m_cmd_cas_trdid_fifo.read(), + m_cmd_cas_pktid_fifo.read(), false, // write request from processor 0, @@ -4947,12 +5009,12 @@ be_vector, data_vector); - r_sc_fsm = SC_MISS_XRAM_REQ; - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + r_cas_fsm = CAS_MISS_XRAM_REQ; + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Register a GET transaction in TRT" << std::hex - << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] - << " / trt_index = " << r_sc_trt_index.read() << std::endl; + std::cout << " Register a GET transaction in TRT" << std::hex + << " / nline = " << m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()] + << " / trt_index = " << r_cas_trt_index.read() << std::endl; } #endif @@ -4961,20 +5023,20 @@ } ////////////////////// - case SC_MISS_XRAM_REQ: // request the IXR_CMD FSM to fetch the missing line - { - if ( !r_sc_to_ixr_cmd_req ) - { - r_sc_to_ixr_cmd_req = true; - r_sc_to_ixr_cmd_write = false; - r_sc_to_ixr_cmd_trdid = r_sc_trt_index.read(); - r_sc_to_ixr_cmd_nline = m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]; - r_sc_fsm = SC_WAIT; - -#if DEBUG_MEMC_SC -if( m_debug_sc_fsm ) + case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM to fetch the missing line + { + if ( !r_cas_to_ixr_cmd_req ) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_write = false; + r_cas_to_ixr_cmd_trdid = r_cas_trt_index.read(); + r_cas_to_ixr_cmd_nline = m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()]; + r_cas_fsm = CAS_WAIT; + +#if DEBUG_MEMC_CAS +if( m_debug_cas_fsm ) { - std::cout << " Request a GET transaction to IXR_CMD FSM" << std::hex - << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()] - << " / trt_index = " << r_sc_trt_index.read() << std::endl; + std::cout << " Request a GET transaction to IXR_CMD FSM" << std::hex + << " / nline = " << m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()] + << " / trt_index = " << r_cas_trt_index.read() << std::endl; } #endif @@ -4982,5 +5044,5 @@ break; } - } // end switch r_sc_fsm + } // end switch r_cas_fsm @@ -4992,11 +5054,11 @@ // // It implements a round-robin priority between the three possible client FSMs - // XRAM_RSP, WRITE and SC. Each FSM can request two types of services: + // XRAM_RSP, WRITE and CAS. Each FSM can request two types of services: // - r_xram_rsp_to_init_cmd_multi_req : multi-inval // r_xram_rsp_to_init_cmd_brdcast_req : broadcast-inval // - r_write_to_init_cmd_multi_req : multi-update // r_write_to_init_cmd_brdcast_req : broadcast-inval - // - r_sc_to_init_cmd_multi_req : multi-update - // r_sc_to_init_cmd_brdcast_req : broadcast-inval + // - r_cas_to_init_cmd_multi_req : multi-update + // r_cas_to_init_cmd_brdcast_req : broadcast-inval // // An inval request is a single cell VCI write command containing the @@ -5035,13 +5097,13 @@ m_cpt_inval++; } - else if ( m_sc_to_init_cmd_inst_fifo.rok() || - r_sc_to_init_cmd_multi_req.read() ) - { - r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE; + else if ( m_cas_to_init_cmd_inst_fifo.rok() || + r_cas_to_init_cmd_multi_req.read() ) + { + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE; m_cpt_update++; } - else if( r_sc_to_init_cmd_brdcast_req.read() ) - { - r_init_cmd_fsm = INIT_CMD_SC_BRDCAST; + else if( r_cas_to_init_cmd_brdcast_req.read() ) + { + r_init_cmd_fsm = INIT_CMD_CAS_BRDCAST; m_cpt_inval++; } @@ -5062,13 +5124,13 @@ m_cpt_inval++; } - else if ( m_sc_to_init_cmd_inst_fifo.rok() || - r_sc_to_init_cmd_multi_req.read() ) - { - r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE; + else if ( m_cas_to_init_cmd_inst_fifo.rok() || + r_cas_to_init_cmd_multi_req.read() ) + { + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE; m_cpt_update++; } - else if( r_sc_to_init_cmd_brdcast_req.read() ) - { - r_init_cmd_fsm = INIT_CMD_SC_BRDCAST; + else if( r_cas_to_init_cmd_brdcast_req.read() ) + { + r_init_cmd_fsm = INIT_CMD_CAS_BRDCAST; m_cpt_inval++; } @@ -5087,15 +5149,15 @@ } ////////////////////////// - case INIT_CMD_SC_UPDT_IDLE: // SC FSM has highest priority - { - if ( m_sc_to_init_cmd_inst_fifo.rok() || - r_sc_to_init_cmd_multi_req.read() ) - { - r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE; + case INIT_CMD_CAS_UPDT_IDLE: // CAS FSM has highest priority + { + if ( m_cas_to_init_cmd_inst_fifo.rok() || + r_cas_to_init_cmd_multi_req.read() ) + { + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE; m_cpt_update++; } - else if( r_sc_to_init_cmd_brdcast_req.read() ) - { - r_init_cmd_fsm = INIT_CMD_SC_BRDCAST; + else if( r_cas_to_init_cmd_brdcast_req.read() ) + { + r_init_cmd_fsm = INIT_CMD_CAS_BRDCAST; m_cpt_inval++; } @@ -5217,51 +5279,51 @@ } ///////////////////////// - case INIT_CMD_SC_BRDCAST: // send a broadcast-inval (from SC FSM) + case INIT_CMD_CAS_BRDCAST: // send a broadcast-inval (from CAS FSM) { if( p_vci_ini.cmdack ) { m_cpt_inval_brdcast++; - r_sc_to_init_cmd_brdcast_req = false; - r_init_cmd_fsm = INIT_CMD_SC_UPDT_IDLE; + r_cas_to_init_cmd_brdcast_req = false; + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_IDLE; } break; } //////////////////////////// - case INIT_CMD_SC_UPDT_NLINE: // send nline for a multi-update (from SC FSM) - { - if ( m_sc_to_init_cmd_inst_fifo.rok() ) + case INIT_CMD_CAS_UPDT_NLINE: // send nline for a multi-update (from CAS FSM) + { + if ( m_cas_to_init_cmd_inst_fifo.rok() ) { if ( p_vci_ini.cmdack ) { m_cpt_update_mult++; - r_init_cmd_fsm = INIT_CMD_SC_UPDT_INDEX; + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_INDEX; } } else { - if( r_sc_to_init_cmd_multi_req.read() ) r_sc_to_init_cmd_multi_req = false; - r_init_cmd_fsm = INIT_CMD_SC_UPDT_IDLE; + if( r_cas_to_init_cmd_multi_req.read() ) r_cas_to_init_cmd_multi_req = false; + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_IDLE; } break; } //////////////////////////// - case INIT_CMD_SC_UPDT_INDEX: // send word index for a multi-update (from SC FSM) - { - if ( p_vci_ini.cmdack ) r_init_cmd_fsm = INIT_CMD_SC_UPDT_DATA; + case INIT_CMD_CAS_UPDT_INDEX: // send word index for a multi-update (from CAS FSM) + { + if ( p_vci_ini.cmdack ) r_init_cmd_fsm = INIT_CMD_CAS_UPDT_DATA; break; } /////////////////////////// - case INIT_CMD_SC_UPDT_DATA: // send first data for a multi-update (from SC FSM) + case INIT_CMD_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) { if ( p_vci_ini.cmdack ) { - if ( r_sc_to_init_cmd_is_long.read() ) + if ( r_cas_to_init_cmd_is_long.read() ) { - r_init_cmd_fsm = INIT_CMD_SC_UPDT_DATA_HIGH; + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_DATA_HIGH; } else { - sc_to_init_cmd_fifo_get = true; - r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE; + cas_to_init_cmd_fifo_get = true; + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE; } } @@ -5269,10 +5331,10 @@ } //////////////////////// - case INIT_CMD_SC_UPDT_DATA_HIGH: // send second data for a multi-update (from SC FSM) + case INIT_CMD_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) { if ( p_vci_ini.cmdack ) { - sc_to_init_cmd_fifo_get = true; - r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE; + cas_to_init_cmd_fifo_get = true; + r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE; } break; @@ -5287,9 +5349,9 @@ // - r_read_to_tgt_rsp_req // - r_write_to_tgt_rsp_req - // - r_sc_to_tgt_rsp_req + // - r_cas_to_tgt_rsp_req // - r_cleanup_to_tgt_rsp_req // - r_xram_rsp_to_tgt_rsp_req // - r_init_rsp_to_tgt_rsp_req - // The ordering is : read > write > sc > xram > init > cleanup + // The ordering is : read > write > cas > xram > init > cleanup ///////////////////////////////////////////////////////////////////// @@ -5300,5 +5362,5 @@ { if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; + else if ( r_cas_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CAS ; else if ( r_xram_rsp_to_tgt_rsp_req ) { @@ -5306,5 +5368,5 @@ r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); } - else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; + else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT ; else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; else if ( r_read_to_tgt_rsp_req ) @@ -5316,7 +5378,7 @@ } //////////////////////// - case TGT_RSP_WRITE_IDLE: // sc requests have the highest priority - { - if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; + case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority + { + if ( r_cas_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CAS; else if ( r_xram_rsp_to_tgt_rsp_req ) { @@ -5324,5 +5386,5 @@ r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); } - else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; + else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT ; else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; else if ( r_read_to_tgt_rsp_req ) @@ -5336,5 +5398,5 @@ } /////////////////////// - case TGT_RSP_SC_IDLE: // xram_rsp requests have the highest priority + case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority { if ( r_xram_rsp_to_tgt_rsp_req ) @@ -5343,5 +5405,20 @@ r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); } - else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; + else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT ; + else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if ( r_read_to_tgt_rsp_req ) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if ( r_cas_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CAS ; + break; + } + /////////////////////// + case TGT_RSP_XRAM_IDLE: // init requests have the highest priority + { + + if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT ; else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; else if ( r_read_to_tgt_rsp_req ) @@ -5351,20 +5428,5 @@ } else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; - break; - } - /////////////////////// - case TGT_RSP_XRAM_IDLE: // init requests have the highest priority - { - - if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; - else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if ( r_read_to_tgt_rsp_req ) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; + else if ( r_cas_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CAS ; else if ( r_xram_rsp_to_tgt_rsp_req ) { @@ -5384,5 +5446,5 @@ } else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; + else if ( r_cas_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CAS ; else if ( r_xram_rsp_to_tgt_rsp_req ) { @@ -5402,5 +5464,5 @@ } else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if ( r_sc_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_SC; + else if ( r_cas_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CAS ; else if ( r_xram_rsp_to_tgt_rsp_req ) { @@ -5408,5 +5470,5 @@ r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); } - else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT; + else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT ; else if ( r_cleanup_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; break; @@ -5424,4 +5486,5 @@ << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read() << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_read_to_tgt_rsp_pktid.read() << " / rdata = " << std::hex << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; @@ -5451,5 +5514,6 @@ std::cout << " Write response" << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() << std::endl; + << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; } #endif @@ -5470,5 +5534,6 @@ std::cout << " Cleanup response" << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() << std::endl; + << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; } #endif @@ -5479,5 +5544,5 @@ } ////////////////// - case TGT_RSP_SC: // send one atomic word response + case TGT_RSP_CAS: // send one atomic word response { if ( p_vci_tgt.rspack ) @@ -5487,11 +5552,12 @@ if( m_debug_tgt_rsp_fsm ) { - std::cout << " SC response" - << " / rsrcid = " << std::dec << r_sc_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_sc_to_tgt_rsp_trdid.read() << std::endl; + std::cout << " CAS response" + << " / rsrcid = " << std::dec << r_cas_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; } #endif - r_tgt_rsp_fsm = TGT_RSP_SC_IDLE; - r_sc_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE; + r_cas_to_tgt_rsp_req = false; } break; @@ -5510,4 +5576,5 @@ << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read() << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() << " / rdata = " << std::hex << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; @@ -5539,5 +5606,6 @@ std::cout << " Write response after coherence transaction" << " / rsrcid = " << std::dec << r_init_rsp_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_init_rsp_to_tgt_rsp_trdid.read() << std::endl; + << " / rtrdid = " << r_init_rsp_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_init_rsp_to_tgt_rsp_pktid.read() << std::endl; } #endif @@ -5579,7 +5647,7 @@ r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if (( r_sc_fsm.read() == SC_UPT_LOCK ) || - ( r_sc_fsm.read() == SC_BC_UPT_LOCK )) - r_alloc_upt_fsm = ALLOC_UPT_SC; + else if (( r_cas_fsm.read() == CAS_UPT_LOCK ) || + ( r_cas_fsm.read() == CAS_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_CAS; } break; @@ -5596,7 +5664,7 @@ r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if (( r_sc_fsm.read() == SC_UPT_LOCK ) || - ( r_sc_fsm.read() == SC_BC_UPT_LOCK )) - r_alloc_upt_fsm = ALLOC_UPT_SC; + else if (( r_cas_fsm.read() == CAS_UPT_LOCK ) || + ( r_cas_fsm.read() == CAS_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_CAS; else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK ) @@ -5612,7 +5680,7 @@ r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if (( r_sc_fsm.read() == SC_UPT_LOCK ) || - ( r_sc_fsm.read() == SC_BC_UPT_LOCK )) - r_alloc_upt_fsm = ALLOC_UPT_SC; + else if (( r_cas_fsm.read() == CAS_UPT_LOCK ) || + ( r_cas_fsm.read() == CAS_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_CAS; else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK ) @@ -5629,7 +5697,7 @@ if(r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) { - if (( r_sc_fsm.read() == SC_UPT_LOCK ) || - ( r_sc_fsm.read() == SC_BC_UPT_LOCK )) - r_alloc_upt_fsm = ALLOC_UPT_SC; + if (( r_cas_fsm.read() == CAS_UPT_LOCK ) || + ( r_cas_fsm.read() == CAS_BC_UPT_LOCK )) + r_alloc_upt_fsm = ALLOC_UPT_CAS; else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK ) @@ -5646,7 +5714,7 @@ ////////////////////////// - case ALLOC_UPT_SC: - if (( r_sc_fsm.read() != SC_UPT_LOCK ) && - ( r_sc_fsm.read() != SC_BC_UPT_LOCK )) + case ALLOC_UPT_CAS: + if (( r_cas_fsm.read() != CAS_UPT_LOCK ) && + ( r_cas_fsm.read() != CAS_BC_UPT_LOCK )) { if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK ) @@ -5672,5 +5740,5 @@ // The ALLOC_DIR FSM allocates the access to the directory and // the data cache with a round robin priority between 5 user FSMs : - // The cyclic ordering is READ > WRITE > SC > CLEANUP > XRAM_RSP + // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP // The ressource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// @@ -5704,6 +5772,6 @@ r_alloc_dir_fsm = ALLOC_DIR_WRITE; - else if (r_sc_fsm.read() == SC_DIR_REQ) - r_alloc_dir_fsm = ALLOC_DIR_SC; + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) @@ -5733,6 +5801,6 @@ ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ))) { - if ( r_sc_fsm.read() == SC_DIR_REQ ) - r_alloc_dir_fsm = ALLOC_DIR_SC; + if ( r_cas_fsm.read() == CAS_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; else if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) @@ -5748,20 +5816,20 @@ //////////////////// - case ALLOC_DIR_SC: - if ((( r_sc_fsm.read() != SC_DIR_REQ ) && - ( r_sc_fsm.read() != SC_DIR_LOCK ) && - ( r_sc_fsm.read() != SC_DIR_HIT_READ ) && - ( r_sc_fsm.read() != SC_DIR_HIT_WRITE ) && - ( r_sc_fsm.read() != SC_BC_TRT_LOCK ) && - ( r_sc_fsm.read() != SC_BC_UPT_LOCK ) && - ( r_sc_fsm.read() != SC_MISS_TRT_LOCK ) && - ( r_sc_fsm.read() != SC_UPT_LOCK ) && - ( r_sc_fsm.read() != SC_UPT_HEAP_LOCK )) + case ALLOC_DIR_CAS: + if ((( r_cas_fsm.read() != CAS_DIR_REQ ) && + ( r_cas_fsm.read() != CAS_DIR_LOCK ) && + ( r_cas_fsm.read() != CAS_DIR_HIT_READ ) && + ( r_cas_fsm.read() != CAS_DIR_HIT_WRITE ) && + ( r_cas_fsm.read() != CAS_BC_TRT_LOCK ) && + ( r_cas_fsm.read() != CAS_BC_UPT_LOCK ) && + ( r_cas_fsm.read() != CAS_MISS_TRT_LOCK ) && + ( r_cas_fsm.read() != CAS_UPT_LOCK ) && + ( r_cas_fsm.read() != CAS_UPT_HEAP_LOCK )) || - (( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) && - ( r_alloc_heap_fsm.read() == ALLOC_HEAP_SC )) + (( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK ) && + ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS )) || - (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) && - ( r_alloc_trt_fsm.read() == ALLOC_TRT_SC ))) + (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) && + ( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS ))) { if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) @@ -5795,6 +5863,6 @@ r_alloc_dir_fsm = ALLOC_DIR_WRITE; - else if ( r_sc_fsm.read() == SC_DIR_REQ ) - r_alloc_dir_fsm = ALLOC_DIR_SC; + else if ( r_cas_fsm.read() == CAS_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; } break; @@ -5812,6 +5880,6 @@ r_alloc_dir_fsm = ALLOC_DIR_WRITE; - else if ( r_sc_fsm.read() == SC_DIR_REQ ) - r_alloc_dir_fsm = ALLOC_DIR_SC; + else if ( r_cas_fsm.read() == CAS_DIR_REQ ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; else if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) @@ -5827,5 +5895,5 @@ // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer) // with a round robin priority between 4 user FSMs : - // The cyclic priority is READ > WRITE > SC > XRAM_RSP + // The cyclic priority is READ > WRITE > CAS > XRAM_RSP // The ressource is always allocated. /////////////////////////////////////////////////////////////////////////////////// @@ -5841,7 +5909,7 @@ r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) || - ( r_sc_fsm.read() == SC_BC_TRT_LOCK )) - r_alloc_trt_fsm = ALLOC_TRT_SC; + else if (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) || + ( r_cas_fsm.read() == CAS_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_CAS; else if (( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) && @@ -5861,7 +5929,7 @@ ( r_write_fsm.read() != WRITE_BC_UPT_LOCK )) { - if (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) || - ( r_sc_fsm.read() == SC_BC_TRT_LOCK )) - r_alloc_trt_fsm = ALLOC_TRT_SC; + if (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) || + ( r_cas_fsm.read() == CAS_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_CAS; else if (( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) && @@ -5879,8 +5947,8 @@ //////////////////// - case ALLOC_TRT_SC: - if (( r_sc_fsm.read() != SC_MISS_TRT_LOCK ) && - ( r_sc_fsm.read() != SC_BC_TRT_LOCK ) && - ( r_sc_fsm.read() != SC_BC_UPT_LOCK )) + case ALLOC_TRT_CAS: + if (( r_cas_fsm.read() != CAS_MISS_TRT_LOCK ) && + ( r_cas_fsm.read() != CAS_BC_TRT_LOCK ) && + ( r_cas_fsm.read() != CAS_BC_UPT_LOCK )) { if (( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) && @@ -5920,7 +5988,7 @@ r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) || - ( r_sc_fsm.read() == SC_BC_TRT_LOCK )) - r_alloc_trt_fsm = ALLOC_TRT_SC; + else if (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) || + ( r_cas_fsm.read() == CAS_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_CAS; } break; @@ -5938,7 +6006,7 @@ r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if (( r_sc_fsm.read() == SC_MISS_TRT_LOCK ) || - ( r_sc_fsm.read() == SC_BC_TRT_LOCK )) - r_alloc_trt_fsm = ALLOC_TRT_SC; + else if (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) || + ( r_cas_fsm.read() == CAS_BC_TRT_LOCK )) + r_alloc_trt_fsm = ALLOC_TRT_CAS; else if (( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK ) && @@ -5955,5 +6023,5 @@ // The ALLOC_HEAP FSM allocates the access to the heap // with a round robin priority between 5 user FSMs : - // The cyclic ordering is READ > WRITE > SC > CLEANUP > XRAM_RSP + // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP // The ressource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// @@ -5983,6 +6051,6 @@ r_alloc_heap_fsm = ALLOC_HEAP_WRITE; - else if ( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) - r_alloc_heap_fsm = ALLOC_HEAP_SC; + else if ( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ ) @@ -6000,6 +6068,6 @@ ( r_write_fsm.read() != WRITE_UPT_NEXT )) { - if ( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) - r_alloc_heap_fsm = ALLOC_HEAP_SC; + if ( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ ) @@ -6015,8 +6083,8 @@ //////////////////// - case ALLOC_HEAP_SC: - if (( r_sc_fsm.read() != SC_UPT_HEAP_LOCK ) && - ( r_sc_fsm.read() != SC_UPT_REQ ) && - ( r_sc_fsm.read() != SC_UPT_NEXT )) + case ALLOC_HEAP_CAS: + if (( r_cas_fsm.read() != CAS_UPT_HEAP_LOCK ) && + ( r_cas_fsm.read() != CAS_UPT_REQ ) && + ( r_cas_fsm.read() != CAS_UPT_NEXT )) { if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ ) @@ -6050,6 +6118,6 @@ r_alloc_heap_fsm = ALLOC_HEAP_WRITE; - else if ( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) - r_alloc_heap_fsm = ALLOC_HEAP_SC; + else if ( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; } break; @@ -6066,6 +6134,6 @@ r_alloc_heap_fsm = ALLOC_HEAP_WRITE; - else if ( r_sc_fsm.read() == SC_UPT_HEAP_LOCK ) - r_alloc_heap_fsm = ALLOC_HEAP_SC; + else if ( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK ) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ ) @@ -6139,31 +6207,31 @@ } //////////////////////////////////////////////////////////////////////////////////// - // TGT_CMD to SC FIFO + // TGT_CMD to CAS FIFO //////////////////////////////////////////////////////////////////////////////////// - if ( cmd_sc_fifo_put ) { - if ( cmd_sc_fifo_get ) { - m_cmd_sc_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read())); - m_cmd_sc_eop_fifo.put_and_get(p_vci_tgt.eop.read()); - m_cmd_sc_srcid_fifo.put_and_get(p_vci_tgt.srcid.read()); - m_cmd_sc_trdid_fifo.put_and_get(p_vci_tgt.trdid.read()); - m_cmd_sc_pktid_fifo.put_and_get(p_vci_tgt.pktid.read()); - m_cmd_sc_wdata_fifo.put_and_get(p_vci_tgt.wdata.read()); + if ( cmd_cas_fifo_put ) { + if ( cmd_cas_fifo_get ) { + m_cmd_cas_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read())); + m_cmd_cas_eop_fifo.put_and_get(p_vci_tgt.eop.read()); + m_cmd_cas_srcid_fifo.put_and_get(p_vci_tgt.srcid.read()); + m_cmd_cas_trdid_fifo.put_and_get(p_vci_tgt.trdid.read()); + m_cmd_cas_pktid_fifo.put_and_get(p_vci_tgt.pktid.read()); + m_cmd_cas_wdata_fifo.put_and_get(p_vci_tgt.wdata.read()); } else { - m_cmd_sc_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read())); - m_cmd_sc_eop_fifo.simple_put(p_vci_tgt.eop.read()); - m_cmd_sc_srcid_fifo.simple_put(p_vci_tgt.srcid.read()); - m_cmd_sc_trdid_fifo.simple_put(p_vci_tgt.trdid.read()); - m_cmd_sc_pktid_fifo.simple_put(p_vci_tgt.pktid.read()); - m_cmd_sc_wdata_fifo.simple_put(p_vci_tgt.wdata.read()); + m_cmd_cas_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read())); + m_cmd_cas_eop_fifo.simple_put(p_vci_tgt.eop.read()); + m_cmd_cas_srcid_fifo.simple_put(p_vci_tgt.srcid.read()); + m_cmd_cas_trdid_fifo.simple_put(p_vci_tgt.trdid.read()); + m_cmd_cas_pktid_fifo.simple_put(p_vci_tgt.pktid.read()); + m_cmd_cas_wdata_fifo.simple_put(p_vci_tgt.wdata.read()); } } else { - if ( cmd_sc_fifo_get ) { - m_cmd_sc_addr_fifo.simple_get(); - m_cmd_sc_eop_fifo.simple_get(); - m_cmd_sc_srcid_fifo.simple_get(); - m_cmd_sc_trdid_fifo.simple_get(); - m_cmd_sc_pktid_fifo.simple_get(); - m_cmd_sc_wdata_fifo.simple_get(); + if ( cmd_cas_fifo_get ) { + m_cmd_cas_addr_fifo.simple_get(); + m_cmd_cas_eop_fifo.simple_get(); + m_cmd_cas_srcid_fifo.simple_get(); + m_cmd_cas_trdid_fifo.simple_get(); + m_cmd_cas_pktid_fifo.simple_get(); + m_cmd_cas_wdata_fifo.simple_get(); } } @@ -6223,27 +6291,27 @@ } //////////////////////////////////////////////////////////////////////////////////// - // SC to INIT_CMD FIFO + // CAS to INIT_CMD FIFO //////////////////////////////////////////////////////////////////////////////////// - if ( sc_to_init_cmd_fifo_put ) { - if ( sc_to_init_cmd_fifo_get ) { - m_sc_to_init_cmd_inst_fifo.put_and_get(sc_to_init_cmd_fifo_inst); - m_sc_to_init_cmd_srcid_fifo.put_and_get(sc_to_init_cmd_fifo_srcid); + if ( cas_to_init_cmd_fifo_put ) { + if ( cas_to_init_cmd_fifo_get ) { + m_cas_to_init_cmd_inst_fifo.put_and_get(cas_to_init_cmd_fifo_inst); + m_cas_to_init_cmd_srcid_fifo.put_and_get(cas_to_init_cmd_fifo_srcid); #if L1_MULTI_CACHE - m_sc_to_init_cmd_cache_id_fifo.put_and_get(sc_to_init_cmd_fifo_cache_id); + m_cas_to_init_cmd_cache_id_fifo.put_and_get(cas_to_init_cmd_fifo_cache_id); #endif } else { - m_sc_to_init_cmd_inst_fifo.simple_put(sc_to_init_cmd_fifo_inst); - m_sc_to_init_cmd_srcid_fifo.simple_put(sc_to_init_cmd_fifo_srcid); + m_cas_to_init_cmd_inst_fifo.simple_put(cas_to_init_cmd_fifo_inst); + m_cas_to_init_cmd_srcid_fifo.simple_put(cas_to_init_cmd_fifo_srcid); #if L1_MULTI_CACHE - m_sc_to_init_cmd_cache_id_fifo.simple_put(sc_to_init_cmd_fifo_cache_id); + m_cas_to_init_cmd_cache_id_fifo.simple_put(cas_to_init_cmd_fifo_cache_id); #endif } } else { - if ( sc_to_init_cmd_fifo_get ) { - m_sc_to_init_cmd_inst_fifo.simple_get(); - m_sc_to_init_cmd_srcid_fifo.simple_get(); + if ( cas_to_init_cmd_fifo_get ) { + m_cas_to_init_cmd_inst_fifo.simple_get(); + m_cas_to_init_cmd_srcid_fifo.simple_get(); #if L1_MULTI_CACHE - m_sc_to_init_cmd_cache_id_fifo.simple_get(); + m_cas_to_init_cmd_cache_id_fifo.simple_get(); #endif } @@ -6280,20 +6348,20 @@ p_vci_ixr.eop = true; } - else if ( r_ixr_cmd_fsm.read() == IXR_CMD_SC_NLINE ) { - if(r_sc_to_ixr_cmd_write.read()){ + else if ( r_ixr_cmd_fsm.read() == IXR_CMD_CAS_NLINE ) { + if(r_cas_to_ixr_cmd_write.read()){ p_vci_ixr.cmd = vci_param::CMD_WRITE; p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)((r_sc_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4); + p_vci_ixr.address = (addr_t)((r_cas_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4); p_vci_ixr.plen = m_words*4; - p_vci_ixr.wdata = r_sc_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read(); - p_vci_ixr.trdid = r_sc_to_ixr_cmd_trdid.read(); + p_vci_ixr.wdata = r_cas_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read(); + p_vci_ixr.trdid = r_cas_to_ixr_cmd_trdid.read(); p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words-1)); } else { p_vci_ixr.cmd = vci_param::CMD_READ; p_vci_ixr.cmdval = true; - p_vci_ixr.address = (addr_t)(r_sc_to_ixr_cmd_nline.read()*m_words*4); + p_vci_ixr.address = (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4); p_vci_ixr.plen = m_words*4; p_vci_ixr.wdata = 0x00000000; - p_vci_ixr.trdid = r_sc_to_ixr_cmd_trdid.read(); + p_vci_ixr.trdid = r_cas_to_ixr_cmd_trdid.read(); p_vci_ixr.eop = true; } @@ -6358,9 +6426,9 @@ p_vci_tgt.cmdack = m_cmd_write_addr_fifo.wok(); break; - case TGT_CMD_ATOMIC: - p_vci_tgt.cmdack = m_cmd_sc_addr_fifo.wok(); + case TGT_CMD_CAS: + p_vci_tgt.cmdack = m_cmd_cas_addr_fifo.wok(); break; default: - p_vci_tgt.cmdack = false; + p_vci_tgt.cmdack = false; break; } @@ -6373,5 +6441,5 @@ case TGT_RSP_READ_IDLE: case TGT_RSP_WRITE_IDLE: - case TGT_RSP_SC_IDLE: + case TGT_RSP_CAS_IDLE: case TGT_RSP_XRAM_IDLE: case TGT_RSP_INIT_IDLE: @@ -6409,13 +6477,13 @@ p_vci_tgt.rtrdid = r_cleanup_to_tgt_rsp_trdid.read(); p_vci_tgt.rpktid = r_cleanup_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; // Can be a SC rsp + p_vci_tgt.rerror = 0; // Can be a CAS rsp p_vci_tgt.reop = true; break; - case TGT_RSP_SC: + case TGT_RSP_CAS: p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_sc_to_tgt_rsp_data.read(); - p_vci_tgt.rsrcid = r_sc_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_sc_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_sc_to_tgt_rsp_pktid.read(); + p_vci_tgt.rdata = r_cas_to_tgt_rsp_data.read(); + p_vci_tgt.rsrcid = r_cas_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_cas_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_cas_to_tgt_rsp_pktid.read(); p_vci_tgt.rerror = 0; p_vci_tgt.reop = true; @@ -6438,5 +6506,5 @@ p_vci_tgt.rtrdid = r_init_rsp_to_tgt_rsp_trdid.read(); p_vci_tgt.rpktid = r_init_rsp_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; // Can be a SC rsp + p_vci_tgt.rerror = 0; // Can be a CAS rsp p_vci_tgt.reop = true; break; @@ -6460,5 +6528,5 @@ case INIT_CMD_UPDT_IDLE: case INIT_CMD_INVAL_IDLE: - case INIT_CMD_SC_UPDT_IDLE: + case INIT_CMD_CAS_UPDT_IDLE: p_vci_ini.cmdval = false; p_vci_ini.address = 0; @@ -6578,21 +6646,21 @@ break; - case INIT_CMD_SC_BRDCAST: + case INIT_CMD_CAS_BRDCAST: p_vci_ini.cmdval = true; p_vci_ini.address = m_broadcast_address; - p_vci_ini.wdata = (addr_t)r_sc_to_init_cmd_nline.read(); - p_vci_ini.be = ((r_sc_to_init_cmd_nline.read() >> 32) & 0x3); + p_vci_ini.wdata = (addr_t)r_cas_to_init_cmd_nline.read(); + p_vci_ini.be = ((r_cas_to_init_cmd_nline.read() >> 32) & 0x3); p_vci_ini.plen = 4 ; p_vci_ini.eop = true; - p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); + p_vci_ini.trdid = r_cas_to_init_cmd_trdid.read(); p_vci_ini.pktid = 0; break; - case INIT_CMD_SC_UPDT_NLINE: + case INIT_CMD_CAS_UPDT_NLINE: vci_ini_address = (vci_addr_t) - m_sc_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); - - p_vci_ini.cmdval = m_sc_to_init_cmd_inst_fifo.rok(); - if(m_sc_to_init_cmd_inst_fifo.rok()){ - if( m_sc_to_init_cmd_inst_fifo.read() ) { + m_cas_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); + + p_vci_ini.cmdval = m_cas_to_init_cmd_inst_fifo.rok(); + if(m_cas_to_init_cmd_inst_fifo.rok()){ + if( m_cas_to_init_cmd_inst_fifo.read() ) { p_vci_ini.address = (addr_t)(vci_ini_address + 12); } else { @@ -6602,7 +6670,7 @@ p_vci_ini.address = 0; } - p_vci_ini.wdata = (uint32_t)r_sc_to_init_cmd_nline.read(); - p_vci_ini.be = ((r_sc_to_init_cmd_nline.read() >> 32 ) & 0x3); - if(r_sc_to_init_cmd_is_long.read()){ + p_vci_ini.wdata = (uint32_t)r_cas_to_init_cmd_nline.read(); + p_vci_ini.be = ((r_cas_to_init_cmd_nline.read() >> 32 ) & 0x3); + if(r_cas_to_init_cmd_is_long.read()){ p_vci_ini.plen = 4 * 4; } else { @@ -6610,49 +6678,49 @@ } p_vci_ini.eop = false; - p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); + p_vci_ini.trdid = r_cas_to_init_cmd_trdid.read(); #if L1_MULTI_CACHE - p_vci_ini.pktid = m_sc_to_init_cmd_cache_id_fifo.read(); + p_vci_ini.pktid = m_cas_to_init_cmd_cache_id_fifo.read(); #endif break; - case INIT_CMD_SC_UPDT_INDEX: + case INIT_CMD_CAS_UPDT_INDEX: vci_ini_address = (vci_addr_t) - m_sc_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); + m_cas_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); p_vci_ini.cmdval = true; - if( m_sc_to_init_cmd_inst_fifo.read() ) { + if( m_cas_to_init_cmd_inst_fifo.read() ) { p_vci_ini.address = (addr_t)(vci_ini_address + 12); } else { p_vci_ini.address = (addr_t)(vci_ini_address + 8); } - p_vci_ini.wdata = r_sc_to_init_cmd_index.read(); + p_vci_ini.wdata = r_cas_to_init_cmd_index.read(); p_vci_ini.be = 0xF; - if(r_sc_to_init_cmd_is_long.read()){ + if(r_cas_to_init_cmd_is_long.read()){ p_vci_ini.plen = 4 * 4; } else { p_vci_ini.plen = 4 * 3; } - p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); + p_vci_ini.trdid = r_cas_to_init_cmd_trdid.read(); #if L1_MULTI_CACHE - p_vci_ini.pktid = m_sc_to_init_cmd_cache_id_fifo.read(); + p_vci_ini.pktid = m_cas_to_init_cmd_cache_id_fifo.read(); #endif p_vci_ini.eop = false; break; - case INIT_CMD_SC_UPDT_DATA: + case INIT_CMD_CAS_UPDT_DATA: vci_ini_address = (vci_addr_t) - m_sc_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); + m_cas_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); p_vci_ini.cmdval = true; - if( m_sc_to_init_cmd_inst_fifo.read() ) { + if( m_cas_to_init_cmd_inst_fifo.read() ) { p_vci_ini.address = (addr_t)(vci_ini_address + 12); } else { p_vci_ini.address = (addr_t)(vci_ini_address + 8); } - p_vci_ini.wdata = r_sc_to_init_cmd_wdata.read(); + p_vci_ini.wdata = r_cas_to_init_cmd_wdata.read(); p_vci_ini.be = 0xF; - p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); + p_vci_ini.trdid = r_cas_to_init_cmd_trdid.read(); #if L1_MULTI_CACHE - p_vci_ini.pktid = m_sc_to_init_cmd_cache_id_fifo.read(); -#endif - if(r_sc_to_init_cmd_is_long.read()){ + p_vci_ini.pktid = m_cas_to_init_cmd_cache_id_fifo.read(); +#endif + if(r_cas_to_init_cmd_is_long.read()){ p_vci_ini.plen = 4 * 4; p_vci_ini.eop = false; @@ -6662,20 +6730,20 @@ } break; - case INIT_CMD_SC_UPDT_DATA_HIGH: + case INIT_CMD_CAS_UPDT_DATA_HIGH: vci_ini_address = (vci_addr_t) - m_sc_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); + m_cas_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S); p_vci_ini.cmdval = true; - if( m_sc_to_init_cmd_inst_fifo.read() ) { + if( m_cas_to_init_cmd_inst_fifo.read() ) { p_vci_ini.address = (addr_t)(vci_ini_address + 12); } else { p_vci_ini.address = (addr_t)(vci_ini_address + 8); } - p_vci_ini.wdata = r_sc_to_init_cmd_wdata_high.read(); + p_vci_ini.wdata = r_cas_to_init_cmd_wdata_high.read(); p_vci_ini.be = 0xF; p_vci_ini.plen = 4 * 4; - p_vci_ini.trdid = r_sc_to_init_cmd_trdid.read(); + p_vci_ini.trdid = r_cas_to_init_cmd_trdid.read(); #if L1_MULTI_CACHE - p_vci_ini.pktid = m_sc_to_init_cmd_cache_id_fifo.read(); + p_vci_ini.pktid = m_cas_to_init_cmd_cache_id_fifo.read(); #endif p_vci_ini.eop = true;