Index: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 284)
+++ trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 285)
@@ -2350,5 +2350,4 @@
                     {     
                     case iss_t::XTN_PTPR:   			// itlb & dtlb must be flushed
-                        r_mmu_ptpr       = m_dreq.wdata;
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_SWITCH;
@@ -3368,9 +3367,22 @@
     }
     ///////////////////////
-    case DCACHE_XTN_SWITCH:		// Both itlb and dtlb must be flushed
-    {
+    case DCACHE_XTN_SWITCH:		// The r_ptpr registers must be written,
+                                // and both itlb and dtlb must be flushed.
+                                // Caution : the itlb miss requests must be taken 
+                                // to avoid dead-lock in case of simultaneous ITLB miss
+    {
+        // itlb miss request
+        if ( r_icache_tlb_miss_req.read() )
+        {
+            r_dcache_tlb_ins    = true;
+            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
+            r_dcache_fsm        = DCACHE_TLB_MISS;
+            break;
+        }
+
         if ( not r_dcache_xtn_req.read() )
         {
             r_dtlb.flush();
+            r_mmu_ptpr   = m_dreq.wdata;
             r_dcache_fsm = DCACHE_IDLE;
             m_drsp.valid = true;
@@ -3380,6 +3392,6 @@
     /////////////////////
     case DCACHE_XTN_SYNC:		// waiting until write buffer empty
-                                        // The coherence request must be taken
-                                        // as there is a risk of dead-lock
+                                // The coherence request must be taken
+                                // as there is a risk of dead-lock
     {
         // external coherence request 
@@ -3401,5 +3413,6 @@
     case DCACHE_XTN_IC_INVAL_VA:	// Caution : the itlb miss requests must be taken 
     case DCACHE_XTN_IC_INVAL_PA:	// because the XTN_ICACHE_INVAL request to icache
-    case DCACHE_XTN_IT_INVAL:		// can generate an itlb miss...
+    case DCACHE_XTN_IT_INVAL:		// can generate an itlb miss,
+                                    // and because it can exist a simultaneous ITLB miss
     {
         // external coherence request
@@ -3434,5 +3447,5 @@
                                 // A cleanup request is generated for each valid line 
                                 // and we are blocked until the previous cleanup is completed
-				// Finally, both the itlb and dtlb are flushed
+				                // Finally, both the itlb and dtlb are flushed
                                 // (including global entries) 
     {