- Timestamp:
- Jan 15, 2013, 5:54:45 PM (12 years ago)
- Location:
- trunk/modules
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h
r150 r287 5 5 * 6 6 * SOCLIB_LGPL_HEADER_BEGIN 7 * 7 * 8 8 * This file is part of SoCLib, GNU LGPLv2.1. 9 * 9 * 10 10 * SoCLib is free software; you can redistribute it and/or modify it 11 11 * under the terms of the GNU Lesser General Public License as published 12 12 * by the Free Software Foundation; version 2.1 of the License. 13 * 13 * 14 14 * SoCLib is distributed in the hope that it will be useful, but 15 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 17 * Lesser General Public License for more details. 18 * 18 * 19 19 * You should have received a copy of the GNU Lesser General Public 20 20 * License along with SoCLib; if not, write to the Free Software 21 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 22 22 * 02110-1301 USA 23 * 23 * 24 24 * SOCLIB_LGPL_HEADER_END 25 * 26 * Maintainers: alexandre.joannou@lip6.fr 27 * 25 28 */ 26 29 … … 41 44 // - VCI plen == 8 bits 42 45 // - VCI srcid <= 14 bits 43 // - VCI trdid <= 8bits44 // - VCI pktid field not transmitted45 // - VCI rerror == 2 bits46 // - VCI trdid <= 4 bits 47 // - VCI pktid <= 4 bits 48 // - VCI rerror == 1 bit 46 49 //////////////////////////////////////////////////////////////////////// 47 50 … … 60 63 template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> 61 64 class VciVdspinInitiatorWrapper 62 65 : public soclib::caba::BaseModule 63 66 { 64 // Command FSM 67 // Command FSM 65 68 enum fsm_state_cmd{ 66 67 68 69 70 69 CMD_IDLE, 70 CMD_BROADCAST, 71 CMD_READ, 72 CMD_WRITE, 73 CMD_WDATA, 71 74 }; 72 75 73 76 // Response FSM 74 77 enum fsm_state_rsp{ 75 76 RSP_READ, 77 RSP_WRITE, 78 RSP_IDLE, 79 RSP_DSPIN_SINGLE_FLIT, 80 RSP_DSPIN_MULTI_FLIT, 78 81 }; 79 82 … … 83 86 public: 84 87 // ports 85 sc_core::sc_in<bool> 86 sc_core::sc_in<bool> 87 soclib::caba::DspinOutput<dspin_cmd_width> 88 soclib::caba::DspinInput<dspin_rsp_width> 89 soclib::caba::VciTarget<vci_param> 88 sc_core::sc_in<bool> p_clk; 89 sc_core::sc_in<bool> p_resetn; 90 soclib::caba::DspinOutput<dspin_cmd_width> p_dspin_out; 91 soclib::caba::DspinInput<dspin_rsp_width> p_dspin_in; 92 soclib::caba::VciTarget<vci_param> p_vci; 90 93 91 94 // constructor / destructor 92 VciVdspinInitiatorWrapper( sc_module_name name,93 size_tcmd_fifo_depth,94 size_t rsp_fifo_depth);95 VciVdspinInitiatorWrapper( sc_module_name name, 96 size_t cmd_fifo_depth, 97 size_t rsp_fifo_depth ); 95 98 private: 96 99 // internal registers 97 sc_core::sc_signal<int> 98 sc_core::sc_signal<int> 99 sc_core::sc_signal<sc_uint<dspin_rsp_width> >r_rsp_buf;100 sc_core::sc_signal<int> r_cmd_fsm; 101 sc_core::sc_signal<int> r_rsp_fsm; 102 sc_core::sc_signal<sc_uint<dspin_rsp_width> > r_rsp_buf; 100 103 101 104 // fifos cmd and rsp 102 soclib::caba::GenericFifo<sc_uint<dspin_cmd_width> > 103 soclib::caba::GenericFifo<sc_uint<dspin_rsp_width> > 105 soclib::caba::GenericFifo<sc_uint<dspin_cmd_width> > r_fifo_cmd; 106 soclib::caba::GenericFifo<sc_uint<dspin_rsp_width> > r_fifo_rsp; 104 107 105 108 // methods systemc … … 113 116 114 117 }} // end namespace 115 118 116 119 #endif // VCI_VDSPIN_INITIATOR_WRAPPER_H_ 117 120 -
trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp
r284 r287 23 23 * 24 24 * SOCLIB_LGPL_HEADER_END 25 * 26 * Maintainers: alexandre.joannou@lip6.fr 27 * 25 28 */ 26 29 … … 31 34 #define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width> 32 35 33 ////////////////////////////////////////////////////////// :////////////////////////////////34 tmpl(/**/)::VciVdspinInitiatorWrapper( sc_module_namename,35 size_tcmd_fifo_depth,36 size_t rsp_fifo_depth)37 :soclib::caba::BaseModule(name),38 39 40 41 42 43 44 45 r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth),46 r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth)36 ////////////////////////////////////////////////////////////////////////////////////////// 37 tmpl(/**/)::VciVdspinInitiatorWrapper( sc_module_name name, 38 size_t cmd_fifo_depth, 39 size_t rsp_fifo_depth ) 40 : soclib::caba::BaseModule(name), 41 p_clk("p_clk"), 42 p_resetn("p_resetn"), 43 p_dspin_out("p_dspin_out"), 44 p_dspin_in("p_dspin_in"), 45 p_vci("p_vci"), 46 r_cmd_fsm("r_cmd_fsm"), 47 r_rsp_fsm("r_rsp_fsm"), 48 r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), 49 r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) 47 50 { 48 51 SC_METHOD (transition); 49 52 dont_initialize(); 50 53 sensitive << p_clk.pos(); 54 51 55 SC_METHOD (genMoore); 52 56 dont_initialize(); … … 56 60 assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); 57 61 assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); 58 assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); 59 assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); 60 assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); 61 assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); 62 assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); 62 assert( (vci_param::B == 4 ) && "The VCI DATA filds must have 32 bits"); 63 assert( (vci_param::K == 8 ) && "The VCI PLEN field cannot have more than 8 bits"); 64 assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 14 bits"); 65 assert( (vci_param::T <= 4 ) && "The VCI TRDID field cannot have more than 4 bits"); 66 assert( (vci_param::P <= 4 ) && "The VCI PKTID field cannot have more than 4 bits"); 67 assert( (vci_param::E <= 2 ) && "The VCI RERROR field cannot have more than 2 bits"); 63 68 64 69 } // end constructor … … 68 73 { 69 74 sc_uint<dspin_cmd_width> cmd_fifo_data; 70 bool cmd_fifo_write;71 bool cmd_fifo_read;75 bool cmd_fifo_write; 76 bool cmd_fifo_read; 72 77 73 78 sc_uint<dspin_rsp_width> rsp_fifo_data; 74 bool rsp_fifo_write;75 bool rsp_fifo_read;79 bool rsp_fifo_write; 80 bool rsp_fifo_read; 76 81 77 82 if (p_resetn == false) 78 83 { 79 84 r_fifo_cmd.init(); 80 85 r_fifo_rsp.init(); … … 123 128 else address = address << (39 - vci_param::N); 124 129 125 if ( is_broadcast ) 130 if ( is_broadcast ) // VCI broacast command 126 131 { 127 132 r_cmd_fsm = CMD_BROADCAST; … … 131 136 0x0000000001LL; 132 137 } 133 else if (is_read ) 138 else if (is_read ) // VCI READ command 134 139 { 135 140 r_cmd_fsm = CMD_READ; 136 141 cmd_fifo_data = address & 0x7FFFFFFFFELL; 137 142 } 138 else 143 else // VCI WRITE command 139 144 { 140 145 r_cmd_fsm = CMD_WRITE; … … 144 149 break; 145 150 } 146 case CMD_BROADCAST: // write second DSPIN flit in case of broadcast151 case CMD_BROADCAST: // write second DSPIN flit in case of broadcast 147 152 { 148 153 if( p_vci.cmdval && r_fifo_cmd.wok() ) … … 158 163 break; 159 164 } 160 case CMD_READ: // write second DSPIN flit in case of read/write165 case CMD_READ: // write second DSPIN flit in case of read/write 161 166 case CMD_WRITE: 162 167 { … … 179 184 if ( p_vci.cons.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000200000LL ; 180 185 181 if( r_cmd_fsm == CMD_READ ) 186 if( r_cmd_fsm == CMD_READ ) // read command 182 187 { 183 188 r_cmd_fsm = CMD_IDLE; 184 189 cmd_fifo_data = cmd_fifo_data | 0x8000000000LL ; 185 190 } 186 else // write command191 else // write command 187 192 { 188 193 r_cmd_fsm = CMD_WDATA; … … 221 226 // The FIFO output is analysed and translated to a VCI packet 222 227 ////////////////////////////////////////////////////////////// 223 // - A N+1 flits DSPIN re ad response packet is translated228 // - A N+1 flits DSPIN response packet is translated 224 229 // to a N flits VCI response. 225 // - A single flit DSPIN writeresponse packet is translated226 // to a single flit VCI response .230 // - A single flit DSPIN response packet is translated 231 // to a single flit VCI response with RDATA = 0. 227 232 // A valid DSPIN flit in the fifo_rsp is always consumed 228 233 // in the CMD_IDLE state, but no VCI flit is transmitted. 229 // The VCI flits are sent in the RSP_READ & RSP_WRITE states. 234 // The VCI flits are sent in the RSP_DSPIN_SINGLE_FLIT & 235 // RSP_DSPIN_MULTI_FLIT states. 230 236 ////////////////////////////////////////////////////////////// 231 237 … … 235 241 236 242 // r_rsp_fsm, rsp_fifo_read 237 rsp_fifo_read = false; // default value 238 239 switch(r_rsp_fsm) { 243 rsp_fifo_read = false; // default value 244 245 switch(r_rsp_fsm) 246 { 240 247 case RSP_IDLE: 241 {242 if( r_fifo_rsp.rok() )243 {244 rsp_fifo_read = true;245 r_rsp_buf = r_fifo_rsp.read();246 if ( (r_fifo_rsp.read() & 0x000020000LL) == 0 ) r_rsp_fsm = RSP_READ;247 else r_rsp_fsm = RSP_WRITE;248 }249 break;250 }251 case RSP_READ:252 248 { 253 if( r_fifo_rsp.rok() && p_vci.rspack.read() ) 254 { 255 rsp_fifo_read = true; 256 if ( (r_fifo_rsp.read() & 0x100000000LL) ) r_rsp_fsm = RSP_IDLE; 257 } 258 break; 259 } 260 case RSP_WRITE: 261 { 262 if ( p_vci.rspack.read() ) r_rsp_fsm = RSP_IDLE; 263 } 249 if( r_fifo_rsp.rok() ) 250 { 251 rsp_fifo_read = true; 252 r_rsp_buf = r_fifo_rsp.read(); 253 if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL ) 254 r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT; 255 else 256 r_rsp_fsm = RSP_DSPIN_MULTI_FLIT; 257 } 258 break; 259 } 260 case RSP_DSPIN_SINGLE_FLIT: 261 { 262 if ( p_vci.rspack.read() ) 263 r_rsp_fsm = RSP_IDLE; 264 break; 265 } 266 case RSP_DSPIN_MULTI_FLIT: 267 { 268 if( r_fifo_rsp.rok() && p_vci.rspack.read() ) 269 { 270 rsp_fifo_read = true; 271 if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL ) 272 r_rsp_fsm = RSP_IDLE; 273 } 274 break; 275 } 264 276 } // end switch r_rsp_fsm 265 277 … … 275 287 { 276 288 // VCI CMD interface 277 278 279 280 289 if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) ) 290 { 291 p_vci.cmdack = false; 292 } 281 293 else 282 283 284 294 { 295 p_vci.cmdack = r_fifo_cmd.wok(); 296 } 285 297 286 298 // VCI RSP interface 287 299 if ( r_rsp_fsm.read() == RSP_IDLE ) 288 289 290 291 else if ( r_rsp_fsm.read() == RSP_WRITE)292 293 294 295 296 297 298 299 300 301 else if ( r_rsp_fsm.read() == RSP_READ)302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 300 { 301 p_vci.rspval = false; 302 } 303 else if ( r_rsp_fsm.read() == RSP_DSPIN_SINGLE_FLIT ) 304 { 305 p_vci.rspval = true; 306 p_vci.rdata = 0; 307 p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18); 308 p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x000000F00LL) >> 8); 309 p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read() & 0x00000F000LL) >> 12); 310 p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000LL) >> 16); 311 p_vci.reop = true; 312 } 313 else if ( r_rsp_fsm.read() == RSP_DSPIN_MULTI_FLIT ) 314 { 315 p_vci.rspval = r_fifo_rsp.rok(); 316 p_vci.rdata = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFFLL); 317 p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18); 318 p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x000000F00LL) >> 8); 319 p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read() & 0x00000F000LL) >> 12); 320 p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000LL) >> 16); 321 p_vci.reop = ((r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL); 322 } 323 324 // DSPIN_OUT interface 325 p_dspin_out.write = r_fifo_cmd.rok(); 326 p_dspin_out.data = r_fifo_cmd.read(); 327 328 // DSPIN_IN interface 329 p_dspin_in.read = r_fifo_rsp.wok(); 318 330 319 331 }; // end genMoore … … 330 342 }; 331 343 const char* rsp_str[] = { 332 "RSP_IDLE ",333 "RSP_ READ",334 "RSP_ WRITE",344 "RSP_IDLE ", 345 "RSP_DSPIN_SINGLE_FLIT", 346 "RSP_DSPIN_MULTI_FLIT ", 335 347 }; 336 348 -
trunk/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h
r185 r287 5 5 * 6 6 * SOCLIB_LGPL_HEADER_BEGIN 7 * 7 * 8 8 * This file is part of SoCLib, GNU LGPLv2.1. 9 * 9 * 10 10 * SoCLib is free software; you can redistribute it and/or modify it 11 11 * under the terms of the GNU Lesser General Public License as published 12 12 * by the Free Software Foundation; version 2.1 of the License. 13 * 13 * 14 14 * SoCLib is distributed in the hope that it will be useful, but 15 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 17 * Lesser General Public License for more details. 18 * 18 * 19 19 * You should have received a copy of the GNU Lesser General Public 20 20 * License along with SoCLib; if not, write to the Free Software 21 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 22 22 * 02110-1301 USA 23 * 23 * 24 24 * SOCLIB_LGPL_HEADER_END 25 * 26 * Maintainers: alexandre.joannou@lip6.fr 27 * 25 28 */ 26 29 … … 39 42 // - VCI address width <= 40 bits 40 43 // - VCI data == 32 bits 41 // - VCI plen 42 // - VCI srcid 43 // - VCI trdid <= 8bits44 // - VCI pktid field not transmitted45 // - VCI rerror == 2 bits44 // - VCI plen == 8 bits 45 // - VCI srcid <= 14 bits 46 // - VCI trdid <= 4 bits 47 // - VCI pktid <= 4 bits 48 // - VCI rerror == 1 bit 46 49 //////////////////////////////////////////////////////////////////////// 47 50 … … 62 65 template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> 63 66 class VciVdspinTargetWrapper 64 67 : public soclib::caba::BaseModule 65 68 { 66 69 67 // Command FSM 70 // Command FSM 68 71 enum fsm_state_cmd{ 69 72 CMD_IDLE, … … 77 80 enum fsm_state_rsp{ 78 81 RSP_IDLE, 79 RSP_ READ,80 RSP_ WRITE,82 RSP_DSPIN_SINGLE_FLIT, 83 RSP_DSPIN_MULTI_FLIT, 81 84 }; 82 85 … … 86 89 public: 87 90 // ports 88 sc_core::sc_in<bool> 89 sc_core::sc_in<bool> 90 soclib::caba::DspinOutput<dspin_rsp_width> 91 soclib::caba::DspinInput<dspin_cmd_width> 92 soclib::caba::VciInitiator<vci_param> 91 sc_core::sc_in<bool> p_clk; 92 sc_core::sc_in<bool> p_resetn; 93 soclib::caba::DspinOutput<dspin_rsp_width> p_dspin_out; 94 soclib::caba::DspinInput<dspin_cmd_width> p_dspin_in; 95 soclib::caba::VciInitiator<vci_param> p_vci; 93 96 94 97 // constructor / destructor 95 VciVdspinTargetWrapper( sc_module_name name,96 size_tcmd_fifo_depth,97 size_t rsp_fifo_depth);98 VciVdspinTargetWrapper( sc_module_name name, 99 size_t cmd_fifo_depth, 100 size_t rsp_fifo_depth ); 98 101 private: 99 102 // internal registers 100 sc_core::sc_signal<int> 101 sc_core::sc_signal<sc_uint<dspin_cmd_width> >r_cmd_buf0;102 sc_core::sc_signal<sc_uint<dspin_cmd_width> >r_cmd_buf1;103 sc_core::sc_signal<int> 104 sc_core::sc_signal<size_t> 103 sc_core::sc_signal<int> r_cmd_fsm; 104 sc_core::sc_signal<sc_uint<dspin_cmd_width> > r_cmd_buf0; 105 sc_core::sc_signal<sc_uint<dspin_cmd_width> > r_cmd_buf1; 106 sc_core::sc_signal<int> r_rsp_fsm; 107 sc_core::sc_signal<size_t> r_flit_count; 105 108 106 109 // fifos cmd and rsp 107 soclib::caba::GenericFifo<sc_uint<dspin_cmd_width> > 108 soclib::caba::GenericFifo<sc_uint<dspin_rsp_width> > 110 soclib::caba::GenericFifo<sc_uint<dspin_cmd_width> > r_fifo_cmd; 111 soclib::caba::GenericFifo<sc_uint<dspin_rsp_width> > r_fifo_rsp; 109 112 110 113 // methods systemc … … 118 121 119 122 }} // end namespace 120 123 121 124 #endif // VCI_VDSPIN_TARGET_WRAPPER_H_ 122 125 -
trunk/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp
r284 r287 23 23 * 24 24 * SOCLIB_LGPL_HEADER_END 25 * 26 * Maintainers: alexandre.joannou@lip6.fr 27 * 25 28 */ 26 29 … … 33 36 #define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width> 34 37 35 ////////////////////////////////////////////////////////// :////////////////////////////////36 tmpl(/**/)::VciVdspinTargetWrapper( sc_module_namename,37 size_tcmd_fifo_depth,38 size_t rsp_fifo_depth)39 :soclib::caba::BaseModule(name),40 41 42 43 44 45 46 47 48 49 38 ////////////////////////////////////////////////////////////////////////////////////////// 39 tmpl(/**/)::VciVdspinTargetWrapper( sc_module_name name, 40 size_t cmd_fifo_depth, 41 size_t rsp_fifo_depth ) 42 : soclib::caba::BaseModule(name), 43 p_clk("p_clk"), 44 p_resetn("p_resetn"), 45 p_dspin_out("p_dspin_out"), 46 p_dspin_in("p_dspin_in"), 47 p_vci("p_vci"), 48 r_cmd_fsm("r_cmd_fsm"), 49 r_rsp_fsm("r_rsp_fsm"), 50 r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), 51 r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) 52 { 50 53 SC_METHOD (transition); 51 54 dont_initialize(); 52 55 sensitive << p_clk.pos(); 56 53 57 SC_METHOD (genMoore); 54 58 dont_initialize(); 55 59 sensitive << p_clk.neg(); 56 60 57 assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); 58 assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); 59 assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); 60 assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); 61 assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); 62 assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); 63 assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); 64 assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); 65 66 } // end constructor 61 assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); 62 assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); 63 assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); 64 assert( (vci_param::B == 4 ) && "The VCI DATA filds must have 32 bits"); 65 assert( (vci_param::K == 8 ) && "The VCI PLEN field cannot have more than 8 bits"); 66 assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 14 bits"); 67 assert( (vci_param::T <= 4 ) && "The VCI TRDID field cannot have more than 4 bits"); 68 assert( (vci_param::P <= 4 ) && "The VCI PKTID field cannot have more than 4 bits"); 69 assert( (vci_param::E <= 2 ) && "The VCI RERROR field cannot have more than 2 bits"); 70 71 } // end constructor 67 72 68 73 ///////////////////////// 69 74 tmpl(void)::transition() 70 75 { 71 sc_uint<dspin_cmd_width> 72 bool cmd_fifo_write;73 bool cmd_fifo_read;74 75 sc_uint<dspin_rsp_width> 76 bool rsp_fifo_write;77 bool rsp_fifo_read;76 sc_uint<dspin_cmd_width> cmd_fifo_data; 77 bool cmd_fifo_write; 78 bool cmd_fifo_read; 79 80 sc_uint<dspin_rsp_width> rsp_fifo_data; 81 bool rsp_fifo_write; 82 bool rsp_fifo_read; 78 83 79 84 if (p_resetn == false) 80 85 { 81 86 r_fifo_cmd.init(); 82 87 r_fifo_rsp.init(); … … 91 96 // and the DSPIN packet is stored in the fifo_rsp 92 97 ///////////////////////////////////////////////////////////// 93 // - A single flit VCI write response packet is translated94 // to a single flit DSPIN response.95 // - A N flits VCI read response packet is translated96 // to a N+1 flits DSPIN response98 // - A single flit VCI response packet with a 0 RDATA value 99 // is translated to a single flit DSPIN response. 100 // - All other VCI responses are translated to a multi-flit 101 // DSPIN response. 97 102 // In the RSP_IDLE state, the first DSPIN flit is written 98 103 // in fifo_rsp , but no VCI flit is consumed. The VCI flits 99 // are consumed in the RSP_READ or RSP_WRITE states. 104 // are consumed in the RSP_DSPIN_SINGLE_FLIT, or the 105 // SP_DSPIN_MULTI_FLIT states. 100 106 ////////////////////////////////////////////////////////////// 101 107 … … 104 110 105 111 // r_rsp_fsm, rsp_fifo_write and rsp_fifo_data 106 rsp_fifo_write = false; // default value 107 108 switch(r_rsp_fsm) { 112 rsp_fifo_write = false; // default value 113 114 switch(r_rsp_fsm) 115 { 109 116 case RSP_IDLE: // write first DSPIN flit into rsp_fifo 110 { 111 if( p_vci.rspval && r_fifo_rsp.wok() ) 117 { 118 if( p_vci.rspval.read() && r_fifo_rsp.wok() ) 119 { 120 bool is_single_flit = ( p_vci.reop.read() && ( p_vci.rdata.read() == 0) ); 121 122 rsp_fifo_write = true; 123 rsp_fifo_data = (((sc_uint<dspin_rsp_width>)p_vci.rsrcid.read()) << 18) | 124 (((sc_uint<dspin_rsp_width>)p_vci.rerror.read()) << 16) | 125 (((sc_uint<dspin_rsp_width>)p_vci.rtrdid.read()) << 12) | 126 (((sc_uint<dspin_rsp_width>)p_vci.rpktid.read()) << 8); 127 if ( is_single_flit ) 112 128 { 113 bool is_read = ( (p_vci.rerror.read() & 0x2) == 0); 114 115 rsp_fifo_write = true; 116 rsp_fifo_data = (((sc_uint<dspin_rsp_width>)p_vci.rsrcid.read()) << 18) | 117 (((sc_uint<dspin_rsp_width>)p_vci.rerror.read()) << 16) | 118 (((sc_uint<dspin_rsp_width>)p_vci.rtrdid.read()) << 12) | 119 (((sc_uint<dspin_rsp_width>)p_vci.rpktid.read()) << 8); 120 if ( is_read ) 121 { 122 r_rsp_fsm = RSP_READ; 123 } 124 else 125 { 126 rsp_fifo_data = rsp_fifo_data | 0x100000000LL; 127 r_rsp_fsm = RSP_WRITE; 128 } 129 rsp_fifo_data = rsp_fifo_data | 0x100000000LL; // EOP = 1 130 rsp_fifo_data = rsp_fifo_data & 0x1FFFFFFFELL; // BC = 0 131 r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT; 129 132 } 130 break; 131 } 132 case RSP_READ: // write DSPIN data flit in case of read 133 { 134 if( p_vci.rspval && r_fifo_rsp.wok() ) 133 else 135 134 { 136 rsp_fifo_write = true; 137 rsp_fifo_data = ((sc_uint<dspin_rsp_width>)p_vci.rdata.read()); 138 if ( p_vci.reop ) 139 { 140 rsp_fifo_data = rsp_fifo_data | 0x100000000LL; 141 r_rsp_fsm = RSP_IDLE; 142 } 135 rsp_fifo_data = rsp_fifo_data & 0x0FFFFFFFFLL; // EOP = 0 136 rsp_fifo_data = rsp_fifo_data & 0x1FFFFFFFELL; // BC = 0 137 r_rsp_fsm = RSP_DSPIN_MULTI_FLIT; 143 138 } 144 break; 145 } 146 case RSP_WRITE: 147 { 148 rsp_fifo_write = false; 149 if ( r_fifo_rsp.wok() ) r_rsp_fsm = RSP_IDLE; 150 break; 151 } 139 } 140 break; 141 } 142 case RSP_DSPIN_SINGLE_FLIT: 143 { 144 rsp_fifo_write = false; 145 if ( r_fifo_rsp.wok() ) 146 r_rsp_fsm = RSP_IDLE; 147 break; 148 } 149 case RSP_DSPIN_MULTI_FLIT: // write DSPIN data flit 150 { 151 if( p_vci.rspval && r_fifo_rsp.wok() ) 152 { 153 rsp_fifo_write = true; 154 rsp_fifo_data = ((sc_uint<dspin_rsp_width>)p_vci.rdata.read()); 155 if ( p_vci.reop ) 156 { 157 rsp_fifo_data = rsp_fifo_data | 0x100000000LL; // EOP = 1 158 r_rsp_fsm = RSP_IDLE; 159 } 160 } 161 break; 162 } 152 163 } // end switch r_cmd_fsm 153 164 … … 157 168 if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } 158 169 159 170 ////////////////////////////////////////////////////////////// 160 171 // DSPIN command packet to VCI command packet 161 // The DSPIN packet is stored in the fifo_ rsp172 // The DSPIN packet is stored in the fifo_cmd 162 173 // The FIFO output is analysed and translated to a VCI packet 163 164 165 166 167 168 169 170 171 172 173 174 174 ////////////////////////////////////////////////////////////// 175 // - A 2 flits DSPIN broadcast command is translated 176 // to a 1 flit VCI broadcast command. 177 // - A 2 flits DSPIN read command is translated 178 // to a 1 flit VCI read command. 179 // - A N+2 flits DSPIN write command is translated 180 // to a N flits VCI write command. 181 // The VCI flits are sent in the CMD_READ, CMD_WDATA 182 // & CMD_BROADCAST states. 183 // The r_cmd_buf0 et r_cmd_buf1 buffers are used to store 184 // the two first DSPIN flits (in case of write). 185 ////////////////////////////////////////////////////////////// 175 186 176 187 // cmd_fifo_write, cmd_fifo_data … … 179 190 180 191 // r_cmd_fsm, cmd_fifo_read 181 cmd_fifo_read = false; // default value 182 183 switch(r_cmd_fsm) { 192 cmd_fifo_read = false; // default value 193 194 switch(r_cmd_fsm) 195 { 184 196 case CMD_IDLE: 185 { 186 if( r_fifo_cmd.rok() ) 187 { 188 bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1); 189 190 cmd_fifo_read = true; 191 r_cmd_buf0 = r_fifo_cmd.read(); // save address 192 if ( is_broadcast ) r_cmd_fsm = CMD_BROADCAST; 193 else r_cmd_fsm = CMD_RW; 194 } 195 break; 196 } 197 { 198 if( r_fifo_cmd.rok() ) 199 { 200 bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1); 201 202 cmd_fifo_read = true; 203 r_cmd_buf0 = r_fifo_cmd.read(); // save address 204 205 if ( is_broadcast ) 206 r_cmd_fsm = CMD_BROADCAST; 207 else 208 r_cmd_fsm = CMD_RW; 209 } 210 break; 211 } 197 212 case CMD_BROADCAST: 198 213 { 199 if( r_fifo_cmd.rok() && p_vci.cmdack ) 200 { 201 cmd_fifo_read = true; 214 if( r_fifo_cmd.rok() && p_vci.cmdack ) 215 { 216 cmd_fifo_read = true; 217 r_cmd_fsm = CMD_IDLE; 218 } 219 break; 220 } 221 case CMD_RW: 222 { 223 if( r_fifo_cmd.rok() ) 224 { 225 cmd_fifo_read = true; 226 r_cmd_buf1 = r_fifo_cmd.read(); // save command parameters 227 // read command if EOP 228 if ( (r_fifo_cmd.read() & 0x8000000000LL) ) 229 r_cmd_fsm = CMD_READ; 230 else 231 r_cmd_fsm = CMD_WDATA; 232 r_flit_count = 0; 233 } 234 break; 235 } 236 case CMD_READ: 237 { 238 if ( p_vci.cmdack.read() ) 239 r_cmd_fsm = CMD_IDLE; 240 break; 241 } 242 case CMD_WDATA: 243 { 244 if( r_fifo_cmd.rok() && p_vci.cmdack.read() ) 245 { 246 if ( (r_cmd_buf1.read() & 0x0000200000LL) == 0 ) 247 r_flit_count = r_flit_count + 1; 248 cmd_fifo_read = true; 249 if ( (r_fifo_cmd.read() & 0x8000000000LL) ) 202 250 r_cmd_fsm = CMD_IDLE; 203 } 204 break; 205 } 206 case CMD_RW: 207 { 208 if( r_fifo_cmd.rok() ) 209 { 210 cmd_fifo_read = true; 211 r_cmd_buf1 = r_fifo_cmd.read(); // save command parameters 212 // read command if EOP 213 if ( (r_fifo_cmd.read() & 0x8000000000LL) ) r_cmd_fsm = CMD_READ; 214 else r_cmd_fsm = CMD_WDATA; 215 r_flit_count = 0; 216 } 217 break; 218 } 219 case CMD_READ: 220 { 221 if ( p_vci.cmdack.read() ) r_cmd_fsm = CMD_IDLE; 222 break; 223 } 224 case CMD_WDATA: 225 { 226 if( r_fifo_cmd.rok() && p_vci.cmdack.read() ) 227 { 228 if ( (r_cmd_buf1.read() & 0x0000200000LL) == 0 ) r_flit_count = r_flit_count + 1; 229 cmd_fifo_read = true; 230 if ( (r_fifo_cmd.read() & 0x8000000000LL) ) r_cmd_fsm = CMD_IDLE; 231 } 232 break; 233 } 251 } 252 break; 253 } 234 254 } // end switch r_cmd_fsm 235 255 … … 245 265 { 246 266 // VCI RSP interface 247 if ( r_rsp_fsm.read() == RSP_IDLE )p_vci.rspack = false;248 else 267 if ( r_rsp_fsm.read() == RSP_IDLE ) p_vci.rspack = false; 268 else p_vci.rspack = r_fifo_rsp.wok(); 249 269 250 270 // VCI CMD interface 251 271 if ( (r_cmd_fsm.read() == CMD_IDLE) || (r_cmd_fsm.read() == CMD_RW) ) 272 { 273 p_vci.cmdval = false; 274 } 275 else if ( r_cmd_fsm.read() == CMD_BROADCAST ) // VCI CMD broadcast 276 { 277 if ( r_fifo_cmd.rok() ) 278 { 279 sc_uint<dspin_cmd_width> minmax = r_cmd_buf0.read() & 0x7FFFF80000LL; 280 if ( vci_param::N == 40 ) minmax = (minmax << 1); 281 else minmax = (minmax >> (39 - vci_param::N) ); 282 p_vci.cmdval = true; 283 p_vci.address = (sc_uint<vci_param::N>)minmax | 0x3; 284 p_vci.cmd = vci_param::CMD_WRITE; 285 p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); 286 p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); 287 p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf0.read() & 0x000007FFE0LL) >> 5); 288 p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf0.read() & 0x000000001ELL) >> 1); 289 p_vci.pktid = 0; 290 p_vci.plen = vci_param::B; 291 p_vci.contig = true; 292 p_vci.cons = false; 293 p_vci.eop = true; 294 } 295 else 252 296 { 253 297 p_vci.cmdval = false; 254 298 } 255 else if ( r_cmd_fsm.read() == CMD_BROADCAST ) // VCI CMD broadcast 256 { 257 if ( r_fifo_cmd.rok() ) 258 { 259 sc_uint<dspin_cmd_width> minmax = r_cmd_buf0.read() & 0x7FFFF80000LL; 260 if ( vci_param::N == 40 ) minmax = (minmax << 1); 261 else minmax = (minmax >> (39 - vci_param::N) ); 262 p_vci.cmdval = true; 263 p_vci.address = (sc_uint<vci_param::N>)minmax | 0x3; 264 p_vci.cmd = vci_param::CMD_WRITE; 265 p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); 266 p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); 267 p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf0.read() & 0x000007FFE0LL) >> 5); 268 p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf0.read() & 0x000000001ELL) >> 1); 269 p_vci.pktid = 0; 270 p_vci.plen = vci_param::B; 271 p_vci.contig = true; 272 p_vci.cons = false; 273 p_vci.eop = true; 274 } 275 else 276 { 277 p_vci.cmdval = false; 278 } 279 } 280 else if ( r_cmd_fsm.read() == CMD_READ ) // VCI CMD read 299 } 300 else if ( r_cmd_fsm.read() == CMD_READ ) // VCI CMD read 301 { 302 sc_uint<vci_param::N> address; 303 if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1); 304 else address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); 305 p_vci.cmdval = true; 306 p_vci.address = address; 307 p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23); 308 p_vci.wdata = 0; 309 p_vci.be = (sc_uint<vci_param::B>)((r_cmd_buf1.read() & 0x000000001ELL) >> 1); 310 p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25); 311 p_vci.pktid = (sc_uint<vci_param::P>)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5); 312 p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9); 313 p_vci.plen = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13); 314 p_vci.contig = ((r_cmd_buf1.read() & 0x0000400000LL) != 0); 315 p_vci.cons = ((r_cmd_buf1.read() & 0x0000200000LL) != 0); 316 p_vci.eop = true; 317 } 318 else if ( r_cmd_fsm.read() == CMD_WDATA ) // VCI write command 319 { 320 if ( r_fifo_cmd.rok() ) 281 321 { 282 322 sc_uint<vci_param::N> address; … … 284 324 else address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); 285 325 p_vci.cmdval = true; 286 p_vci.address = address ;287 p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23);288 p_vci.wdata = 0;289 p_vci.be = (sc_uint<vci_param::B>)((r_ cmd_buf1.read() & 0x000000001ELL) >> 1);290 p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25);291 p_vci.pktid = (sc_uint<vci_param::P>)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5);292 p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9);293 p_vci.plen = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13);326 p_vci.address = address + (r_flit_count.read()*vci_param::B); 327 p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23); 328 p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); 329 p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); 330 p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25); 331 p_vci.pktid = (sc_uint<vci_param::P>)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5); 332 p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9); 333 p_vci.plen = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13); 294 334 p_vci.contig = ((r_cmd_buf1.read() & 0x0000400000LL) != 0); 295 335 p_vci.cons = ((r_cmd_buf1.read() & 0x0000200000LL) != 0); 296 p_vci.eop = true; 336 p_vci.eop = ((r_fifo_cmd.read() & 0x8000000000LL) == 0x8000000000LL); 337 } 338 else 339 { 340 p_vci.cmdval = false; 341 } 297 342 } 298 else if ( r_cmd_fsm.read() == CMD_WDATA ) // VCI write command299 {300 if ( r_fifo_cmd.rok() )301 {302 sc_uint<vci_param::N> address;303 if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1);304 else address = (r_cmd_buf0.read() >> (39 - vci_param::N) );305 p_vci.cmdval = true;306 p_vci.address = address + (r_flit_count.read()*vci_param::B);307 p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23);308 p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL);309 p_vci.be = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32);310 p_vci.srcid = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25);311 p_vci.pktid = (sc_uint<vci_param::P>)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5);312 p_vci.trdid = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9);313 p_vci.plen = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13);314 p_vci.contig = ((r_cmd_buf1.read() & 0x0000400000LL) != 0);315 p_vci.cons = ((r_cmd_buf1.read() & 0x0000200000LL) != 0);316 p_vci.eop = ((r_fifo_cmd.read() & 0x8000000000LL) == 0x8000000000LL);317 }318 else319 {320 p_vci.cmdval = false;321 }322 }323 343 324 344 // DSPIN_OUT interface … … 342 362 }; 343 363 const char* rsp_str[] = { 344 "RSP_IDLE ",345 "RSP_ READ",346 "RSP_ WRITE",364 "RSP_IDLE ", 365 "RSP_DSPIN_SINGLE_FLIT", 366 "RSP_DSPIN_MULTI_FLIT ", 347 367 }; 348 368 std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()]
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