Index: trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp
===================================================================
--- trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp	(revision 284)
+++ trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp	(revision 287)
@@ -23,4 +23,7 @@
   *
   * SOCLIB_LGPL_HEADER_END
+  *
+  * Maintainers: alexandre.joannou@lip6.fr
+  *
   */
 
@@ -31,22 +34,23 @@
 #define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
 
-//////////////////////////////////////////////////////////:////////////////////////////////
-tmpl(/**/)::VciVdspinInitiatorWrapper(sc_module_name             name,
-                      size_t                cmd_fifo_depth,
-                      size_t                rsp_fifo_depth)
-           : soclib::caba::BaseModule(name),
-                 p_clk("p_clk"),
-                 p_resetn("p_resetn"),
-                 p_dspin_out("p_dspin_out"),
-                 p_dspin_in("p_dspin_in"),
-                 p_vci("p_vci"),
-                 r_cmd_fsm("r_cmd_fsm"),
-                 r_rsp_fsm("r_rsp_fsm"),
-             r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth),
-             r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth)
+//////////////////////////////////////////////////////////////////////////////////////////
+tmpl(/**/)::VciVdspinInitiatorWrapper(  sc_module_name  name,
+                                        size_t          cmd_fifo_depth,
+                                        size_t          rsp_fifo_depth  )
+            :   soclib::caba::BaseModule(name),
+                p_clk("p_clk"),
+                p_resetn("p_resetn"),
+                p_dspin_out("p_dspin_out"),
+                p_dspin_in("p_dspin_in"),
+                p_vci("p_vci"),
+                r_cmd_fsm("r_cmd_fsm"),
+                r_rsp_fsm("r_rsp_fsm"),
+                r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth),
+                r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth)
 {
     SC_METHOD (transition);
     dont_initialize();
     sensitive << p_clk.pos();
+
     SC_METHOD (genMoore);
     dont_initialize();
@@ -56,9 +60,10 @@
     assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits");
     assert( (vci_param::N    <= 40) && "The VCI ADDRESS field cannot have more than 40 bits");
-    assert( (vci_param::B    == 4) && "The VCI DATA filds must have 32 bits");
-    assert( (vci_param::K    == 8) && "The VCI PLEN field cannot have more than 8 bits");
-    assert( (vci_param::S    <= 14) && "The VCI SRCID field cannot have more than 8 bits");
-    assert( (vci_param::T    <= 8) && "The VCI TRDID field cannot have more than 8 bits");
-    assert( (vci_param::E    == 2) && "The VCI RERROR field cannot have more than 2 bits");
+    assert( (vci_param::B    == 4 ) && "The VCI DATA filds must have 32 bits");
+    assert( (vci_param::K    == 8 ) && "The VCI PLEN field cannot have more than 8 bits");
+    assert( (vci_param::S    <= 14) && "The VCI SRCID field cannot have more than 14 bits");
+    assert( (vci_param::T    <= 4 ) && "The VCI TRDID field cannot have more than 4 bits");
+    assert( (vci_param::P    <= 4 ) && "The VCI PKTID field cannot have more than 4 bits");
+    assert( (vci_param::E    <= 2 ) && "The VCI RERROR field cannot have more than 2 bits");
 
 } //  end constructor
@@ -68,13 +73,13 @@
 {
     sc_uint<dspin_cmd_width>    cmd_fifo_data;
-    bool                cmd_fifo_write;
-    bool                cmd_fifo_read;
+    bool                        cmd_fifo_write;
+    bool                        cmd_fifo_read;
 
     sc_uint<dspin_rsp_width>    rsp_fifo_data;
-    bool                rsp_fifo_write;
-    bool                rsp_fifo_read;
+    bool                        rsp_fifo_write;
+    bool                        rsp_fifo_read;
 
     if (p_resetn == false)
-        {
+    {
         r_fifo_cmd.init();
         r_fifo_rsp.init();
@@ -123,5 +128,5 @@
                     else                      address = address << (39 - vci_param::N);
 
-                    if ( is_broadcast )    // VCI broacast command
+                    if ( is_broadcast ) // VCI broacast command
                     {
                         r_cmd_fsm     = CMD_BROADCAST;
@@ -131,10 +136,10 @@
                                                         0x0000000001LL;
                     }
-                    else if (is_read )            // VCI READ  command
+                    else if (is_read )  // VCI READ  command
                     {
                         r_cmd_fsm     = CMD_READ;
                         cmd_fifo_data = address & 0x7FFFFFFFFELL;
                     }
-                    else                 // VCI WRITE command
+                    else                // VCI WRITE command
                     {
                         r_cmd_fsm     = CMD_WRITE;
@@ -144,5 +149,5 @@
          break;
         }
-        case CMD_BROADCAST:        // write second DSPIN flit in case of broadcast
+        case CMD_BROADCAST:             // write second DSPIN flit in case of broadcast
             {
                 if( p_vci.cmdval && r_fifo_cmd.wok() )
@@ -158,5 +163,5 @@
                 break;
             }
-            case CMD_READ:    // write second DSPIN flit in case of read/write
+            case CMD_READ:              // write second DSPIN flit in case of read/write
             case CMD_WRITE:
             {
@@ -179,10 +184,10 @@
                     if ( p_vci.cons.read()   ) cmd_fifo_data = cmd_fifo_data | 0x0000200000LL ;
 
-                    if( r_cmd_fsm == CMD_READ )  // read command
+                    if( r_cmd_fsm == CMD_READ ) // read command
                     {
                         r_cmd_fsm = CMD_IDLE;
                         cmd_fifo_data = cmd_fifo_data    | 0x8000000000LL ;
                     }
-                    else            // write command
+                    else                        // write command
                     {
                         r_cmd_fsm = CMD_WDATA;
@@ -221,11 +226,12 @@
     // The FIFO output is analysed and translated to a VCI packet
     //////////////////////////////////////////////////////////////
-    // - A N+1 flits DSPIN read response packet is translated
+    // - A N+1 flits DSPIN response packet is translated
     //   to a N flits VCI response.
-    // - A single flit DSPIN write response packet is translated
-    //   to a single flit VCI response.
+    // - A single flit DSPIN response packet is translated
+    //   to a single flit VCI response with RDATA = 0.
     // A valid DSPIN flit in the fifo_rsp is always consumed
     // in the CMD_IDLE state, but no VCI flit is transmitted.
-    // The VCI flits are sent in the RSP_READ & RSP_WRITE states.
+    // The VCI flits are sent in the RSP_DSPIN_SINGLE_FLIT &
+    // RSP_DSPIN_MULTI_FLIT states.
     //////////////////////////////////////////////////////////////
 
@@ -235,31 +241,37 @@
 
     // r_rsp_fsm, rsp_fifo_read
-        rsp_fifo_read = false;        // default value
-
-    switch(r_rsp_fsm) {
+    rsp_fifo_read = false;        // default value
+
+    switch(r_rsp_fsm)
+    {
         case RSP_IDLE:
-            {
-        if( r_fifo_rsp.rok() )
-                {
-            rsp_fifo_read = true;
-                    r_rsp_buf = r_fifo_rsp.read();
-                    if ( (r_fifo_rsp.read() & 0x000020000LL) == 0 )  r_rsp_fsm = RSP_READ;
-                    else                              r_rsp_fsm = RSP_WRITE;
-        }
-        break;
-            }
-        case RSP_READ:
         {
-        if( r_fifo_rsp.rok() && p_vci.rspack.read() )
-                {
-            rsp_fifo_read = true;
-                    if ( (r_fifo_rsp.read() & 0x100000000LL) ) r_rsp_fsm = RSP_IDLE;
-        }
-        break;
-            }
-            case RSP_WRITE:
-            {
-                if ( p_vci.rspack.read() ) r_rsp_fsm = RSP_IDLE;
-            }
+            if( r_fifo_rsp.rok() )
+            {
+                rsp_fifo_read = true;
+                r_rsp_buf = r_fifo_rsp.read();
+                if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL )
+                    r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT;
+                else
+                    r_rsp_fsm = RSP_DSPIN_MULTI_FLIT;
+            }
+            break;
+        }
+        case RSP_DSPIN_SINGLE_FLIT:
+        {
+            if ( p_vci.rspack.read() )
+                r_rsp_fsm = RSP_IDLE;
+            break;
+        }
+        case RSP_DSPIN_MULTI_FLIT:
+        {
+            if( r_fifo_rsp.rok() && p_vci.rspack.read() )
+            {
+                rsp_fifo_read = true;
+                if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL )
+                    r_rsp_fsm = RSP_IDLE;
+            }
+            break;
+        }
     } // end switch r_rsp_fsm
 
@@ -275,45 +287,45 @@
 {
     // VCI CMD interface
-        if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) )
-        {
-            p_vci.cmdack = false;
-        }
+    if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) )
+    {
+        p_vci.cmdack = false;
+    }
     else
-        {
-            p_vci.cmdack = r_fifo_cmd.wok();
-        }
+    {
+        p_vci.cmdack = r_fifo_cmd.wok();
+    }
 
     // VCI RSP interface
     if ( r_rsp_fsm.read() == RSP_IDLE )
-        {
-            p_vci.rspval = false;
-        }
-        else if ( r_rsp_fsm.read() == RSP_WRITE )
-        {
-            p_vci.rspval = true;
-            p_vci.rdata  = 0;
-            p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18);
-            p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x000000F00LL) >> 8);
-            p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read() & 0x00000F000LL) >> 12);
-            p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000LL) >> 16);
-            p_vci.reop   = true;
-        }
-        else if ( r_rsp_fsm.read() == RSP_READ )
-        {
-            p_vci.rspval = r_fifo_rsp.rok();
-            p_vci.rdata  = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFFLL);
-            p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read()   & 0x0FFFC0000LL) >> 18);
-            p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read()   & 0x000000F00LL) >> 8);
-            p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read()   & 0x00000F000LL) >> 12);
-            p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read()   & 0x000030000LL) >> 16);
-            p_vci.reop   = ((r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL);
-        }
-
-        // DSPIN_OUT interface
-        p_dspin_out.write = r_fifo_cmd.rok();
-        p_dspin_out.data  = r_fifo_cmd.read();
-
-        // DSPIN_IN interface
-        p_dspin_in.read   = r_fifo_rsp.wok();
+    {
+        p_vci.rspval = false;
+    }
+    else if ( r_rsp_fsm.read() == RSP_DSPIN_SINGLE_FLIT )
+    {
+        p_vci.rspval = true;
+        p_vci.rdata  = 0;
+        p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18);
+        p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x000000F00LL) >> 8);
+        p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read() & 0x00000F000LL) >> 12);
+        p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000LL) >> 16);
+        p_vci.reop   = true;
+    }
+    else if ( r_rsp_fsm.read() == RSP_DSPIN_MULTI_FLIT )
+    {
+        p_vci.rspval = r_fifo_rsp.rok();
+        p_vci.rdata  = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFFLL);
+        p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read()   & 0x0FFFC0000LL) >> 18);
+        p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read()   & 0x000000F00LL) >> 8);
+        p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read()   & 0x00000F000LL) >> 12);
+        p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read()   & 0x000030000LL) >> 16);
+        p_vci.reop   = ((r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL);
+    }
+
+    // DSPIN_OUT interface
+    p_dspin_out.write = r_fifo_cmd.rok();
+    p_dspin_out.data  = r_fifo_cmd.read();
+
+    // DSPIN_IN interface
+    p_dspin_in.read   = r_fifo_rsp.wok();
 
 }; // end genMoore
@@ -330,7 +342,7 @@
     };
     const char* rsp_str[] = {
-    "RSP_IDLE     ",
-    "RSP_READ     ",
-    "RSP_WRITE    ",
+    "RSP_IDLE             ",
+    "RSP_DSPIN_SINGLE_FLIT",
+    "RSP_DSPIN_MULTI_FLIT ",
     };
 
