Index: /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h =================================================================== --- /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h (revision 286) +++ /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h (revision 287) @@ -5,22 +5,25 @@ * * SOCLIB_LGPL_HEADER_BEGIN - * + * * This file is part of SoCLib, GNU LGPLv2.1. - * + * * SoCLib is free software; you can redistribute it and/or modify it * under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation; version 2.1 of the License. - * + * * SoCLib is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with SoCLib; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA * 02110-1301 USA - * + * * SOCLIB_LGPL_HEADER_END + * + * Maintainers: alexandre.joannou@lip6.fr + * */ @@ -41,7 +44,7 @@ // - VCI plen == 8 bits // - VCI srcid <= 14 bits -// - VCI trdid <= 8 bits -// - VCI pktid field not transmitted -// - VCI rerror == 2 bits +// - VCI trdid <= 4 bits +// - VCI pktid <= 4 bits +// - VCI rerror == 1 bit //////////////////////////////////////////////////////////////////////// @@ -60,20 +63,20 @@ template class VciVdspinInitiatorWrapper - : public soclib::caba::BaseModule + : public soclib::caba::BaseModule { - // Command FSM + // Command FSM enum fsm_state_cmd{ - CMD_IDLE, - CMD_BROADCAST, - CMD_READ, - CMD_WRITE, - CMD_WDATA, + CMD_IDLE, + CMD_BROADCAST, + CMD_READ, + CMD_WRITE, + CMD_WDATA, }; // Response FSM enum fsm_state_rsp{ - RSP_IDLE, - RSP_READ, - RSP_WRITE, + RSP_IDLE, + RSP_DSPIN_SINGLE_FLIT, + RSP_DSPIN_MULTI_FLIT, }; @@ -83,23 +86,23 @@ public: // ports - sc_core::sc_in p_clk; - sc_core::sc_in p_resetn; - soclib::caba::DspinOutput p_dspin_out; - soclib::caba::DspinInput p_dspin_in; - soclib::caba::VciTarget p_vci; + sc_core::sc_in p_clk; + sc_core::sc_in p_resetn; + soclib::caba::DspinOutput p_dspin_out; + soclib::caba::DspinInput p_dspin_in; + soclib::caba::VciTarget p_vci; // constructor / destructor - VciVdspinInitiatorWrapper( sc_module_name name, - size_t cmd_fifo_depth, - size_t rsp_fifo_depth); + VciVdspinInitiatorWrapper( sc_module_name name, + size_t cmd_fifo_depth, + size_t rsp_fifo_depth ); private: // internal registers - sc_core::sc_signal r_cmd_fsm; - sc_core::sc_signal r_rsp_fsm; - sc_core::sc_signal > r_rsp_buf; + sc_core::sc_signal r_cmd_fsm; + sc_core::sc_signal r_rsp_fsm; + sc_core::sc_signal > r_rsp_buf; // fifos cmd and rsp - soclib::caba::GenericFifo > r_fifo_cmd; - soclib::caba::GenericFifo > r_fifo_rsp; + soclib::caba::GenericFifo > r_fifo_cmd; + soclib::caba::GenericFifo > r_fifo_rsp; // methods systemc @@ -113,5 +116,5 @@ }} // end namespace - + #endif // VCI_VDSPIN_INITIATOR_WRAPPER_H_ Index: /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp =================================================================== --- /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp (revision 286) +++ /trunk/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp (revision 287) @@ -23,4 +23,7 @@ * * SOCLIB_LGPL_HEADER_END + * + * Maintainers: alexandre.joannou@lip6.fr + * */ @@ -31,22 +34,23 @@ #define tmpl(x) template x VciVdspinInitiatorWrapper -//////////////////////////////////////////////////////////://////////////////////////////// -tmpl(/**/)::VciVdspinInitiatorWrapper(sc_module_name name, - size_t cmd_fifo_depth, - size_t rsp_fifo_depth) - : soclib::caba::BaseModule(name), - p_clk("p_clk"), - p_resetn("p_resetn"), - p_dspin_out("p_dspin_out"), - p_dspin_in("p_dspin_in"), - p_vci("p_vci"), - r_cmd_fsm("r_cmd_fsm"), - r_rsp_fsm("r_rsp_fsm"), - r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), - r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) +////////////////////////////////////////////////////////////////////////////////////////// +tmpl(/**/)::VciVdspinInitiatorWrapper( sc_module_name name, + size_t cmd_fifo_depth, + size_t rsp_fifo_depth ) + : soclib::caba::BaseModule(name), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_dspin_out("p_dspin_out"), + p_dspin_in("p_dspin_in"), + p_vci("p_vci"), + r_cmd_fsm("r_cmd_fsm"), + r_rsp_fsm("r_rsp_fsm"), + r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), + r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) { SC_METHOD (transition); dont_initialize(); sensitive << p_clk.pos(); + SC_METHOD (genMoore); dont_initialize(); @@ -56,9 +60,10 @@ assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); - assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); - assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); - assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); - assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); - assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); + assert( (vci_param::B == 4 ) && "The VCI DATA filds must have 32 bits"); + assert( (vci_param::K == 8 ) && "The VCI PLEN field cannot have more than 8 bits"); + assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 14 bits"); + assert( (vci_param::T <= 4 ) && "The VCI TRDID field cannot have more than 4 bits"); + assert( (vci_param::P <= 4 ) && "The VCI PKTID field cannot have more than 4 bits"); + assert( (vci_param::E <= 2 ) && "The VCI RERROR field cannot have more than 2 bits"); } // end constructor @@ -68,13 +73,13 @@ { sc_uint cmd_fifo_data; - bool cmd_fifo_write; - bool cmd_fifo_read; + bool cmd_fifo_write; + bool cmd_fifo_read; sc_uint rsp_fifo_data; - bool rsp_fifo_write; - bool rsp_fifo_read; + bool rsp_fifo_write; + bool rsp_fifo_read; if (p_resetn == false) - { + { r_fifo_cmd.init(); r_fifo_rsp.init(); @@ -123,5 +128,5 @@ else address = address << (39 - vci_param::N); - if ( is_broadcast ) // VCI broacast command + if ( is_broadcast ) // VCI broacast command { r_cmd_fsm = CMD_BROADCAST; @@ -131,10 +136,10 @@ 0x0000000001LL; } - else if (is_read ) // VCI READ command + else if (is_read ) // VCI READ command { r_cmd_fsm = CMD_READ; cmd_fifo_data = address & 0x7FFFFFFFFELL; } - else // VCI WRITE command + else // VCI WRITE command { r_cmd_fsm = CMD_WRITE; @@ -144,5 +149,5 @@ break; } - case CMD_BROADCAST: // write second DSPIN flit in case of broadcast + case CMD_BROADCAST: // write second DSPIN flit in case of broadcast { if( p_vci.cmdval && r_fifo_cmd.wok() ) @@ -158,5 +163,5 @@ break; } - case CMD_READ: // write second DSPIN flit in case of read/write + case CMD_READ: // write second DSPIN flit in case of read/write case CMD_WRITE: { @@ -179,10 +184,10 @@ if ( p_vci.cons.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000200000LL ; - if( r_cmd_fsm == CMD_READ ) // read command + if( r_cmd_fsm == CMD_READ ) // read command { r_cmd_fsm = CMD_IDLE; cmd_fifo_data = cmd_fifo_data | 0x8000000000LL ; } - else // write command + else // write command { r_cmd_fsm = CMD_WDATA; @@ -221,11 +226,12 @@ // The FIFO output is analysed and translated to a VCI packet ////////////////////////////////////////////////////////////// - // - A N+1 flits DSPIN read response packet is translated + // - A N+1 flits DSPIN response packet is translated // to a N flits VCI response. - // - A single flit DSPIN write response packet is translated - // to a single flit VCI response. + // - A single flit DSPIN response packet is translated + // to a single flit VCI response with RDATA = 0. // A valid DSPIN flit in the fifo_rsp is always consumed // in the CMD_IDLE state, but no VCI flit is transmitted. - // The VCI flits are sent in the RSP_READ & RSP_WRITE states. + // The VCI flits are sent in the RSP_DSPIN_SINGLE_FLIT & + // RSP_DSPIN_MULTI_FLIT states. ////////////////////////////////////////////////////////////// @@ -235,31 +241,37 @@ // r_rsp_fsm, rsp_fifo_read - rsp_fifo_read = false; // default value - - switch(r_rsp_fsm) { + rsp_fifo_read = false; // default value + + switch(r_rsp_fsm) + { case RSP_IDLE: - { - if( r_fifo_rsp.rok() ) - { - rsp_fifo_read = true; - r_rsp_buf = r_fifo_rsp.read(); - if ( (r_fifo_rsp.read() & 0x000020000LL) == 0 ) r_rsp_fsm = RSP_READ; - else r_rsp_fsm = RSP_WRITE; - } - break; - } - case RSP_READ: { - if( r_fifo_rsp.rok() && p_vci.rspack.read() ) - { - rsp_fifo_read = true; - if ( (r_fifo_rsp.read() & 0x100000000LL) ) r_rsp_fsm = RSP_IDLE; - } - break; - } - case RSP_WRITE: - { - if ( p_vci.rspack.read() ) r_rsp_fsm = RSP_IDLE; - } + if( r_fifo_rsp.rok() ) + { + rsp_fifo_read = true; + r_rsp_buf = r_fifo_rsp.read(); + if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL ) + r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT; + else + r_rsp_fsm = RSP_DSPIN_MULTI_FLIT; + } + break; + } + case RSP_DSPIN_SINGLE_FLIT: + { + if ( p_vci.rspack.read() ) + r_rsp_fsm = RSP_IDLE; + break; + } + case RSP_DSPIN_MULTI_FLIT: + { + if( r_fifo_rsp.rok() && p_vci.rspack.read() ) + { + rsp_fifo_read = true; + if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL ) + r_rsp_fsm = RSP_IDLE; + } + break; + } } // end switch r_rsp_fsm @@ -275,45 +287,45 @@ { // VCI CMD interface - if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) ) - { - p_vci.cmdack = false; - } + if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) ) + { + p_vci.cmdack = false; + } else - { - p_vci.cmdack = r_fifo_cmd.wok(); - } + { + p_vci.cmdack = r_fifo_cmd.wok(); + } // VCI RSP interface if ( r_rsp_fsm.read() == RSP_IDLE ) - { - p_vci.rspval = false; - } - else if ( r_rsp_fsm.read() == RSP_WRITE ) - { - p_vci.rspval = true; - p_vci.rdata = 0; - p_vci.rsrcid = (sc_uint)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18); - p_vci.rpktid = (sc_uint)((r_rsp_buf.read() & 0x000000F00LL) >> 8); - p_vci.rtrdid = (sc_uint)((r_rsp_buf.read() & 0x00000F000LL) >> 12); - p_vci.rerror = (sc_uint)((r_rsp_buf.read() & 0x000030000LL) >> 16); - p_vci.reop = true; - } - else if ( r_rsp_fsm.read() == RSP_READ ) - { - p_vci.rspval = r_fifo_rsp.rok(); - p_vci.rdata = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFFLL); - p_vci.rsrcid = (sc_uint)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18); - p_vci.rpktid = (sc_uint)((r_rsp_buf.read() & 0x000000F00LL) >> 8); - p_vci.rtrdid = (sc_uint)((r_rsp_buf.read() & 0x00000F000LL) >> 12); - p_vci.rerror = (sc_uint)((r_rsp_buf.read() & 0x000030000LL) >> 16); - p_vci.reop = ((r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL); - } - - // DSPIN_OUT interface - p_dspin_out.write = r_fifo_cmd.rok(); - p_dspin_out.data = r_fifo_cmd.read(); - - // DSPIN_IN interface - p_dspin_in.read = r_fifo_rsp.wok(); + { + p_vci.rspval = false; + } + else if ( r_rsp_fsm.read() == RSP_DSPIN_SINGLE_FLIT ) + { + p_vci.rspval = true; + p_vci.rdata = 0; + p_vci.rsrcid = (sc_uint)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18); + p_vci.rpktid = (sc_uint)((r_rsp_buf.read() & 0x000000F00LL) >> 8); + p_vci.rtrdid = (sc_uint)((r_rsp_buf.read() & 0x00000F000LL) >> 12); + p_vci.rerror = (sc_uint)((r_rsp_buf.read() & 0x000030000LL) >> 16); + p_vci.reop = true; + } + else if ( r_rsp_fsm.read() == RSP_DSPIN_MULTI_FLIT ) + { + p_vci.rspval = r_fifo_rsp.rok(); + p_vci.rdata = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFFLL); + p_vci.rsrcid = (sc_uint)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18); + p_vci.rpktid = (sc_uint)((r_rsp_buf.read() & 0x000000F00LL) >> 8); + p_vci.rtrdid = (sc_uint)((r_rsp_buf.read() & 0x00000F000LL) >> 12); + p_vci.rerror = (sc_uint)((r_rsp_buf.read() & 0x000030000LL) >> 16); + p_vci.reop = ((r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL); + } + + // DSPIN_OUT interface + p_dspin_out.write = r_fifo_cmd.rok(); + p_dspin_out.data = r_fifo_cmd.read(); + + // DSPIN_IN interface + p_dspin_in.read = r_fifo_rsp.wok(); }; // end genMoore @@ -330,7 +342,7 @@ }; const char* rsp_str[] = { - "RSP_IDLE ", - "RSP_READ ", - "RSP_WRITE ", + "RSP_IDLE ", + "RSP_DSPIN_SINGLE_FLIT", + "RSP_DSPIN_MULTI_FLIT ", }; Index: /trunk/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h =================================================================== --- /trunk/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h (revision 286) +++ /trunk/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h (revision 287) @@ -5,22 +5,25 @@ * * SOCLIB_LGPL_HEADER_BEGIN - * + * * This file is part of SoCLib, GNU LGPLv2.1. - * + * * SoCLib is free software; you can redistribute it and/or modify it * under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation; version 2.1 of the License. - * + * * SoCLib is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with SoCLib; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA * 02110-1301 USA - * + * * SOCLIB_LGPL_HEADER_END + * + * Maintainers: alexandre.joannou@lip6.fr + * */ @@ -39,9 +42,9 @@ // - VCI address width <= 40 bits // - VCI data == 32 bits -// - VCI plen == 8 bits -// - VCI srcid <= 14 bits -// - VCI trdid <= 8 bits -// - VCI pktid field not transmitted -// - VCI rerror == 2 bits +// - VCI plen == 8 bits +// - VCI srcid <= 14 bits +// - VCI trdid <= 4 bits +// - VCI pktid <= 4 bits +// - VCI rerror == 1 bit //////////////////////////////////////////////////////////////////////// @@ -62,8 +65,8 @@ template class VciVdspinTargetWrapper - : public soclib::caba::BaseModule + : public soclib::caba::BaseModule { - // Command FSM + // Command FSM enum fsm_state_cmd{ CMD_IDLE, @@ -77,6 +80,6 @@ enum fsm_state_rsp{ RSP_IDLE, - RSP_READ, - RSP_WRITE, + RSP_DSPIN_SINGLE_FLIT, + RSP_DSPIN_MULTI_FLIT, }; @@ -86,25 +89,25 @@ public: // ports - sc_core::sc_in p_clk; - sc_core::sc_in p_resetn; - soclib::caba::DspinOutput p_dspin_out; - soclib::caba::DspinInput p_dspin_in; - soclib::caba::VciInitiator p_vci; + sc_core::sc_in p_clk; + sc_core::sc_in p_resetn; + soclib::caba::DspinOutput p_dspin_out; + soclib::caba::DspinInput p_dspin_in; + soclib::caba::VciInitiator p_vci; // constructor / destructor - VciVdspinTargetWrapper( sc_module_name name, - size_t cmd_fifo_depth, - size_t rsp_fifo_depth); + VciVdspinTargetWrapper( sc_module_name name, + size_t cmd_fifo_depth, + size_t rsp_fifo_depth ); private: // internal registers - sc_core::sc_signal r_cmd_fsm; - sc_core::sc_signal > r_cmd_buf0; - sc_core::sc_signal > r_cmd_buf1; - sc_core::sc_signal r_rsp_fsm; - sc_core::sc_signal r_flit_count; + sc_core::sc_signal r_cmd_fsm; + sc_core::sc_signal > r_cmd_buf0; + sc_core::sc_signal > r_cmd_buf1; + sc_core::sc_signal r_rsp_fsm; + sc_core::sc_signal r_flit_count; // fifos cmd and rsp - soclib::caba::GenericFifo > r_fifo_cmd; - soclib::caba::GenericFifo > r_fifo_rsp; + soclib::caba::GenericFifo > r_fifo_cmd; + soclib::caba::GenericFifo > r_fifo_rsp; // methods systemc @@ -118,5 +121,5 @@ }} // end namespace - + #endif // VCI_VDSPIN_TARGET_WRAPPER_H_ Index: /trunk/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp =================================================================== --- /trunk/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp (revision 286) +++ /trunk/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp (revision 287) @@ -23,4 +23,7 @@ * * SOCLIB_LGPL_HEADER_END + * + * Maintainers: alexandre.joannou@lip6.fr + * */ @@ -33,50 +36,52 @@ #define tmpl(x) template x VciVdspinTargetWrapper -//////////////////////////////////////////////////////////://////////////////////////////// -tmpl(/**/)::VciVdspinTargetWrapper(sc_module_name name, - size_t cmd_fifo_depth, - size_t rsp_fifo_depth) - : soclib::caba::BaseModule(name), - p_clk("p_clk"), - p_resetn("p_resetn"), - p_dspin_out("p_dspin_out"), - p_dspin_in("p_dspin_in"), - p_vci("p_vci"), - r_cmd_fsm("r_cmd_fsm"), - r_rsp_fsm("r_rsp_fsm"), - r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), - r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) - { +////////////////////////////////////////////////////////////////////////////////////////// +tmpl(/**/)::VciVdspinTargetWrapper( sc_module_name name, + size_t cmd_fifo_depth, + size_t rsp_fifo_depth ) + : soclib::caba::BaseModule(name), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_dspin_out("p_dspin_out"), + p_dspin_in("p_dspin_in"), + p_vci("p_vci"), + r_cmd_fsm("r_cmd_fsm"), + r_rsp_fsm("r_rsp_fsm"), + r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth), + r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth) +{ SC_METHOD (transition); dont_initialize(); sensitive << p_clk.pos(); + SC_METHOD (genMoore); dont_initialize(); sensitive << p_clk.neg(); - assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); - assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); - assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); - assert( (vci_param::B == 4) && "The VCI DATA filds must have 32 bits"); - assert( (vci_param::K == 8) && "The VCI PLEN field cannot have more than 8 bits"); - assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 8 bits"); - assert( (vci_param::T <= 8) && "The VCI TRDID field cannot have more than 8 bits"); - assert( (vci_param::E == 2) && "The VCI RERROR field cannot have more than 2 bits"); - - } // end constructor + assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits"); + assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits"); + assert( (vci_param::N <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); + assert( (vci_param::B == 4 ) && "The VCI DATA filds must have 32 bits"); + assert( (vci_param::K == 8 ) && "The VCI PLEN field cannot have more than 8 bits"); + assert( (vci_param::S <= 14) && "The VCI SRCID field cannot have more than 14 bits"); + assert( (vci_param::T <= 4 ) && "The VCI TRDID field cannot have more than 4 bits"); + assert( (vci_param::P <= 4 ) && "The VCI PKTID field cannot have more than 4 bits"); + assert( (vci_param::E <= 2 ) && "The VCI RERROR field cannot have more than 2 bits"); + +} // end constructor ///////////////////////// tmpl(void)::transition() { - sc_uint cmd_fifo_data; - bool cmd_fifo_write; - bool cmd_fifo_read; - - sc_uint rsp_fifo_data; - bool rsp_fifo_write; - bool rsp_fifo_read; + sc_uint cmd_fifo_data; + bool cmd_fifo_write; + bool cmd_fifo_read; + + sc_uint rsp_fifo_data; + bool rsp_fifo_write; + bool rsp_fifo_read; if (p_resetn == false) - { + { r_fifo_cmd.init(); r_fifo_rsp.init(); @@ -91,11 +96,12 @@ // and the DSPIN packet is stored in the fifo_rsp ///////////////////////////////////////////////////////////// - // - A single flit VCI write response packet is translated - // to a single flit DSPIN response. - // - A N flits VCI read response packet is translated - // to a N+1 flits DSPIN response + // - A single flit VCI response packet with a 0 RDATA value + // is translated to a single flit DSPIN response. + // - All other VCI responses are translated to a multi-flit + // DSPIN response. // In the RSP_IDLE state, the first DSPIN flit is written // in fifo_rsp , but no VCI flit is consumed. The VCI flits - // are consumed in the RSP_READ or RSP_WRITE states. + // are consumed in the RSP_DSPIN_SINGLE_FLIT, or the + // SP_DSPIN_MULTI_FLIT states. ////////////////////////////////////////////////////////////// @@ -104,50 +110,55 @@ // r_rsp_fsm, rsp_fifo_write and rsp_fifo_data - rsp_fifo_write = false; // default value - - switch(r_rsp_fsm) { + rsp_fifo_write = false; // default value + + switch(r_rsp_fsm) + { case RSP_IDLE: // write first DSPIN flit into rsp_fifo - { - if( p_vci.rspval && r_fifo_rsp.wok() ) + { + if( p_vci.rspval.read() && r_fifo_rsp.wok() ) + { + bool is_single_flit = ( p_vci.reop.read() && ( p_vci.rdata.read() == 0) ); + + rsp_fifo_write = true; + rsp_fifo_data = (((sc_uint)p_vci.rsrcid.read()) << 18) | + (((sc_uint)p_vci.rerror.read()) << 16) | + (((sc_uint)p_vci.rtrdid.read()) << 12) | + (((sc_uint)p_vci.rpktid.read()) << 8); + if ( is_single_flit ) { - bool is_read = ( (p_vci.rerror.read() & 0x2) == 0); - - rsp_fifo_write = true; - rsp_fifo_data = (((sc_uint)p_vci.rsrcid.read()) << 18) | - (((sc_uint)p_vci.rerror.read()) << 16) | - (((sc_uint)p_vci.rtrdid.read()) << 12) | - (((sc_uint)p_vci.rpktid.read()) << 8); - if ( is_read ) - { - r_rsp_fsm = RSP_READ; - } - else - { - rsp_fifo_data = rsp_fifo_data | 0x100000000LL; - r_rsp_fsm = RSP_WRITE; - } + rsp_fifo_data = rsp_fifo_data | 0x100000000LL; // EOP = 1 + rsp_fifo_data = rsp_fifo_data & 0x1FFFFFFFELL; // BC = 0 + r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT; } - break; - } - case RSP_READ: // write DSPIN data flit in case of read - { - if( p_vci.rspval && r_fifo_rsp.wok() ) + else { - rsp_fifo_write = true; - rsp_fifo_data = ((sc_uint)p_vci.rdata.read()); - if ( p_vci.reop ) - { - rsp_fifo_data = rsp_fifo_data | 0x100000000LL; - r_rsp_fsm = RSP_IDLE; - } + rsp_fifo_data = rsp_fifo_data & 0x0FFFFFFFFLL; // EOP = 0 + rsp_fifo_data = rsp_fifo_data & 0x1FFFFFFFELL; // BC = 0 + r_rsp_fsm = RSP_DSPIN_MULTI_FLIT; } - break; - } - case RSP_WRITE: - { - rsp_fifo_write = false; - if ( r_fifo_rsp.wok() ) r_rsp_fsm = RSP_IDLE; - break; - } + } + break; + } + case RSP_DSPIN_SINGLE_FLIT: + { + rsp_fifo_write = false; + if ( r_fifo_rsp.wok() ) + r_rsp_fsm = RSP_IDLE; + break; + } + case RSP_DSPIN_MULTI_FLIT: // write DSPIN data flit + { + if( p_vci.rspval && r_fifo_rsp.wok() ) + { + rsp_fifo_write = true; + rsp_fifo_data = ((sc_uint)p_vci.rdata.read()); + if ( p_vci.reop ) + { + rsp_fifo_data = rsp_fifo_data | 0x100000000LL; // EOP = 1 + r_rsp_fsm = RSP_IDLE; + } + } + break; + } } // end switch r_cmd_fsm @@ -157,20 +168,20 @@ if((rsp_fifo_write == false) && (rsp_fifo_read == true)) { r_fifo_rsp.simple_get(); } - ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// // DSPIN command packet to VCI command packet - // The DSPIN packet is stored in the fifo_rsp + // The DSPIN packet is stored in the fifo_cmd // The FIFO output is analysed and translated to a VCI packet - ////////////////////////////////////////////////////////////// - // - A 2 flits DSPIN broadcast command is translated - // to a 1 flit VCI broadcast command. - // - A 2 flits DSPIN read command is translated - // to a 1 flit VCI read command. - // - A N+2 flits DSPIN write command is translated - // to a N flits VCI write command. - // The VCI flits are sent in the CMD_READ, CMD_WDATA - // & CMD_BROADCAST states. - // The r_cmd_buf0 et r_cmd_buf1 buffers are used to store - // the two first DSPIN flits (in case of write). - ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + // - A 2 flits DSPIN broadcast command is translated + // to a 1 flit VCI broadcast command. + // - A 2 flits DSPIN read command is translated + // to a 1 flit VCI read command. + // - A N+2 flits DSPIN write command is translated + // to a N flits VCI write command. + // The VCI flits are sent in the CMD_READ, CMD_WDATA + // & CMD_BROADCAST states. + // The r_cmd_buf0 et r_cmd_buf1 buffers are used to store + // the two first DSPIN flits (in case of write). + ////////////////////////////////////////////////////////////// // cmd_fifo_write, cmd_fifo_data @@ -179,57 +190,66 @@ // r_cmd_fsm, cmd_fifo_read - cmd_fifo_read = false; // default value - - switch(r_cmd_fsm) { + cmd_fifo_read = false; // default value + + switch(r_cmd_fsm) + { case CMD_IDLE: - { - if( r_fifo_cmd.rok() ) - { - bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1); - - cmd_fifo_read = true; - r_cmd_buf0 = r_fifo_cmd.read(); // save address - if ( is_broadcast ) r_cmd_fsm = CMD_BROADCAST; - else r_cmd_fsm = CMD_RW; - } - break; - } + { + if( r_fifo_cmd.rok() ) + { + bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1); + + cmd_fifo_read = true; + r_cmd_buf0 = r_fifo_cmd.read(); // save address + + if ( is_broadcast ) + r_cmd_fsm = CMD_BROADCAST; + else + r_cmd_fsm = CMD_RW; + } + break; + } case CMD_BROADCAST: { - if( r_fifo_cmd.rok() && p_vci.cmdack ) - { - cmd_fifo_read = true; + if( r_fifo_cmd.rok() && p_vci.cmdack ) + { + cmd_fifo_read = true; + r_cmd_fsm = CMD_IDLE; + } + break; + } + case CMD_RW: + { + if( r_fifo_cmd.rok() ) + { + cmd_fifo_read = true; + r_cmd_buf1 = r_fifo_cmd.read(); // save command parameters + // read command if EOP + if ( (r_fifo_cmd.read() & 0x8000000000LL) ) + r_cmd_fsm = CMD_READ; + else + r_cmd_fsm = CMD_WDATA; + r_flit_count = 0; + } + break; + } + case CMD_READ: + { + if ( p_vci.cmdack.read() ) + r_cmd_fsm = CMD_IDLE; + break; + } + case CMD_WDATA: + { + if( r_fifo_cmd.rok() && p_vci.cmdack.read() ) + { + if ( (r_cmd_buf1.read() & 0x0000200000LL) == 0 ) + r_flit_count = r_flit_count + 1; + cmd_fifo_read = true; + if ( (r_fifo_cmd.read() & 0x8000000000LL) ) r_cmd_fsm = CMD_IDLE; - } - break; - } - case CMD_RW: - { - if( r_fifo_cmd.rok() ) - { - cmd_fifo_read = true; - r_cmd_buf1 = r_fifo_cmd.read(); // save command parameters - // read command if EOP - if ( (r_fifo_cmd.read() & 0x8000000000LL) ) r_cmd_fsm = CMD_READ; - else r_cmd_fsm = CMD_WDATA; - r_flit_count = 0; - } - break; - } - case CMD_READ: - { - if ( p_vci.cmdack.read() ) r_cmd_fsm = CMD_IDLE; - break; - } - case CMD_WDATA: - { - if( r_fifo_cmd.rok() && p_vci.cmdack.read() ) - { - if ( (r_cmd_buf1.read() & 0x0000200000LL) == 0 ) r_flit_count = r_flit_count + 1; - cmd_fifo_read = true; - if ( (r_fifo_cmd.read() & 0x8000000000LL) ) r_cmd_fsm = CMD_IDLE; - } - break; - } + } + break; + } } // end switch r_cmd_fsm @@ -245,38 +265,58 @@ { // VCI RSP interface - if ( r_rsp_fsm.read() == RSP_IDLE ) p_vci.rspack = false; - else p_vci.rspack = r_fifo_rsp.wok(); + if ( r_rsp_fsm.read() == RSP_IDLE ) p_vci.rspack = false; + else p_vci.rspack = r_fifo_rsp.wok(); // VCI CMD interface if ( (r_cmd_fsm.read() == CMD_IDLE) || (r_cmd_fsm.read() == CMD_RW) ) + { + p_vci.cmdval = false; + } + else if ( r_cmd_fsm.read() == CMD_BROADCAST ) // VCI CMD broadcast + { + if ( r_fifo_cmd.rok() ) + { + sc_uint minmax = r_cmd_buf0.read() & 0x7FFFF80000LL; + if ( vci_param::N == 40 ) minmax = (minmax << 1); + else minmax = (minmax >> (39 - vci_param::N) ); + p_vci.cmdval = true; + p_vci.address = (sc_uint)minmax | 0x3; + p_vci.cmd = vci_param::CMD_WRITE; + p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); + p_vci.be = (sc_uint)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); + p_vci.srcid = (sc_uint)((r_cmd_buf0.read() & 0x000007FFE0LL) >> 5); + p_vci.trdid = (sc_uint)((r_cmd_buf0.read() & 0x000000001ELL) >> 1); + p_vci.pktid = 0; + p_vci.plen = vci_param::B; + p_vci.contig = true; + p_vci.cons = false; + p_vci.eop = true; + } + else { p_vci.cmdval = false; } - else if ( r_cmd_fsm.read() == CMD_BROADCAST ) // VCI CMD broadcast - { - if ( r_fifo_cmd.rok() ) - { - sc_uint minmax = r_cmd_buf0.read() & 0x7FFFF80000LL; - if ( vci_param::N == 40 ) minmax = (minmax << 1); - else minmax = (minmax >> (39 - vci_param::N) ); - p_vci.cmdval = true; - p_vci.address = (sc_uint)minmax | 0x3; - p_vci.cmd = vci_param::CMD_WRITE; - p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); - p_vci.be = (sc_uint)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); - p_vci.srcid = (sc_uint)((r_cmd_buf0.read() & 0x000007FFE0LL) >> 5); - p_vci.trdid = (sc_uint)((r_cmd_buf0.read() & 0x000000001ELL) >> 1); - p_vci.pktid = 0; - p_vci.plen = vci_param::B; - p_vci.contig = true; - p_vci.cons = false; - p_vci.eop = true; - } - else - { - p_vci.cmdval = false; - } - } - else if ( r_cmd_fsm.read() == CMD_READ ) // VCI CMD read + } + else if ( r_cmd_fsm.read() == CMD_READ ) // VCI CMD read + { + sc_uint address; + if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1); + else address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); + p_vci.cmdval = true; + p_vci.address = address; + p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23); + p_vci.wdata = 0; + p_vci.be = (sc_uint)((r_cmd_buf1.read() & 0x000000001ELL) >> 1); + p_vci.srcid = (sc_uint)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25); + p_vci.pktid = (sc_uint)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5); + p_vci.trdid = (sc_uint)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9); + p_vci.plen = (sc_uint)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13); + p_vci.contig = ((r_cmd_buf1.read() & 0x0000400000LL) != 0); + p_vci.cons = ((r_cmd_buf1.read() & 0x0000200000LL) != 0); + p_vci.eop = true; + } + else if ( r_cmd_fsm.read() == CMD_WDATA ) // VCI write command + { + if ( r_fifo_cmd.rok() ) { sc_uint address; @@ -284,41 +324,21 @@ else address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); p_vci.cmdval = true; - p_vci.address = address; - p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23); - p_vci.wdata = 0; - p_vci.be = (sc_uint)((r_cmd_buf1.read() & 0x000000001ELL) >> 1); - p_vci.srcid = (sc_uint)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25); - p_vci.pktid = (sc_uint)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5); - p_vci.trdid = (sc_uint)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9); - p_vci.plen = (sc_uint)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13); + p_vci.address = address + (r_flit_count.read()*vci_param::B); + p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23); + p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); + p_vci.be = (sc_uint)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); + p_vci.srcid = (sc_uint)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25); + p_vci.pktid = (sc_uint)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5); + p_vci.trdid = (sc_uint)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9); + p_vci.plen = (sc_uint)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13); p_vci.contig = ((r_cmd_buf1.read() & 0x0000400000LL) != 0); p_vci.cons = ((r_cmd_buf1.read() & 0x0000200000LL) != 0); - p_vci.eop = true; + p_vci.eop = ((r_fifo_cmd.read() & 0x8000000000LL) == 0x8000000000LL); + } + else + { + p_vci.cmdval = false; + } } - else if ( r_cmd_fsm.read() == CMD_WDATA ) // VCI write command - { - if ( r_fifo_cmd.rok() ) - { - sc_uint address; - if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1); - else address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); - p_vci.cmdval = true; - p_vci.address = address + (r_flit_count.read()*vci_param::B); - p_vci.cmd = (sc_uint<2>)((r_cmd_buf1.read() & 0x0001800000LL) >> 23); - p_vci.wdata = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL); - p_vci.be = (sc_uint)((r_fifo_cmd.read() & 0x0F00000000LL) >> 32); - p_vci.srcid = (sc_uint)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25); - p_vci.pktid = (sc_uint)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5); - p_vci.trdid = (sc_uint)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9); - p_vci.plen = (sc_uint)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13); - p_vci.contig = ((r_cmd_buf1.read() & 0x0000400000LL) != 0); - p_vci.cons = ((r_cmd_buf1.read() & 0x0000200000LL) != 0); - p_vci.eop = ((r_fifo_cmd.read() & 0x8000000000LL) == 0x8000000000LL); - } - else - { - p_vci.cmdval = false; - } - } // DSPIN_OUT interface @@ -342,7 +362,7 @@ }; const char* rsp_str[] = { - "RSP_IDLE ", - "RSP_READ ", - "RSP_WRITE ", + "RSP_IDLE ", + "RSP_DSPIN_SINGLE_FLIT", + "RSP_DSPIN_MULTI_FLIT ", }; std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()]