Index: /trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
===================================================================
--- /trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h	(revision 288)
+++ /trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h	(revision 289)
@@ -620,4 +620,96 @@
   }; // end class HeapDirectory
 
+  ////////////////////////////////////////////////////////////////////////
+  //                        Cache Data 
+  ////////////////////////////////////////////////////////////////////////
+  class CacheData {
+    private:
+      const uint32_t m_sets;
+      const uint32_t m_ways;
+      const uint32_t m_words;
+
+      uint32_t *** m_cache_data;
+
+    public:
+
+      CacheData(uint32_t ways, uint32_t sets, uint32_t words)
+        : m_sets(sets), m_ways(ways), m_words(words) {
+
+          m_cache_data = new uint32_t ** [ways];
+          for ( size_t i=0 ; i < ways ; i++ ) {
+            m_cache_data[i] = new uint32_t * [sets];
+          }
+          for ( size_t i=0; i<ways; i++ ) {
+            for ( size_t j=0; j<sets; j++ ) {
+              m_cache_data[i][j] = new uint32_t [words];
+            }
+          }
+        }
+
+      ~CacheData() {
+          for(size_t i=0; i<m_ways ; i++){
+              for(size_t j=0; j<m_sets ; j++){
+                  delete [] m_cache_data[i][j];
+              }
+          }
+          for(size_t i=0; i<m_ways ; i++){
+              delete [] m_cache_data[i];
+          }
+          delete [] m_cache_data;
+      }
+
+      uint32_t read (
+          const uint32_t &way,
+          const uint32_t &set,
+          const uint32_t &word) const {
+
+        assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
+        assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way" );
+        assert((word < m_words) && "Cache data error: Trying to read a wrong word");
+
+        return m_cache_data[way][set][word];
+      }
+
+      void read_line(
+          const uint32_t &way,
+          const uint32_t &set,
+          sc_core::sc_signal<uint32_t> * cache_line)
+      {
+        assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
+        assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
+      
+        for (uint32_t word=0; word<m_words; word++)
+          cache_line[word].write(m_cache_data[way][set][word]);
+      }
+
+      void write (
+          const uint32_t &way,
+          const uint32_t &set,
+          const uint32_t &word,
+          const uint32_t &data,
+          const uint32_t &be = 0xF) {
+
+        assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set" );
+        assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way" );
+        assert((word < m_words) && "Cache data error: Trying to write a wrong word");
+        assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong word cell");
+
+        if (be == 0x0) return;
+
+        if (be == 0xF) {
+            m_cache_data[way][set][word] = data; 
+            return;
+        }
+
+        uint32_t mask = 0;
+        if  (be & 0x1) mask = mask | 0x000000FF;
+        if  (be & 0x2) mask = mask | 0x0000FF00;
+        if  (be & 0x4) mask = mask | 0x00FF0000;
+        if  (be & 0x8) mask = mask | 0xFF000000;
+
+        m_cache_data[way][set][word] = 
+          (data & mask) | (m_cache_data[way][set][word] & ~mask);
+      }
+  }; // end class CacheData
 
 }} // end namespaces
Index: /trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
===================================================================
--- /trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h	(revision 288)
+++ /trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h	(revision 289)
@@ -420,7 +420,6 @@
       UpdateTab       m_update_tab;       // pending update & invalidate
       CacheDirectory  m_cache_directory;  // data cache directory
+      CacheData       m_cache_data;       // data array[set][way][word]
       HeapDirectory   m_heap;             // heap for copies
-
-      data_t      *** m_cache_data;       // data array[set][way][word]
 
       // adress masks
Index: /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
===================================================================
--- /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 288)
+++ /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 289)
@@ -276,4 +276,7 @@
     p_vci_ixr("vci_ixr"),
 
+    m_seglist(mtp.getSegmentList(vci_tgt_index)),
+    m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
+
     m_initiators( 1 << vci_param::S ),
     m_heap_size( heap_size ),
@@ -283,6 +286,4 @@
     m_srcid_ixr( mtx.indexForId(vci_ixr_index) ),
     m_srcid_ini( mtc.indexForId(vci_ini_index) ),
-    m_seglist(mtp.getSegmentList(vci_tgt_index)),
-    m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
     m_transaction_tab_lines(transaction_tab_lines),
     m_transaction_tab( transaction_tab_lines, nwords ),
@@ -290,4 +291,5 @@
     m_update_tab( update_tab_lines ),
     m_cache_directory( nways, nsets, nwords, vci_param::N ),
+    m_cache_data( nways, nsets, nwords ),
     m_heap( m_heap_size ),
 
@@ -409,18 +411,4 @@
           m_cseg[i] = &(*seg);
           i++;
-      }
-
-      // Memory cache allocation & initialisation
-      m_cache_data = new data_t**[nways];
-      for ( size_t i=0 ; i<nways ; ++i ) {
-        m_cache_data[i] = new data_t*[nsets];
-      }
-      for ( size_t i=0; i<nways; ++i ) {
-        for ( size_t j=0; j<nsets; ++j ) {
-          m_cache_data[i][j] = new data_t[nwords];
-          for ( size_t k=0; k<nwords; k++){
-            m_cache_data[i][j][k]=0;
-          }
-        }
       }
 
@@ -558,14 +546,4 @@
     /////////////////////////////////
   {
-    for(size_t i=0; i<m_ways ; i++){
-      for(size_t j=0; j<m_sets ; j++){
-        delete [] m_cache_data[i][j];
-      }
-    }
-    for(size_t i=0; i<m_ways ; i++){
-      delete [] m_cache_data[i];
-    }
-    delete [] m_cache_data;
-
     delete [] r_ixr_rsp_to_xram_rsp_rok;
 
@@ -1318,5 +1296,6 @@
         size_t set        = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
         size_t way        = r_read_way.read();
-        for ( size_t i=0 ; i<m_words ; i++ ) r_read_data[i] = m_cache_data[way][set][i];
+
+        m_cache_data.read_line(way, set, r_read_data);
 
         // update the cache directory
@@ -1412,5 +1391,6 @@
         size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
         size_t way = r_read_way.read();
-        for ( size_t i=0 ; i<m_words ; i++ ) r_read_data[i] = m_cache_data[way][set][i];
+
+        m_cache_data.read_line(way, set, r_read_data);
 
         // update the cache directory
@@ -1789,14 +1769,9 @@
 
         // initialize the be field for all words
-        for ( size_t i=0 ; i<m_words ; i++ )
-        {
-          if ( i == index ) r_write_be[i] = m_cmd_write_be_fifo.read();
-          else              r_write_be[i] = 0x0;
-        }
-
-        if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
-          r_write_byte = true;
-        else
-          r_write_byte = false;
+        for ( size_t word=0 ; word<m_words ; word++ )
+        {
+          if ( word == index ) r_write_be[word] = m_cmd_write_be_fifo.read();
+          else                 r_write_be[word] = 0x0;
+        }
 
         if( m_cmd_write_eop_fifo.read() )
@@ -1854,7 +1829,4 @@
         r_write_data[index] = m_cmd_write_data_fifo.read();
         r_write_word_count  = r_write_word_count.read() + 1;
-
-        if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
-          r_write_byte = true;
 
         if ( m_cmd_write_eop_fifo.read() )
@@ -1917,12 +1889,5 @@
           else
           {
-            if (r_write_byte.read())
-            {
-              r_write_fsm = WRITE_DIR_READ;
-            }
-            else
-            {
-              r_write_fsm = WRITE_DIR_HIT;
-            }
+            r_write_fsm = WRITE_DIR_HIT;
           }
         }
@@ -1961,29 +1926,20 @@
       size_t set  = m_y[(vci_addr_t)(r_write_address.read())];
       size_t way  = r_write_way.read();
-      for(size_t i=0 ; i<m_words ; i++)
+      for(size_t word=0 ; word<m_words ; word++)
       {
         data_t mask = 0;
-        if  (r_write_be[i].read() & 0x1) mask = mask | 0x000000FF;
-        if  (r_write_be[i].read() & 0x2) mask = mask | 0x0000FF00;
-        if  (r_write_be[i].read() & 0x4) mask = mask | 0x00FF0000;
-        if  (r_write_be[i].read() & 0x8) mask = mask | 0xFF000000;
+        if  (r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;
+        if  (r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;
+        if  (r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;
+        if  (r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;
 
         // complete only if mask is not null (for energy consumption)
-        if ( r_write_be[i].read() || r_write_is_cnt.read() )
-        {
-          r_write_data[i]  = (r_write_data[i].read() & mask) |
-            (m_cache_data[way][set][i] & ~mask);
-        }
+        r_write_data[word]  = (r_write_data[word].read() & mask) |
+          (m_cache_data.read(way, set, word) & ~mask);
+
       } // end for
 
       // test if a coherence broadcast is required
-      if( r_write_is_cnt.read() && r_write_count.read() )
-      {
-        r_write_fsm = WRITE_BC_TRT_LOCK;
-      }
-      else
-      {
-        r_write_fsm = WRITE_DIR_HIT;
-      }
+      r_write_fsm = WRITE_BC_TRT_LOCK;
 
 #if DEBUG_MEMC_WRITE
@@ -2034,17 +1990,14 @@
       if( no_update )
       {
-        for(size_t i=0 ; i<m_words ; i++)
-        {
-          if  ( r_write_be[i].read() )
+        for(size_t word=0 ; word<m_words ; word++)
+        {
+          m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
+
+          if ( m_monitor_ok )
           {
-            m_cache_data[way][set][i]  = r_write_data[i].read();
-
-            if ( m_monitor_ok )
-            {
-              vci_addr_t address = (r_write_address.read() & ~(vci_addr_t)0x3F) | i<<2;
-              char buf[80];
-              snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", r_write_srcid.read());
-              check_monitor( buf, address, r_write_data[i].read() );
-            }
+            vci_addr_t address = (r_write_address.read() & ~(vci_addr_t)0x3F) | word<<2;
+            char buf[80];
+            snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", r_write_srcid.read());
+            check_monitor( buf, address, r_write_data[word].read() );
           }
         }
@@ -2122,17 +2075,14 @@
         if ( wok )    // write data in cache
         {
-          for(size_t i=0 ; i<m_words ; i++)
+          for(size_t word=0 ; word<m_words ; word++)
           {
-            if ( r_write_be[i].read() )
-            {
-              m_cache_data[way][set][i] = r_write_data[i].read();
-
-              if ( m_monitor_ok )
-              {
-                vci_addr_t address = (r_write_address.read() & ~(vci_addr_t)0x3F) | i<<2;
-                char buf[80];
-                snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", srcid);
-                check_monitor(buf, address, r_write_data[i].read() );
-              }
+            m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
+
+            if ( m_monitor_ok )
+            {
+              vci_addr_t address = (r_write_address.read() & ~(vci_addr_t)0x3F) | word<<2;
+              char buf[80];
+              snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", srcid);
+              check_monitor(buf, address, r_write_data[word].read() );
             }
           }
@@ -2373,14 +2323,9 @@
 
           // initialize the be field for all words
-          for ( size_t i=0 ; i<m_words ; i++ )
+          for ( size_t word=0 ; word<m_words ; word++ )
           {
-            if ( i == index ) r_write_be[i] = m_cmd_write_be_fifo.read();
-            else              r_write_be[i] = 0x0;
+            if ( word == index ) r_write_be[word] = m_cmd_write_be_fifo.read();
+            else                 r_write_be[word] = 0x0;
           }
-
-          if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
-            r_write_byte = true;
-          else
-            r_write_byte = false;
 
           if( m_cmd_write_eop_fifo.read() )
@@ -2428,7 +2373,7 @@
         }
 #endif
-        size_t    hit_index = 0;
-        size_t    wok_index = 0;
-        vci_addr_t  addr      = (vci_addr_t)r_write_address.read();
+        size_t  hit_index = 0;
+        size_t  wok_index = 0;
+        vci_addr_t  addr  = (vci_addr_t)r_write_address.read();
         bool    hit_read  = m_transaction_tab.hit_read(m_nline[addr], hit_index);
         bool    hit_write = m_transaction_tab.hit_write(m_nline[addr]);
@@ -3112,6 +3057,5 @@
 
                 // copy the victim line in a local buffer
-                for (size_t i=0 ; i<m_words ; i++)
-                  r_xram_rsp_victim_data[i] = m_cache_data[way][set][i];
+                m_cache_data.read_line(way, set, r_xram_rsp_victim_data);
 
                 r_xram_rsp_victim_copy      = victim.owner.srcid;
@@ -3228,12 +3172,12 @@
             size_t set   = r_xram_rsp_victim_set.read();
             size_t way   = r_xram_rsp_victim_way.read();
-            for(size_t i=0; i<m_words ; i++)
-            {
-                m_cache_data[way][set][i] = r_xram_rsp_trt_buf.wdata[i];
+            for(size_t word=0; word<m_words ; word++)
+            {
+                m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
 
                 if ( m_monitor_ok )
                 {
-                    vci_addr_t address = r_xram_rsp_trt_buf.nline<<6 | i<<2;
-                    check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[i]);
+                    vci_addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
+                    check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word]);
                 }
             }
@@ -4413,7 +4357,7 @@
 
             // read data in cache & check data change
-            bool ok = ( r_cas_rdata[0].read() == m_cache_data[way][set][word] );
+            bool ok = ( r_cas_rdata[0].read() == m_cache_data.read(way, set, word) );
             if ( r_cas_cpt.read()==4 )  // 64 bits CAS
-                ok &= ( r_cas_rdata[1] == m_cache_data[way][set][word+1] );
+                ok &= ( r_cas_rdata[1] == m_cache_data.read(way, set, word+1));
 
             // to avoid livelock, force the atomic access to fail pseudo-randomly
@@ -4435,5 +4379,5 @@
     std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_READ> Test if CAS success:"
               << " / expected value = " << r_cas_rdata[0].read()
-              << " / actual value = " << m_cache_data[way][set][word]
+              << " / actual value = " << m_cache_data.read(way, set, word)
               << " / forced_fail = " << forced_fail << std::endl;
 }
@@ -4469,7 +4413,7 @@
 
                 // cache update
-                m_cache_data[way][set][word] = r_cas_wdata.read();
+                m_cache_data.write(way, set, word, r_cas_wdata.read());
                 if(r_cas_cpt.read()==4)
-                    m_cache_data[way][set][word+1] = m_cmd_cas_wdata_fifo.read();
+                    m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
 
                 // monitor
@@ -4530,7 +4474,7 @@
                     size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
 
-                    m_cache_data[way][set][word] = r_cas_wdata.read();
+                    m_cache_data.write(way, set, word, r_cas_wdata.read());
                     if(r_cas_cpt.read()==4)
-                        m_cache_data[way][set][word+1] = m_cmd_cas_wdata_fifo.read();
+                        m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
 
                     // monitor
@@ -4714,5 +4658,5 @@
                         else
                         {
-                            r_cas_to_ixr_cmd_data[i] = m_cache_data[way][set][i];
+                            r_cas_to_ixr_cmd_data[i] = m_cache_data.read(way, set, i);
                         }
                     }
@@ -4768,7 +4712,7 @@
                     size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
 
-                    m_cache_data[way][set][word] = r_cas_wdata.read();
+                    m_cache_data.write(way, set, word, r_cas_wdata.read());
                     if(r_cas_cpt.read()==4)
-                        m_cache_data[way][set][word+1] = m_cmd_cas_wdata_fifo.read();
+                        m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
 
                     // monitor