Index: trunk/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd (revision 290) +++ trunk/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd (revision 291) @@ -24,4 +24,5 @@ Uses('common:mapping_table'), Uses('caba:generic_fifo'), + Uses('caba:generic_llsc_global_table'), ], Index: trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 290) +++ trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 291) @@ -54,4 +54,5 @@ #include "mapping_table.h" #include "int_tab.h" +#include "generic_llsc_global_table.h" #include "mem_cache_directory_v4.h" #include "xram_transaction_v4.h" @@ -422,4 +423,12 @@ CacheData m_cache_data; // data array[set][way][word] HeapDirectory m_heap; // heap for copies + GenericLLSCGlobalTable + < + 32 , // desired number of slots + 4096, // number of processors in the system + 8000, // registratioçn life span (in # of LL operations) + typename vci_param::fast_addr_t // address type + > + m_llsc_table; // ll/sc global registration table // adress masks @@ -491,4 +500,6 @@ sc_signal r_read_next_ptr; // Next entry to point to sc_signal r_read_last_free; // Last free entry + sc_signal + r_read_ll_key; // LL key returned by the llsc_global_table // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) @@ -505,4 +516,6 @@ sc_signal r_read_to_tgt_rsp_word; // first word of the response sc_signal r_read_to_tgt_rsp_length; // length of the response + sc_signal + r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table /////////////////////////////////////////////////////////////// @@ -533,10 +546,13 @@ sc_signal r_write_trt_index; // index in Transaction Table sc_signal r_write_upt_index; // index in Update Table + sc_signal r_write_sc_fail; // sc command failed + sc_signal r_write_pending_sc; // sc command pending in WRITE fsm // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) - sc_signal r_write_to_tgt_rsp_req; // valid request - sc_signal r_write_to_tgt_rsp_srcid; // transaction srcid - sc_signal r_write_to_tgt_rsp_trdid; // transaction trdid - sc_signal r_write_to_tgt_rsp_pktid; // transaction pktid + sc_signal r_write_to_tgt_rsp_req; // valid request + sc_signal r_write_to_tgt_rsp_srcid; // transaction srcid + sc_signal r_write_to_tgt_rsp_trdid; // transaction trdid + sc_signal r_write_to_tgt_rsp_pktid; // transaction pktid + sc_signal r_write_to_tgt_rsp_sc_fail; // sc command failed // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) @@ -721,4 +737,6 @@ sc_signal r_xram_rsp_to_tgt_rsp_length; // length of the response sc_signal r_xram_rsp_to_tgt_rsp_rerror; // send error to requester + sc_signal + r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) Index: trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h (revision 290) +++ trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h (revision 291) @@ -32,4 +32,5 @@ std::vector wdata_be; // be for each data in the write buffer bool rerror; // error returned by xram + data_t ll_key; // LL key returned by the llsc_global_table ///////////////////////////////////////////////////////////////////// @@ -127,4 +128,5 @@ wdata.assign(source.wdata.begin(),source.wdata.end()); rerror = source.rerror; + ll_key = source.ll_key; } @@ -325,4 +327,5 @@ // - data : the data to write (in case of write) // - data_be : the mask of the data to write (in case of write) + // - ll_key : the ll key (if any) returned by the llsc_global_table ///////////////////////////////////////////////////////////////////// void set(const size_t index, @@ -336,5 +339,6 @@ const size_t word_index, const std::vector &data_be, - const std::vector &data) + const std::vector &data, + const data_t ll_key = 0) { assert( (index < size_tab) @@ -354,4 +358,5 @@ tab[index].read_length = read_length; tab[index].word_index = word_index; + tab[index].ll_key = ll_key; for(size_t i=0; i>2)) > 16) + // This test checks that the read does not cross a cache line limit. + // It must not be taken into account when dealing with an LL CMD. + if (((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2)) > 16) && ( p_vci_tgt.cmd.read() != vci_param::CMD_LOCKED_READ )) { std::cout @@ -907,5 +911,5 @@ << std::endl; std::cout - << " read command packets must contain one single flit" + << " read or ll command packets must contain one single flit" << std::endl; exit(0); @@ -927,5 +931,8 @@ #endif cmd_read_fifo_put = true; - m_cpt_read++; + if ( p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ ) + m_cpt_ll++; + else + m_cpt_read++; r_tgt_cmd_fsm = TGT_CMD_IDLE; } @@ -1139,5 +1146,5 @@ // READ FSM //////////////////////////////////////////////////////////////////////////////////// - // The READ FSM controls the VCI read requests. + // The READ FSM controls the VCI read and ll requests. // It takes the lock protecting the cache directory to check the cache line status: // - In case of HIT @@ -1174,4 +1181,5 @@ << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() << " / address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read() << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; } @@ -1211,5 +1219,8 @@ DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); - + if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) // access the global table ONLY when we have an LL cmd + { + r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); + } r_read_is_cnt = entry.is_cnt; r_read_dirty = entry.dirty; @@ -1256,4 +1267,9 @@ << " / count = " < global_llsc_table LL access" << std::endl; + } } #endif @@ -1604,7 +1620,8 @@ r_read_to_tgt_rsp_trdid = m_cmd_read_trdid_fifo.read(); r_read_to_tgt_rsp_pktid = m_cmd_read_pktid_fifo.read(); - cmd_read_fifo_get = true; - r_read_to_tgt_rsp_req = true; - r_read_fsm = READ_IDLE; + r_read_to_tgt_rsp_ll_key = r_read_ll_key.read(); + cmd_read_fifo_get = true; + r_read_to_tgt_rsp_req = true; + r_read_fsm = READ_IDLE; #if DEBUG_MEMC_READ @@ -1673,5 +1690,6 @@ m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())], std::vector(m_words,0), - std::vector(m_words,0)); + std::vector(m_words,0), + r_read_ll_key.read()); #if DEBUG_MEMC_READ if( m_debug_read_fsm ) @@ -1718,5 +1736,5 @@ // WRITE FSM /////////////////////////////////////////////////////////////////////////////////// - // The WRITE FSM handles the write bursts sent by the processors. + // The WRITE FSM handles the write bursts and sc requests sent by the processors. // All addresses in a burst must be in the same cache line. // A complete write burst is consumed in the FIFO & copied to a local buffer. @@ -1728,5 +1746,5 @@ // returned to the writing processor. // If the data is cached by other processors, a coherence transaction must - // be launched: + // be launched (sc requests always require a coherence transaction): // It is a multicast update if the line is not in counter mode, and the processor // takes the lock protecting the Update Table (UPT) to register this transaction. @@ -1753,9 +1771,15 @@ if ( m_cmd_write_addr_fifo.rok() ) { - m_cpt_write++; - m_cpt_write_cells++; + if((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) + m_cpt_sc++; + else + { + m_cpt_write++; + m_cpt_write_cells++; + } // consume a word in the FIFO & write it in the local buffer cmd_write_fifo_get = true; + r_write_pending_sc = false; size_t index = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())]; @@ -1775,5 +1799,5 @@ } - if( m_cmd_write_eop_fifo.read() ) + if( m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) ) { r_write_fsm = WRITE_DIR_REQ; @@ -1824,4 +1848,5 @@ // consume a word in the FIFO & write it in the local buffer cmd_write_fifo_get = true; + r_write_pending_sc = false; size_t index = r_write_word_index.read() + r_write_word_count.read(); @@ -1844,4 +1869,36 @@ if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) { + if(((r_write_pktid.read() & 0x7) == TYPE_SC) && not r_write_pending_sc.read()) // check for an SC command (and check that its second flit is not already consumed) + { + if ( m_cmd_write_addr_fifo.rok() ) + { + size_t index = m_x[(vci_addr_t)(r_write_address.read())]; + bool sc_success = m_llsc_table.sc(r_write_address.read(),r_write_data[index].read()); + r_write_sc_fail = !sc_success; + + assert(m_cmd_write_eop_fifo.read() && "Error in VCI_MEM_CACHE : invalid packet format for SC command"); + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + r_write_pending_sc = true; + index = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 1; + r_write_data[index] = m_cmd_write_data_fifo.read(); + if (!sc_success) + { + r_write_fsm = WRITE_RSP; + break; + } + } + else break; + } + //else it is a TYPE_WRITE, need a simple sw access to the + // llsc_global_table + else + { + m_llsc_table.sw(r_write_address.read()); + } r_write_fsm = WRITE_DIR_LOCK; } @@ -1905,4 +1962,8 @@ << " count = " << entry.count << " is_cnt = " << entry.is_cnt << std::endl; + if((r_write_pktid.read() & 0x7) == TYPE_SC) + std::cout << " global_llsc_table SC access" << std::endl; + else + std::cout << " global_llsc_table SW access" << std::endl; } #endif @@ -1985,5 +2046,6 @@ // no_update is true when there is no need for coherence transaction - bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1)); + // (tests for sc requests) + bool no_update = ((r_write_count.read()==0) || ( owner && (r_write_count.read()==1) && (r_write_pktid.read() != TYPE_SC))); // write data in the cache if no coherence transaction @@ -2004,5 +2066,5 @@ } - if ( owner and not no_update ) + if ( owner and not no_update and (r_write_pktid.read() != TYPE_SC)) { r_write_count = r_write_count.read() - 1; @@ -2127,5 +2189,5 @@ case WRITE_UPT_REQ: { - // prepare the coherence ransaction for the INIT_CMD FSM + // prepare the coherence transaction for the INIT_CMD FSM // and write the first copy in the FIFO // send the request if only one copy @@ -2146,5 +2208,5 @@ for (size_t i=min ; i sw access to the llsc_global_table + m_llsc_table.sw(m_cmd_cas_addr_fifo.read()); + // test coherence request if(r_cas_count.read()) // replicated line @@ -4422,4 +4495,5 @@ << " / value = " << r_cas_wdata.read() << " / count = " << r_cas_count.read() << std::endl; + std::cout << " global_llsc_table SW access" << std::endl; } #endif @@ -6383,5 +6457,11 @@ case TGT_RSP_READ: p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); + if( ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL) + && (r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1)) ) + p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()-1].read(); + else if ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL) + p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read(); + else + p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); @@ -6391,10 +6471,18 @@ break; case TGT_RSP_WRITE: + /*if( ((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) ) + { + std::cout << "SC RSP / rsrcid = " << r_write_to_tgt_rsp_srcid.read() << " / rdata = " << r_write_to_tgt_rsp_sc_fail.read() << std::endl; + }*/ p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; + if( ((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) && r_write_to_tgt_rsp_sc_fail.read() ) + p_vci_tgt.rdata = 1; + else + p_vci_tgt.rdata = 0; p_vci_tgt.rsrcid = r_write_to_tgt_rsp_srcid.read(); p_vci_tgt.rtrdid = r_write_to_tgt_rsp_trdid.read(); p_vci_tgt.rpktid = r_write_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); + //p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); + p_vci_tgt.rerror = 0; p_vci_tgt.reop = true; break; @@ -6419,5 +6507,9 @@ case TGT_RSP_XRAM: p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); + if( ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL) + && (r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length-1)) ) + p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read(); + else + p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); @@ -6430,9 +6522,9 @@ case TGT_RSP_INIT: p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; + p_vci_tgt.rdata = 0; // Can be a CAS or SC rsp p_vci_tgt.rsrcid = r_init_rsp_to_tgt_rsp_srcid.read(); p_vci_tgt.rtrdid = r_init_rsp_to_tgt_rsp_trdid.read(); p_vci_tgt.rpktid = r_init_rsp_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; // Can be a CAS rsp + p_vci_tgt.rerror = 0; p_vci_tgt.reop = true; break;