- Timestamp:
- Feb 19, 2013, 1:07:47 PM (12 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/v5/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r296 r299 1202 1202 // They are handled as interrupts generated by the CC_RECEIVE FSM. 1203 1203 // - There is a coherence request when r_tgt_icache_req is set. 1204 // They are taken in IDLE, MISS_WAIT, UNC_WAITstates.1204 // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states. 1205 1205 // - There is a cleanup ack request when r_cleanup_icache_req is set. 1206 // They are taken in IDLE, MISS_ WAIT, UNC_WAIT states,1207 // and also in the MISS_SELECT and MISS_DATA_UPDT states.1206 // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, 1207 // MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states. 1208 1208 // - For both types of requests, actions associated to the pre-empted state 1209 1209 // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK … … 1265 1265 // 6/ uncacheable read miss => ICACHE_UNC_REQ 1266 1266 { 1267 // coherence requests1267 // coherence interrupt 1268 1268 if ( r_tgt_icache_req.read() ) 1269 1269 { … … 1273 1273 } 1274 1274 1275 // cleanup ack requests1275 // cleanup ack interrupt 1276 1276 if ( r_cleanup_icache_req.read() ) 1277 1277 { … … 1717 1717 if (m_ireq.valid) m_cost_ins_miss_frz++; 1718 1718 1719 // cleanup ack request1719 // cleanup ack interrupt 1720 1720 if ( r_cleanup_icache_req.read() ) 1721 1721 { … … 1780 1780 if (m_ireq.valid) m_cost_ins_miss_frz++; 1781 1781 1782 // cleanup ack interrupt 1783 if ( r_cleanup_icache_req.read() ) 1784 { 1785 r_icache_fsm_save = r_icache_fsm.read(); 1786 r_icache_fsm = ICACHE_CC_CLACK; 1787 break; 1788 } 1789 1782 1790 #ifdef INSTRUMENTATION 1783 1791 m_cpt_icache_dir_write++; … … 1805 1813 if (m_ireq.valid) m_cost_ins_miss_frz++; 1806 1814 1807 // coherence request1815 // coherence interrupt 1808 1816 if ( r_tgt_icache_req.read() ) 1809 1817 { … … 1813 1821 } 1814 1822 1815 // cleanup ack request1823 // cleanup ack interrupt 1816 1824 if ( r_cleanup_icache_req.read() ) 1817 1825 { … … 1838 1846 } 1839 1847 /////////////////////////// 1840 case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) if no pending 1841 // matching coherence request (r_icache_miss_inval) 1848 case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) 1842 1849 { 1843 1850 if ( m_ireq.valid ) m_cost_ins_miss_frz++; 1844 1851 1845 // cleanup ack request1852 // cleanup ack interrupt 1846 1853 if ( r_cleanup_icache_req.read() ) 1847 1854 { … … 1853 1860 if ( r_vci_rsp_fifo_icache.rok() ) // response available 1854 1861 { 1855 if ( r_icache_miss_inval.read() ) // Matching coherence request1856 // pop the FIFO, without cache update1857 {1858 #if DEBUG_ICACHE1859 if ( m_debug_icache_fsm )1860 {1861 std::cout << " <PROC " << name()1862 << " ICACHE_MISS_DATA_UPDT> Matching coherence request:"1863 << " pop the FIFO without cache update"1864 << " WORD = " << r_icache_miss_word.read() << std::endl;1865 }1866 #endif1867 }1868 else // No matching coherence request1869 // pop the FIFO and update the cache1870 {1871 1862 1872 1863 #ifdef INSTRUMENTATION 1873 1864 m_cpt_icache_data_write++; 1874 1865 #endif 1875 1876 1877 1878 1866 r_icache.write( r_icache_miss_way.read(), 1867 r_icache_miss_set.read(), 1868 r_icache_miss_word.read(), 1869 r_vci_rsp_fifo_icache.read() ); 1879 1870 #if DEBUG_ICACHE 1880 1871 if ( m_debug_icache_fsm ) … … 1888 1879 } 1889 1880 #endif 1890 }1891 1892 1881 vci_rsp_fifo_icache_get = true; 1893 1882 r_icache_miss_word = r_icache_miss_word.read() + 1; … … 1911 1900 if ( m_ireq.valid ) m_cost_ins_miss_frz++; 1912 1901 1913 // cleanup ack request 1902 // coherence interrupt 1903 if ( r_tgt_icache_req.read() ) 1904 { 1905 r_icache_fsm = ICACHE_CC_CHECK; 1906 r_icache_fsm_save = r_icache_fsm.read(); 1907 break; 1908 } 1909 1910 // cleanup ack interrupt 1914 1911 if ( r_cleanup_icache_req.read() ) 1915 1912 { … … 1919 1916 } 1920 1917 1921 if ( r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line1918 if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line 1922 1919 { 1923 1920 if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup … … 1978 1975 case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM 1979 1976 { 1980 // coherence request1977 // coherence interrupt 1981 1978 if ( r_tgt_icache_req.read() ) 1982 1979 { … … 1986 1983 } 1987 1984 1988 // cleanup ack request1985 // cleanup ack interrupt 1989 1986 if ( r_cleanup_icache_req.read() ) 1990 1987 { … … 2224 2221 // They are handled as interrupts generated by the CC_RECEIVE FSM. 2225 2222 // - There is a coherence request when r_tgt_dcache_req is set. 2226 // They are taken in IDLE, MISS_WAIT, UNC_WAIT, LL_WAIT and SC_WAIT states. 2223 // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT 2224 // and SC_WAIT states. 2227 2225 // - There is a cleanup acknowledge request when r_cleanup_dcache_req is set. 2228 // They are taken in IDLE, MISS_ WAIT, UNC_WAIT, LL_WAIT, SC_WAIT states,2229 // and also in the MISS_SELECT and MISS_DATA_UPDT.2226 // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT, 2227 // MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states. 2230 2228 // - For both types of requests, actions associated to the pre-empted state 2231 2229 // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK … … 2325 2323 // DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the 2326 2324 // dreq.valid (dreq) and r_dcache_updt_req (updt) signals: 2327 // dreq / updt / DTLB / DCACHE.DIR / DCACHE.D IR/2328 // 0 / 0 / NOP / NOP / NOP /2329 // 0 / 1 / NOP / NOP / WRITE /2330 // 1 / 0 / READ / READ / NOP /2331 // 1 / 1 / READ / READ / WRITE /2332 // Those two registers are set at each cycle rom the 3 signals2325 // dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA / 2326 // 0 / 0 / NOP / NOP / NOP / 2327 // 0 / 1 / NOP / NOP / WRITE / 2328 // 1 / 0 / READ / READ / NOP / 2329 // 1 / 1 / READ / READ / WRITE / 2330 // Those two registers are set at each cycle from the 3 signals 2333 2331 // updt_request, wbuf_request, wbuf_write_miss. 2334 2332 { … … 4019 4017 if ( m_dreq.valid) m_cost_data_miss_frz++; 4020 4018 4021 // cleanup ack request4019 // cleanup ack interrupt 4022 4020 if ( r_cleanup_dcache_req.read() ) 4023 4021 { … … 4082 4080 if ( m_dreq.valid) m_cost_data_miss_frz++; 4083 4081 4082 // cleanup ack interrupt 4083 if ( r_cleanup_dcache_req.read() ) 4084 { 4085 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4086 r_dcache_fsm = DCACHE_CC_CLACK; 4087 break; 4088 } 4089 4084 4090 size_t way = r_dcache_miss_way.read(); 4085 4091 size_t set = r_dcache_miss_set.read(); … … 4132 4138 if ( m_dreq.valid) m_cost_data_miss_frz++; 4133 4139 4134 // coherence request4140 // coherence interrupt 4135 4141 if ( r_tgt_dcache_req ) 4136 4142 { … … 4140 4146 } 4141 4147 4142 // cleanup ack request4148 // cleanup ack interrupt 4143 4149 if ( r_cleanup_dcache_req.read() ) 4144 4150 { … … 4210 4216 } 4211 4217 ////////////////////////// 4212 case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) if no pending 4213 // matching coherence request (r_dcache_miss_inval) 4218 case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) 4214 4219 { 4215 4220 if ( m_dreq.valid) m_cost_data_miss_frz++; 4216 4221 4217 // cleanup ack request4222 // cleanup ack interrupt 4218 4223 if ( r_cleanup_dcache_req.read() ) 4219 4224 { … … 4225 4230 if ( r_vci_rsp_fifo_dcache.rok() ) // one word available 4226 4231 { 4227 if ( r_dcache_miss_inval.read() ) // Matching coherence request4228 // pop the FIFO, without cache update4229 {4230 #if DEBUG_DCACHE4231 if ( m_debug_dcache_fsm )4232 {4233 std::cout << " <PROC " << name()4234 << " DCACHE_MISS_DATA_UPDT> Matching coherence request:"4235 << " pop the FIFO without cache update"4236 << " WORD = " << std::dec << r_dcache_miss_word.read() << std::endl;4237 }4238 #endif4239 }4240 else // No matching coherence request4241 // pop the FIFO and update the cache4242 {4243 4232 #ifdef INSTRUMENTATION 4244 4233 m_cpt_dcache_data_write++; … … 4259 4248 } 4260 4249 #endif 4261 }4262 4250 vci_rsp_fifo_dcache_get = true; 4263 4251 r_dcache_miss_word = r_dcache_miss_word.read() + 1; … … 4281 4269 if ( m_dreq.valid) m_cost_data_miss_frz++; 4282 4270 4283 // cleanup ack request 4271 // coherence interrupt 4272 if ( r_tgt_dcache_req ) 4273 { 4274 r_dcache_fsm_cc_save = r_dcache_fsm; 4275 r_dcache_fsm = DCACHE_CC_CHECK; 4276 break; 4277 } 4278 4279 // cleanup ack interrupt 4284 4280 if ( r_cleanup_dcache_req.read() ) 4285 4281 { … … 4289 4285 } 4290 4286 4291 if ( r_dcache_miss_clack.read() )4287 if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge 4292 4288 { 4293 4289 if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup … … 4355 4351 case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read 4356 4352 { 4357 // coherence request4353 // coherence interrupt 4358 4354 if ( r_tgt_dcache_req.read() ) 4359 4355 { … … 4363 4359 } 4364 4360 4365 // cleanup ack request4361 // cleanup ack interrupt 4366 4362 if ( r_cleanup_dcache_req.read() ) 4367 4363 { … … 4400 4396 case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction 4401 4397 { 4402 // coherence request4398 // coherence interrupt 4403 4399 if ( r_tgt_dcache_req.read() ) 4404 4400 { … … 4408 4404 } 4409 4405 4410 // cleanup ack request4406 // cleanup ack interrupt 4411 4407 if ( r_cleanup_dcache_req.read() ) 4412 4408 { … … 4454 4450 case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction 4455 4451 { 4456 // external coherence request4452 // coherence interrupt 4457 4453 if ( r_tgt_dcache_req.read() ) 4458 4454 { … … 4462 4458 } 4463 4459 4464 // cleanup ack request4460 // cleanup ack interrupt 4465 4461 if ( r_cleanup_dcache_req.read() ) 4466 4462 { … … 4546 4542 break; 4547 4543 } 4548 /////////////////////// ///4544 /////////////////////// 4549 4545 case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, 4550 4546 // and return to IDLE state when response is received. … … 4554 4550 // - if the CAS is a failure, we just retry the write. 4555 4551 { 4556 // external coherence request4552 // coherence interrupt 4557 4553 if ( r_tgt_dcache_req ) 4558 4554 { … … 4562 4558 } 4563 4559 4564 // cleanup ack request4560 // cleanup ack interrupt 4565 4561 if ( r_cleanup_dcache_req.read() ) 4566 4562 {
Note: See TracChangeset
for help on using the changeset viewer.
