Index: /branches/v5/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/v5/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 298) +++ /branches/v5/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 299) @@ -1202,8 +1202,8 @@ // They are handled as interrupts generated by the CC_RECEIVE FSM. // - There is a coherence request when r_tgt_icache_req is set. - // They are taken in IDLE, MISS_WAIT, UNC_WAIT states. + // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states. // - There is a cleanup ack request when r_cleanup_icache_req is set. - // They are taken in IDLE, MISS_WAIT, UNC_WAIT states, - // and also in the MISS_SELECT and MISS_DATA_UPDT states. + // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, + // MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states. // - For both types of requests, actions associated to the pre-empted state // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK @@ -1265,5 +1265,5 @@ // 6/ uncacheable read miss => ICACHE_UNC_REQ { - // coherence requests + // coherence interrupt if ( r_tgt_icache_req.read() ) { @@ -1273,5 +1273,5 @@ } - // cleanup ack requests + // cleanup ack interrupt if ( r_cleanup_icache_req.read() ) { @@ -1717,5 +1717,5 @@ if (m_ireq.valid) m_cost_ins_miss_frz++; - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_icache_req.read() ) { @@ -1780,4 +1780,12 @@ if (m_ireq.valid) m_cost_ins_miss_frz++; + // cleanup ack interrupt + if ( r_cleanup_icache_req.read() ) + { + r_icache_fsm_save = r_icache_fsm.read(); + r_icache_fsm = ICACHE_CC_CLACK; + break; + } + #ifdef INSTRUMENTATION m_cpt_icache_dir_write++; @@ -1805,5 +1813,5 @@ if (m_ireq.valid) m_cost_ins_miss_frz++; - // coherence request + // coherence interrupt if ( r_tgt_icache_req.read() ) { @@ -1813,5 +1821,5 @@ } - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_icache_req.read() ) { @@ -1838,10 +1846,9 @@ } /////////////////////////// - case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) if no pending - // matching coherence request (r_icache_miss_inval) + case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) { if ( m_ireq.valid ) m_cost_ins_miss_frz++; - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_icache_req.read() ) { @@ -1853,28 +1860,12 @@ if ( r_vci_rsp_fifo_icache.rok() ) // response available { - if ( r_icache_miss_inval.read() ) // Matching coherence request - // pop the FIFO, without cache update - { -#if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " Matching coherence request:" - << " pop the FIFO without cache update" - << " WORD = " << r_icache_miss_word.read() << std::endl; -} -#endif - } - else // No matching coherence request - // pop the FIFO and update the cache - { #ifdef INSTRUMENTATION m_cpt_icache_data_write++; #endif - r_icache.write( r_icache_miss_way.read(), - r_icache_miss_set.read(), - r_icache_miss_word.read(), - r_vci_rsp_fifo_icache.read() ); + r_icache.write( r_icache_miss_way.read(), + r_icache_miss_set.read(), + r_icache_miss_word.read(), + r_vci_rsp_fifo_icache.read() ); #if DEBUG_ICACHE if ( m_debug_icache_fsm ) @@ -1888,6 +1879,4 @@ } #endif - } - vci_rsp_fifo_icache_get = true; r_icache_miss_word = r_icache_miss_word.read() + 1; @@ -1911,5 +1900,13 @@ if ( m_ireq.valid ) m_cost_ins_miss_frz++; - // cleanup ack request + // coherence interrupt + if ( r_tgt_icache_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // cleanup ack interrupt if ( r_cleanup_icache_req.read() ) { @@ -1919,5 +1916,5 @@ } - if ( r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line + if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line { if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup @@ -1978,5 +1975,5 @@ case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM { - // coherence request + // coherence interrupt if ( r_tgt_icache_req.read() ) { @@ -1986,5 +1983,5 @@ } - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_icache_req.read() ) { @@ -2224,8 +2221,9 @@ // They are handled as interrupts generated by the CC_RECEIVE FSM. // - There is a coherence request when r_tgt_dcache_req is set. - // They are taken in IDLE, MISS_WAIT, UNC_WAIT, LL_WAIT and SC_WAIT states. + // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT + // and SC_WAIT states. // - There is a cleanup acknowledge request when r_cleanup_dcache_req is set. - // They are taken in IDLE, MISS_WAIT, UNC_WAIT, LL_WAIT, SC_WAIT states, - // and also in the MISS_SELECT and MISS_DATA_UPDT. + // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT, + // MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states. // - For both types of requests, actions associated to the pre-empted state // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK @@ -2325,10 +2323,10 @@ // DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the // dreq.valid (dreq) and r_dcache_updt_req (updt) signals: - // dreq / updt / DTLB / DCACHE.DIR / DCACHE.DIR / - // 0 / 0 / NOP / NOP / NOP / - // 0 / 1 / NOP / NOP / WRITE / - // 1 / 0 / READ / READ / NOP / - // 1 / 1 / READ / READ / WRITE / - // Those two registers are set at each cycle rom the 3 signals + // dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA / + // 0 / 0 / NOP / NOP / NOP / + // 0 / 1 / NOP / NOP / WRITE / + // 1 / 0 / READ / READ / NOP / + // 1 / 1 / READ / READ / WRITE / + // Those two registers are set at each cycle from the 3 signals // updt_request, wbuf_request, wbuf_write_miss. { @@ -4019,5 +4017,5 @@ if ( m_dreq.valid) m_cost_data_miss_frz++; - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_dcache_req.read() ) { @@ -4082,4 +4080,12 @@ if ( m_dreq.valid) m_cost_data_miss_frz++; + // cleanup ack interrupt + if ( r_cleanup_dcache_req.read() ) + { + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_CC_CLACK; + break; + } + size_t way = r_dcache_miss_way.read(); size_t set = r_dcache_miss_set.read(); @@ -4132,5 +4138,5 @@ if ( m_dreq.valid) m_cost_data_miss_frz++; - // coherence request + // coherence interrupt if ( r_tgt_dcache_req ) { @@ -4140,5 +4146,5 @@ } - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_dcache_req.read() ) { @@ -4210,10 +4216,9 @@ } ////////////////////////// - case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) if no pending - // matching coherence request (r_dcache_miss_inval) + case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) { if ( m_dreq.valid) m_cost_data_miss_frz++; - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_dcache_req.read() ) { @@ -4225,20 +4230,4 @@ if ( r_vci_rsp_fifo_dcache.rok() ) // one word available { - if ( r_dcache_miss_inval.read() ) // Matching coherence request - // pop the FIFO, without cache update - { -#if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Matching coherence request:" - << " pop the FIFO without cache update" - << " WORD = " << std::dec << r_dcache_miss_word.read() << std::endl; -} -#endif - } - else // No matching coherence request - // pop the FIFO and update the cache - { #ifdef INSTRUMENTATION m_cpt_dcache_data_write++; @@ -4259,5 +4248,4 @@ } #endif - } vci_rsp_fifo_dcache_get = true; r_dcache_miss_word = r_dcache_miss_word.read() + 1; @@ -4281,5 +4269,13 @@ if ( m_dreq.valid) m_cost_data_miss_frz++; - // cleanup ack request + // coherence interrupt + if ( r_tgt_dcache_req ) + { + r_dcache_fsm_cc_save = r_dcache_fsm; + r_dcache_fsm = DCACHE_CC_CHECK; + break; + } + + // cleanup ack interrupt if ( r_cleanup_dcache_req.read() ) { @@ -4289,5 +4285,5 @@ } - if ( r_dcache_miss_clack.read() ) + if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge { if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup @@ -4355,5 +4351,5 @@ case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read { - // coherence request + // coherence interrupt if ( r_tgt_dcache_req.read() ) { @@ -4363,5 +4359,5 @@ } - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_dcache_req.read() ) { @@ -4400,5 +4396,5 @@ case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction { - // coherence request + // coherence interrupt if ( r_tgt_dcache_req.read() ) { @@ -4408,5 +4404,5 @@ } - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_dcache_req.read() ) { @@ -4454,5 +4450,5 @@ case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction { - // external coherence request + // coherence interrupt if ( r_tgt_dcache_req.read() ) { @@ -4462,5 +4458,5 @@ } - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_dcache_req.read() ) { @@ -4546,5 +4542,5 @@ break; } - ////////////////////////// + /////////////////////// case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, // and return to IDLE state when response is received. @@ -4554,5 +4550,5 @@ // - if the CAS is a failure, we just retry the write. { - // external coherence request + // coherence interrupt if ( r_tgt_dcache_req ) { @@ -4562,5 +4558,5 @@ } - // cleanup ack request + // cleanup ack interrupt if ( r_cleanup_dcache_req.read() ) {